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Merge commit 'wd/master'

This commit is contained in:
Jon Loeliger 2008-06-06 10:48:31 -05:00
parent 2c289e320d 8155efbd7a
commit 1a247ba7fa
1223 changed files with 23634 additions and 14754 deletions
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12
CHANGELOG
View File

@ -7221,7 +7221,7 @@ Date: Mon Mar 3 11:57:23 2008 +0000
Originally pointed out by Laurent Pinchart <laurent.pinchart@tbox.biz>,
see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/22846
Signed-off-by: Bernhard Nemec <bnemec <at> ganssloser.com>
Signed-off-by: Bernhard Nemec <bnemec@ganssloser.com>
commit 84d0c2f1e39caff58bf765a7ab7c72da23c25ec8
Author: Kim B. Heino <Kim.Heino@bluegiga.com>
@ -8451,7 +8451,7 @@ Date: Mon Feb 18 14:01:56 2008 -0600
86xx: Convert sbc8641d to use libfdt.
This is the proper fix for a missing closing brace in the function
ft_cpu_setup() noticed by joe.hamman <at> embeddedspecialties.com.
ft_cpu_setup() noticed by joe.hamman@embeddedspecialties.com.
The ft_cpu_setup() function in mpc8641hpcn.c should have been
removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE,
but was missed. Only, the sbc8641d was nominally still using it.
@ -8846,7 +8846,7 @@ Date: Fri Feb 22 11:40:50 2008 +0000
We already have a vendor subdir for Atmel, so we should use it.
Signed-off-by: Haavard Skinnemoen <hskinnemoen <at> atmel.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
commit 6d0943a6be99977d6d853d51749e9963d68eb192
Author: Andreas Engel <andreas.engel@ericsson.com>
@ -8896,8 +8896,8 @@ Date: Thu Jan 3 21:15:56 2008 +0000
AT91CAP9 support : MACB changes
Signed-off-by: Stelian Pop <stelian <at> popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen <at> atmel.com>
Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
commit 6afcabf11d7321850f4feaadfee841488ace54c5
Author: Stelian Pop <stelian@popies.net>
@ -8913,7 +8913,7 @@ Date: Wed Jan 30 21:15:54 2008 +0000
AT91CAP9 support : cpu/ files
Signed-off-by: Stelian Pop <stelian <at> popies.net>
Signed-off-by: Stelian Pop <stelian@popies.net>
commit fa506a926cec348805143576c941f8e61b333cc0
Author: Stelian Pop <stelian@popies.net>

8
MAINTAINERS
View File

@ -204,6 +204,10 @@ Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
KUP4X MPC859
Gary Jennejohn <garyj@denx.de>
quad100hd PPC405EP
Murray Jensen <Murray.Jensen@csiro.au>
cogent_mpc8xx MPC8xx
@ -538,6 +542,9 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
at91cap9adk ARM926EJS (AT91CAP9 SoC)
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
Stefan Roese <sr@denx.de>
@ -695,6 +702,7 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
ATSTK1002 AT32AP7000
ATSTK1003 AT32AP7001
ATSTK1004 AT32AP7002
ATSTK1006 AT32AP7000
ATNGW100 AT32AP7000
#########################################################################

26
MAKEALL
View File

@ -219,6 +219,7 @@ LIST_4xx=" \
PMC405 \
PMC440 \
PPChameleonEVB \
quad100hd \
rainier \
sbc405 \
sc3 \
@ -354,6 +355,7 @@ LIST_85xx=" \
sbc8540 \
sbc8548 \
sbc8560 \
socrates \
stxgp3 \
stxssa \
TQM8540 \
@ -460,6 +462,9 @@ LIST_ARM9=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
ap920t \
ap922_XA10 \
@ -519,6 +524,24 @@ LIST_ARM11=" \
mx31ads \
"
#########################################################################
## AT91 Systems
#########################################################################
LIST_at91=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
at91sam9261ek \
at91sam9263ek \
at91sam9rlek \
cmc_pu2 \
csb637 \
kb9202 \
mp2usb \
m501sk \
"
#########################################################################
## Xscale Systems
#########################################################################
@ -696,6 +719,7 @@ LIST_avr32=" \
atstk1002 \
atstk1003 \
atstk1004 \
atstk1006 \
atngw100 \
"
@ -764,7 +788,7 @@ build_target() {
for arg in $@
do
case "$arg" in
arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa \
arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \
|avr32 \
|blackfin \
|coldfire \

20
Makefile
View File

@ -224,6 +224,7 @@ LIBS += drivers/mtd/libmtd.a
LIBS += drivers/mtd/nand/libnand.a
LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
LIBS += drivers/mtd/onenand/libonenand.a
LIBS += drivers/mtd/spi/libspi_flash.a
LIBS += drivers/net/libnet.a
LIBS += drivers/net/sk98lin/libsk98lin.a
LIBS += drivers/pci/libpci.a
@ -390,6 +391,7 @@ TAG_SUBDIRS += drivers/mtd
TAG_SUBDIRS += drivers/mtd/nand
TAG_SUBDIRS += drivers/mtd/nand_legacy
TAG_SUBDIRS += drivers/mtd/onenand
TAG_SUBDIRS += drivers/mtd/spi
TAG_SUBDIRS += drivers/net
TAG_SUBDIRS += drivers/net/sk98lin
TAG_SUBDIRS += drivers/pci
@ -1391,6 +1393,9 @@ PPChameleonEVB_HI_33_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
quad100hd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
sbc405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@ -2208,6 +2213,9 @@ sbc8560_66_config: unconfig
fi
@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
socrates_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
stxgp3_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
@ -2332,6 +2340,15 @@ shannon_config : unconfig
at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
at91sam9261ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
at91sam9263ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
at91sam9rlek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@ -2876,6 +2893,9 @@ atstk1003_config : unconfig
atstk1004_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
atstk1006_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
atngw100_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x

4
README
View File

@ -961,6 +961,10 @@ The following options need to be configured:
display); also select one of the supported displays
by defining one of these:
CONFIG_ATMEL_LCD:
HITACHI TX09D70VM1CCA, 3.5", 240x320.
CONFIG_NEC_NL6448AC33:
NEC NL6448AC33-18. Active, color, single scan.

2
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
View File

@ -71,7 +71,7 @@ __asm__(" .globl send_kb \n "
" li r3, 0x01 \n "
" bl send_kb \n "
" mtlr r10 \n "
" blr "
" blr \n "
);

409
board/MAI/AmigaOneG3SE/enet.c
View File

@ -274,7 +274,7 @@ struct descriptor { /* A generic descriptor. */
static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */
static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages */
static int rx_next = 0; /* RX descriptor ring pointer */
static int tx_next = 0; /* TX descriptor ring pointer */
static int tx_threshold;
@ -372,22 +372,20 @@ static int issue_and_wait(struct eth_device* dev, int command)
/* Determine network media type and set up 3com accordingly */
/* I think I'm going to start with something known first like 10baseT */
static int auto_negotiate(struct eth_device* dev)
static int auto_negotiate (struct eth_device *dev)
{
int i;
EL3WINDOW(dev, 1);
EL3WINDOW (dev, 1);
/* Wait for Auto negotiation to complete */
for (i = 0; i <= 1000; i++)
{
if (ETH_INW(dev, 2) & 0x04)
for (i = 0; i <= 1000; i++) {
if (ETH_INW (dev, 2) & 0x04)
break;
udelay(100);
udelay (100);
if (i == 1000)
{
PRINTF("Error: Auto negotiation failed\n");
if (i == 1000) {
PRINTF ("Error: Auto negotiation failed\n");
return 0;
}
}
@ -396,101 +394,99 @@ static int auto_negotiate(struct eth_device* dev)
return 1;
}
void eth_interrupt(struct eth_device *dev)
void eth_interrupt (struct eth_device *dev)
{
u16 status = ETH_STATUS(dev);
u16 status = ETH_STATUS (dev);
printf("eth0: status = 0x%04x\n", status);
printf ("eth0: status = 0x%04x\n", status);
if (!(status & IntLatch))
return;
if (status & (1<<6))
{
ETH_CMD(dev, AckIntr | (1<<6));
printf("Acknowledged Interrupt command\n");
if (status & (1 << 6)) {
ETH_CMD (dev, AckIntr | (1 << 6));
printf ("Acknowledged Interrupt command\n");
}
if (status & DownComplete)
{
ETH_CMD(dev, AckIntr | DownComplete);
printf("Acknowledged DownComplete\n");
if (status & DownComplete) {
ETH_CMD (dev, AckIntr | DownComplete);
printf ("Acknowledged DownComplete\n");
}
if (status & UpComplete)
{
ETH_CMD(dev, AckIntr | UpComplete);
printf("Acknowledged UpComplete\n");
if (status & UpComplete) {
ETH_CMD (dev, AckIntr | UpComplete);
printf ("Acknowledged UpComplete\n");
}
ETH_CMD(dev, AckIntr | IntLatch);
printf("Acknowledged IntLatch\n");
ETH_CMD (dev, AckIntr | IntLatch);
printf ("Acknowledged IntLatch\n");
}
int eth_3com_initialize(bd_t *bis)
int eth_3com_initialize (bd_t * bis)
{
u32 eth_iobase = 0, status;
int card_number = 0, ret;
struct eth_device* dev;
struct eth_device *dev;
pci_dev_t devno;
char *s;
s = getenv("3com_base");
s = getenv ("3com_base");
/* Find ethernet controller on the PCI bus */
if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
{
PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
if ((devno =
pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C,
0)) < 0) {
PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n");
goto Done;
}
if (s)
{
unsigned long base = atoi(s);
pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
if (s) {
unsigned long base = atoi (s);
pci_write_config_dword (devno, PCI_BASE_ADDRESS_0,
base | 0x01);
}
ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &eth_iobase);
ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &eth_iobase);
eth_iobase &= ~0xf;
PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_write_config_dword (devno, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled */
ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
ret = pci_read_config_dword (devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_IO))
{
printf("Error: Cannot enable IO access.\n");
if (!(status & PCI_COMMAND_IO)) {
printf ("Error: Cannot enable IO access.\n");
goto Done;
}
if (!(status & PCI_COMMAND_MEMORY))
{
printf("Error: Cannot enable MEMORY access.\n");
if (!(status & PCI_COMMAND_MEMORY)) {
printf ("Error: Cannot enable MEMORY access.\n");
goto Done;
}
if (!(status & PCI_COMMAND_MASTER))
{
printf("Error: Cannot enable Bus Mastering.\n");
if (!(status & PCI_COMMAND_MASTER)) {
printf ("Error: Cannot enable Bus Mastering.\n");
goto Done;
}
dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
dev = (struct eth_device *) malloc (sizeof (*dev)); /*struct eth_device)); */
sprintf(dev->name, "3Com 3c920c#%d", card_number);
sprintf (dev->name, "3Com 3c920c#%d", card_number);
dev->iobase = eth_iobase;
dev->priv = (void*) devno;
dev->priv = (void *) devno;
dev->init = eth_3com_init;
dev->halt = eth_3com_halt;
dev->send = eth_3com_send;
dev->recv = eth_3com_recv;
eth_register(dev);
eth_register (dev);
/* { */
/* char interrupt; */
@ -504,36 +500,32 @@ int eth_3com_initialize(bd_t *bis)
card_number++;
/* Set the latency timer for value */
s = getenv("3com_latency");
if (s)
{
ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
}
else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
s = getenv ("3com_latency");
if (s) {
ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER,
(unsigned char) atoi (s));
} else
ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a);
read_hw_addr(dev, bis); /* get the MAC address from Window 2*/
read_hw_addr (dev, bis); /* get the MAC address from Window 2 */
/* Reset the ethernet controller */
PRINTF ("Issuing reset command....\n");
if (!issue_and_wait(dev, TotalReset))
{
printf("Error: Cannot reset ethernet controller.\n");
if (!issue_and_wait (dev, TotalReset)) {
printf ("Error: Cannot reset ethernet controller.\n");
goto Done;
}
else
} else
PRINTF ("Ethernet controller reset.\n");
/* allocate memory for rx and tx rings */
if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
{
if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) {
PRINTF ("Cannot allocate memory for RX_RING.....\n");
goto Done;
}
if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
{
if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) {
PRINTF ("Cannot allocate memory for TX_RING.....\n");
goto Done;
}
@ -543,7 +535,7 @@ Done:
}
static int eth_3com_init(struct eth_device* dev, bd_t *bis)
static int eth_3com_init (struct eth_device *dev, bd_t * bis)
{
int i, status = 0;
int tx_cur, loop;
@ -553,209 +545,198 @@ static int eth_3com_init(struct eth_device* dev, bd_t *bis)
/* Determine what type of network the machine is connected to */
/* presently drops the connect to 10Mbps */
if (!auto_negotiate(dev))
{
printf("Error: Cannot determine network media.\n");
if (!auto_negotiate (dev)) {
printf ("Error: Cannot determine network media.\n");
goto Done;
}
issue_and_wait(dev, TxReset);
issue_and_wait(dev, RxReset|0x04);
issue_and_wait (dev, TxReset);
issue_and_wait (dev, RxReset | 0x04);
/* Switch to register set 7 for normal use. */
EL3WINDOW(dev, 7);
EL3WINDOW (dev, 7);
/* Initialize Rx and Tx rings */
init_rx_ring(dev);
purge_tx_ring(dev);
init_rx_ring (dev);
purge_tx_ring (dev);
ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
issue_and_wait(dev,SetTxStart|0x07ff);
issue_and_wait (dev, SetTxStart | 0x07ff);
/* Below sets which indication bits to be seen. */
status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
ETH_CMD(dev, status_enable);
status_enable =
SetStatusEnb | HostError | DownComplete | UpComplete | (1 <<
6);
ETH_CMD (dev, status_enable);
/* Below sets no bits are to cause an interrupt since this is just polling */
intr_enable = SetIntrEnb;
/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
ETH_CMD(dev, intr_enable);
ETH_OUTB(dev, 127, UpPoll);
ETH_CMD (dev, intr_enable);
ETH_OUTB (dev, 127, UpPoll);
/* Ack all pending events, and set active indicator mask */
ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
ETH_CMD(dev, intr_enable);
ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
ETH_CMD (dev, intr_enable);
/* Tell the adapter where the RX ring is located */
issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
ETH_CMD(dev, RxEnable); /* Enable the receiver. */
issue_and_wait(dev,UpUnstall);
issue_and_wait (dev, UpStall); /* Stall and set the UplistPtr */
ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr);
ETH_CMD (dev, RxEnable); /* Enable the receiver. */
issue_and_wait (dev, UpUnstall);
/* Send the Individual Address Setup frame */
tx_cur = tx_next;
tx_next = ((tx_next+1) % NUM_TX_DESC);
tx_next = ((tx_next + 1) % NUM_TX_DESC);
ias_cmd = (struct descriptor *)&tx_ring[tx_cur];
ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */
ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
ias_cmd->status = cpu_to_le32 (1 << 31); /* set DnIndicate bit. */
ias_cmd->next = 0;
ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
ias_cmd->length = cpu_to_le32(6 | LAST_FRAG);
ias_cmd->addr = cpu_to_le32 ((u32) & bis->bi_enetaddr[0]);
ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG);
/* Tell the adapter where the TX ring is located */
ETH_CMD(dev, TxEnable); /* Enable transmitter. */
issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
issue_and_wait(dev, DownUnstall);
for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
{
if (i >= TOUT_LOOP)
{
PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
ETH_CMD (dev, TxEnable); /* Enable transmitter. */
issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
issue_and_wait (dev, DownUnstall);
for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
if (i >= TOUT_LOOP) {
PRINTF ("TX Ring status (Init): 0x%4x\n",
le32_to_cpu (tx_ring[tx_cur].status));
PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev));
goto Done;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL (dev, 0, DownListPtr);
issue_and_wait (dev, DownUnstall);
}
status = 1;
Done:
return status;
}
int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
int eth_3com_send (struct eth_device *dev, volatile void *packet, int length)
{
int i, status = 0;
int tx_cur;
if (length <= 0)
{
PRINTF("eth: bad packet size: %d\n", length);
if (length <= 0) {
PRINTF ("eth: bad packet size: %d\n", length);
goto Done;
}
tx_cur = tx_next;
tx_next = (tx_next+1) % NUM_TX_DESC;
tx_next = (tx_next + 1) % NUM_TX_DESC;
tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */
tx_ring[tx_cur].status = cpu_to_le32 (1 << 31); /* set DnIndicate bit */
tx_ring[tx_cur].next = 0;
tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet));
tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG);
tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet));
tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG);
/* Send the packet */
issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */
ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
issue_and_wait(dev, DownUnstall);
issue_and_wait (dev, DownStall); /* stall and set the DownListPtr */
ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
issue_and_wait (dev, DownUnstall);
for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
{
if (i >= TOUT_LOOP)
{
PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
if (i >= TOUT_LOOP) {
PRINTF ("TX Ring status (send): 0x%4x\n",
le32_to_cpu (tx_ring[tx_cur].status));
goto Done;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL (dev, 0, DownListPtr);
issue_and_wait (dev, DownUnstall);
}
status=1;
Done:
status = 1;
Done:
return status;
}
void PrintPacket (uchar *packet, int length)
void PrintPacket (uchar * packet, int length)
{
int loop;
uchar *ptr;
int loop;
uchar *ptr;
printf ("Printing packet of length %x.\n\n", length);
ptr = packet;
for (loop = 1; loop <= length; loop++)
{
for (loop = 1; loop <= length; loop++) {
printf ("%2x ", *ptr++);
if ((loop % 40)== 0)
if ((loop % 40) == 0)
printf ("\n");
}
}
int eth_3com_recv(struct eth_device* dev)
int eth_3com_recv (struct eth_device *dev)
{
u16 stat = 0;
u32 status;
int rx_prev, length = 0;
while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */
while (!(ETH_STATUS (dev) & UpComplete)) /* wait on receipt of packet */
;
status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
while (status & (1<<15))
{
while (status & (1 << 15)) {
/* A packet has been received */
if (status & (1<<15))
{
if (status & (1 << 15)) {
/* A valid frame received */
length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
/* Pass the packet up to the protocol layers */
NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
NetReceive ((uchar *)
le32_to_cpu (rx_ring[rx_next].addr),
length);
rx_ring[rx_next].status = 0; /* clear the status word */
ETH_CMD(dev, AckIntr | UpComplete);
issue_and_wait(dev, UpUnstall);
}
else
if (stat & HostError)
{
ETH_CMD (dev, AckIntr | UpComplete);
issue_and_wait (dev, UpUnstall);
} else if (stat & HostError) {
/* There was an error */
printf("Rx error status: 0x%4x\n", stat);
init_rx_ring(dev);
printf ("Rx error status: 0x%4x\n", stat);
init_rx_ring (dev);
goto Done;
}
rx_prev = rx_next;
rx_next = (rx_next + 1) % NUM_RX_DESC;
stat = ETH_STATUS(dev); /* register status */
status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
stat = ETH_STATUS (dev); /* register status */
status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
}
Done:
return length;
}
void eth_3com_halt(struct eth_device* dev)
void eth_3com_halt (struct eth_device *dev)
{
if (!(dev->iobase))
{
if (!(dev->iobase)) {
goto Done;
}
issue_and_wait(dev, DownStall); /* shut down transmit and receive */
issue_and_wait(dev, UpStall);
issue_and_wait(dev, RxDisable);
issue_and_wait(dev, TxDisable);
issue_and_wait (dev, DownStall); /* shut down transmit and receive */
issue_and_wait (dev, UpStall);
issue_and_wait (dev, RxDisable);
issue_and_wait (dev, TxDisable);
/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
/* free(rx_ring); */
@ -764,33 +745,33 @@ Done:
return;
}
static void init_rx_ring(struct eth_device* dev)
static void init_rx_ring (struct eth_device *dev)
{
int i;
PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
issue_and_wait(dev, UpStall);
PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
issue_and_wait (dev, UpStall);
for (i = 0; i < NUM_RX_DESC; i++)
{
rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
for (i = 0; i < NUM_RX_DESC; i++) {
rx_ring[i].next =
cpu_to_le32 (((u32) &
rx_ring[(i + 1) % NUM_RX_DESC]));
rx_ring[i].status = 0;
rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0]));
rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0]));
rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG);
}
rx_next = 0;
}
static void purge_tx_ring(struct eth_device* dev)
static void purge_tx_ring (struct eth_device *dev)
{
int i;
PRINTF("Purging tx_ring.\n");
PRINTF ("Purging tx_ring.\n");
tx_next = 0;
for (i = 0; i < NUM_TX_DESC; i++)
{
for (i = 0; i < NUM_TX_DESC; i++) {
tx_ring[i].next = 0;
tx_ring[i].status = 0;
tx_ring[i].addr = 0;
@ -798,7 +779,7 @@ static void purge_tx_ring(struct eth_device* dev)
}
}
static void read_hw_addr(struct eth_device* dev, bd_t *bis)
static void read_hw_addr (struct eth_device *dev, bd_t * bis)
{
u8 hw_addr[ETH_ALEN];
unsigned int eeprom[0x40];
@ -807,18 +788,16 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
/* Read the station address from the EEPROM. */
EL3WINDOW(dev, 0);
for (i = 0; i < 0x40; i++)
{
ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
EL3WINDOW (dev, 0);
for (i = 0; i < 0x40; i++) {
ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd);
/* Pause for at least 162 us. for the read to take place. */
for (timer = 10; timer >= 0; timer--)
{
udelay(162);
if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
for (timer = 10; timer >= 0; timer--) {
udelay (162);
if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0)
break;
}
eeprom[i] = ETH_INW(dev, Wn0EepromData);
eeprom[i] = ETH_INW (dev, Wn0EepromData);
}
/* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
@ -828,30 +807,27 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
checksum = (checksum ^ (checksum >> 8)) & 0xff;
if (checksum != 0xbb)
printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n",
checksum);
for (i = 0, j = 0; i < 3; i++)
{
hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
for (i = 0, j = 0; i < 3; i++) {
hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff);
hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff);
}
/* MAC Address is in window 2, write value from EEPROM to window 2 */
EL3WINDOW(dev, 2);
EL3WINDOW (dev, 2);
for (i = 0; i < 6; i++)
ETH_OUTB(dev, hw_addr[i], i);
ETH_OUTB (dev, hw_addr[i], i);
for (j = 0; j < ETH_ALEN; j+=2)
{
hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff);
hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
for (j = 0; j < ETH_ALEN; j += 2) {
hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff);
hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff);
}
for (i=0;i<ETH_ALEN;i++)
{
if (hw_addr[i] != bis->bi_enetaddr[i])
{
for (i = 0; i < ETH_ALEN; i++) {
if (hw_addr[i] != bis->bi_enetaddr[i]) {
/* printf("Warning: HW address don't match:\n"); */
/* printf("Address in 3Com Window 2 is " */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
@ -864,20 +840,25 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
/* goto Done; */
char buffer[256];
if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
{
sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
if (bis->bi_enetaddr[0] == 0
&& bis->bi_enetaddr[1] == 0
&& bis->bi_enetaddr[2] == 0
&& bis->bi_enetaddr[3] == 0
&& bis->bi_enetaddr[4] == 0
&& bis->bi_enetaddr[5] == 0) {
sprintf (buffer,
"%02X:%02X:%02X:%02X:%02X:%02X",
hw_addr[0], hw_addr[1], hw_addr[2],
hw_addr[3], hw_addr[4], hw_addr[5]);
setenv("ethaddr", buffer);
setenv ("ethaddr", buffer);
}
}
}
for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
for (i = 0; i < ETH_ALEN; i++)
dev->enetaddr[i] = hw_addr[i];
Done:
return;

285
board/MAI/AmigaOneG3SE/ps2kbd.c
View File

@ -194,21 +194,22 @@ static unsigned char kbd_ctrl_xlate[] = {
* Init
******************************************************************/
int isa_kbd_init(void)
int isa_kbd_init (void)
{
char* result;
result=kbd_initialize();
if (result != NULL)
{
result = kbd_initialize();
char *result;
result = kbd_initialize ();
if (result != NULL) {
result = kbd_initialize ();
}
if(result==NULL) {
printf("AT Keyboard initialized\n");
irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
if (result == NULL) {
printf ("AT Keyboard initialized\n");
irq_install_handler (KBD_INTERRUPT,
(interrupt_handler_t *) kbd_interrupt,
NULL);
return (1);
}
else {
printf("%s\n",result);
} else {
printf ("%s\n", result);
return (-1);
}
}
@ -301,7 +302,6 @@ int kbd_getc(void)
}
/* set LEDs */
void kbd_set_leds(void)
@ -322,140 +322,139 @@ void kbd_set_leds(void)
kbd_send_data(leds);
}
void handle_keyboard_event(unsigned char scancode)
void handle_keyboard_event (unsigned char scancode)
{
unsigned char keycode;
/* Convert scancode to keycode */
PRINTF("scancode %x\n",scancode);
if(scancode==0xe0) {
e0=1; /* special charakters */
PRINTF ("scancode %x\n", scancode);
if (scancode == 0xe0) {
e0 = 1; /* special charakters */
return;
}
if(e0==1) {
e0=0; /* delete flag */
if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */
((scancode&0x7F)==0x1D)|| /* the right alt key */
((scancode&0x7F)==0x35)|| /* the right '/' key */
((scancode&0x7F)==0x1C)|| /* the right enter key */
((scancode)==0x48)|| /* arrow up */
((scancode)==0x50)|| /* arrow down */
((scancode)==0x4b)|| /* arrow left */
((scancode)==0x4d))) /* arrow right */
if (e0 == 1) {
e0 = 0; /* delete flag */
if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
((scancode & 0x7F) == 0x1D) || /* the right alt key */
((scancode & 0x7F) == 0x35) || /* the right '/' key */
((scancode & 0x7F) == 0x1C) || /* the right enter key */
((scancode) == 0x48) || /* arrow up */
((scancode) == 0x50) || /* arrow down */
((scancode) == 0x4b) || /* arrow left */
((scancode) == 0x4d)))
/* arrow right */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
switch(scancode)
{
switch (scancode) {
case 0x48:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('A');
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('A');
return;
case 0x50:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('B');
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('B');
return;
case 0x4b:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('D');
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('D');
return;
case 0x4D:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('C');
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('C');
return;
case 0x58: /* F12 key */
if (ctrl == 1)
{
if (ctrl == 1) {
extern int console_changed;
setenv("stdin", DEVNAME);
setenv("stdout", "vga");
setenv ("stdin", DEVNAME);
setenv ("stdout", "vga");
console_changed = 1;
}
return;
case 0x2A:
case 0x36: /* shift pressed */
shift=1;
shift = 1;
return; /* do nothing else */
case 0xAA:
case 0xB6: /* shift released */
shift=0;
shift = 0;
return; /* do nothing else */
case 0x38: /* alt pressed */
alt=1;
alt = 1;
return; /* do nothing else */
case 0xB8: /* alt released */
alt=0;
alt = 0;
return; /* do nothing else */
case 0x1d: /* ctrl pressed */
ctrl=1;
ctrl = 1;
return; /* do nothing else */
case 0x9d: /* ctrl released */
ctrl=0;
ctrl = 0;
return; /* do nothing else */
case 0x46: /* scrollock pressed */
scroll_lock=~scroll_lock;
kbd_set_leds();
scroll_lock = ~scroll_lock;
kbd_set_leds ();
return; /* do nothing else */
case 0x3A: /* capslock pressed */
caps_lock=~caps_lock;
kbd_set_leds();
caps_lock = ~caps_lock;
kbd_set_leds ();
return;
case 0x45: /* numlock pressed */
num_lock=~num_lock;
kbd_set_leds();
num_lock = ~num_lock;
kbd_set_leds ();
return;
case 0xC6: /* scroll lock released */
case 0xC5: /* num lock released */
case 0xBA: /* caps lock released */
return; /* just swallow */
}
if((scancode&0x80)==0x80) /* key released */
if ((scancode & 0x80) == 0x80) /* key released */
return;
/* now, decide which table we need */
if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF("unkown scancode %X\n",scancode);
if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown scancode %X\n", scancode);
return; /* swallow it */
}
/* setup plain code first */
keycode=kbd_plain_xlate[scancode];
if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown caps-locked scancode %X\n",scancode);
keycode = kbd_plain_xlate[scancode];
if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown caps-locked scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
if(keycode<'A') { /* we only want the alphas capital */
keycode=kbd_plain_xlate[scancode];
keycode = kbd_shift_xlate[scancode];
if (keycode < 'A') { /* we only want the alphas capital */
keycode = kbd_plain_xlate[scancode];
}
}
if(shift==1) { /* shift overwrites caps_lock */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown shifted scancode %X\n",scancode);
if (shift == 1) { /* shift overwrites caps_lock */
if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown shifted scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
keycode = kbd_shift_xlate[scancode];
}
if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF("unkown ctrl scancode %X\n",scancode);
if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown ctrl scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_ctrl_xlate[scancode];
keycode = kbd_ctrl_xlate[scancode];
}
/* check if valid keycode */
if(keycode==0xff) {
PRINTF("unkown scancode %X\n",scancode);
if (keycode == 0xff) {
PRINTF ("unkown scancode %X\n", scancode);
return; /* swallow unknown codes */
}
kbd_put_queue(keycode);
PRINTF("%x\n",keycode);
kbd_put_queue (keycode);
PRINTF ("%x\n", keycode);
}
/*
@ -463,34 +462,31 @@ void handle_keyboard_event(unsigned char scancode)
* appropriate action.
*
*/
unsigned char handle_kbd_event(void)
unsigned char handle_kbd_event (void)
{
unsigned char status = kbd_read_status();
unsigned char status = kbd_read_status ();
unsigned int work = 10000;
while ((--work > 0) && (status & KBD_STAT_OBF)) {
unsigned char scancode;
scancode = kbd_read_input();
scancode = kbd_read_input ();
/* Error bytes must be ignored to make the
Synaptics touchpads compaq use work */
/* Ignore error bytes */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
{
if (status & KBD_STAT_MOUSE_OBF)
; /* not supported: handle_mouse_event(scancode); */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) {
if (status & KBD_STAT_MOUSE_OBF); /* not supported: handle_mouse_event(scancode); */
else
handle_keyboard_event(scancode);
handle_keyboard_event (scancode);
}
status = kbd_read_status();
status = kbd_read_status ();
}
if (!work)
PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
PRINTF ("pc_keyb: controller jammed (0x%02X).\n", status);
return status;
}
/******************************************************************************
* Lowlevel Part of keyboard section
*/
@ -529,64 +525,65 @@ int kbd_read_data(void)
return val;
}
int kbd_wait_for_input(void)
int kbd_wait_for_input (void)
{
unsigned long timeout;
int val;
timeout = KBD_TIMEOUT;
val=kbd_read_data();
while(val < 0)
{
if(timeout--==0)
val = kbd_read_data ();
while (val < 0) {
if (timeout-- == 0)
return -1;
udelay(1000);
val=kbd_read_data();
udelay (1000);
val = kbd_read_data ();
}
return val;
}
int kb_wait(void)
int kb_wait (void)
{
unsigned long timeout = KBC_TIMEOUT * 10;
do {
unsigned char status = handle_kbd_event();
unsigned char status = handle_kbd_event ();
if (!(status & KBD_STAT_IBF))
return 0; /* ok */
udelay(1000);
udelay (1000);
timeout--;
} while (timeout);
return 1;
}
void kbd_write_command_w(int data)
void kbd_write_command_w (int data)
{
if(kb_wait())
PRINTF("timeout in kbd_write_command_w\n");
kbd_write_command(data);
if (kb_wait ())
PRINTF ("timeout in kbd_write_command_w\n");
kbd_write_command (data);
}
void kbd_write_output_w(int data)
void kbd_write_output_w (int data)
{
if(kb_wait())
PRINTF("timeout in kbd_write_output_w\n");
kbd_write_output(data);
if (kb_wait ())
PRINTF ("timeout in kbd_write_output_w\n");
kbd_write_output (data);
}
void kbd_send_data(unsigned char data)
void kbd_send_data (unsigned char data)
{
unsigned char status;
i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */
kbd_write_output_w(data);
status = kbd_wait_for_input();
i8259_mask_irq (KBD_INTERRUPT); /* disable interrupt */
kbd_write_output_w (data);
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */
i8259_unmask_irq (KBD_INTERRUPT); /* enable interrupt */
}
char * kbd_initialize(void)
char *kbd_initialize (void)
{
int status;
@ -597,22 +594,22 @@ char * kbd_initialize(void)
* This seems to be the only way to get it going.
* If the test is successful a x55 is placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_SELF_TEST);
if (kbd_wait_for_input() != 0x55)
kbd_write_command_w (KBD_CCMD_SELF_TEST);
if (kbd_wait_for_input () != 0x55)
return "Kbd: failed self test";
/*
* Perform a keyboard interface test. This causes the controller
* to test the keyboard clock and data lines. The results of the
* test are placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_KBD_TEST);
if (kbd_wait_for_input() != 0x00)
kbd_write_command_w (KBD_CCMD_KBD_TEST);
if (kbd_wait_for_input () != 0x00)
return "Kbd: interface failed self test";
/*
* Enable the keyboard by allowing the keyboard clock to run.
*/
kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
status = kbd_wait_for_input();
kbd_write_command_w (KBD_CCMD_KBD_ENABLE);
status = kbd_wait_for_input ();
/*
* Reset keyboard. If the read times out
* then the assumption is that no keyboard is
@ -622,17 +619,16 @@ char * kbd_initialize(void)
* Set up to try again if the keyboard asks for RESEND.
*/
do {
kbd_write_output_w(KBD_CMD_RESET);
status = kbd_wait_for_input();
kbd_write_output_w (KBD_CMD_RESET);
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
{
PRINTF("status: %X\n",status);
if (status != KBD_REPLY_RESEND) {
PRINTF ("status: %X\n", status);
return "Kbd: reset failed, no ACK";
}
} while (1);
if (kbd_wait_for_input() != KBD_REPLY_POR)
if (kbd_wait_for_input () != KBD_REPLY_POR)
return "Kbd: reset failed, no POR";
/*
@ -642,44 +638,43 @@ char * kbd_initialize(void)
* Set up to try again if the keyboard asks for RESEND.
*/
do {
kbd_write_output_w(KBD_CMD_DISABLE);
status = kbd_wait_for_input();
kbd_write_output_w (KBD_CMD_DISABLE);
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
return "Kbd: disable keyboard: no ACK";
} while (1);
kbd_write_command_w(KBD_CCMD_WRITE_MODE);
kbd_write_output_w(KBD_MODE_KBD_INT
kbd_write_command_w (KBD_CCMD_WRITE_MODE);
kbd_write_output_w (KBD_MODE_KBD_INT
| KBD_MODE_SYS
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
| KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC);
/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w(KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
kbd_write_command_w (KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input () & KBD_MODE_KCC)) {
/*
* If the controller does not support conversion,
* Set the keyboard to scan-code set 1.
*/
kbd_write_output_w(0xF0);
kbd_wait_for_input();
kbd_write_output_w(0x01);
kbd_wait_for_input();
kbd_write_output_w (0xF0);
kbd_wait_for_input ();
kbd_write_output_w (0x01);
kbd_wait_for_input ();
}
kbd_write_output_w(KBD_CMD_ENABLE);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
kbd_write_output_w (KBD_CMD_ENABLE);
if (kbd_wait_for_input () != KBD_REPLY_ACK)
return "Kbd: enable keyboard: no ACK";
/*
* Finally, set the typematic rate to maximum.
*/
kbd_write_output_w(KBD_CMD_SET_RATE);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
kbd_write_output_w (KBD_CMD_SET_RATE);
if (kbd_wait_for_input () != KBD_REPLY_ACK)
return "Kbd: Set rate: no ACK";
kbd_write_output_w(0x00);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
kbd_write_output_w (0x00);
if (kbd_wait_for_input () != KBD_REPLY_ACK)
return "Kbd: Set rate: no ACK";
return NULL;
}

40
board/MAI/menu/menu.h
View File

@ -4,8 +4,7 @@
/* A single menu */
typedef void (*menu_finish_callback)(struct menu_s *menu);
typedef struct menu_s
{
typedef struct menu_s {
char *name; /* Menu name */
int num_options; /* Number of options in this menu */
int flags; /* Various flags - see below */
@ -28,8 +27,7 @@ typedef struct menu_s
char *name; \
char *help; \
int id; \
void *sys; \
void *sys;
/*
* Menu option types.
@ -110,42 +108,34 @@ typedef struct menu_text_s
#define MENU_SELECTION_TYPE 3
typedef struct menu_select_option_s
{
typedef struct menu_select_option_s {
char *map_from; /* Map this variable contents ... */
char *map_to; /* ... to this menu text and vice versa */
} menu_select_option_t;
typedef struct menu_select_s
{
OPTION_PREAMBLE
int num_options; /* Number of mappings */
typedef struct menu_select_s {
OPTION_PREAMBLE int num_options; /* Number of mappings */
menu_select_option_t **options;
/* Option list array */
} menu_select_t;
#define MENU_ROUTINE_TYPE 4
typedef void (*menu_routine_callback)(struct menu_routine_s *);
typedef void (*menu_routine_callback) (struct menu_routine_s *);
typedef struct menu_routine_s
{
OPTION_PREAMBLE
menu_routine_callback callback;
typedef struct menu_routine_s {
OPTION_PREAMBLE menu_routine_callback callback;
/* routine to be called */
void *user_data; /* User data, don't care for system */
} menu_routine_t;
#define MENU_CUSTOM_TYPE 5
typedef void (*menu_custom_draw)(struct menu_custom_s *);
typedef void (*menu_custom_key)(struct menu_custom_s *, int);
typedef void (*menu_custom_draw) (struct menu_custom_s *);
typedef void (*menu_custom_key) (struct menu_custom_s *, int);
typedef struct menu_custom_s
{
OPTION_PREAMBLE
menu_custom_draw drawfunc;
typedef struct menu_custom_s {
OPTION_PREAMBLE menu_custom_draw drawfunc;
menu_custom_key keyfunc;
void *user_data;
} menu_custom_t;
@ -153,10 +143,8 @@ typedef struct menu_custom_s
/*
* The menu option superstructure
*/
typedef struct menu_option_s
{
union
{
typedef struct menu_option_s {
union {
menu_submenu_t m_sub_menu;
menu_boolean_t m_boolean;
menu_text_t m_text;

4
board/RPXlite_dw/flash.c
View File

@ -178,8 +178,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = addr[0] ;
switch (value & 0x00FF00FF) {
case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;

5
board/ads5121/Makefile
View File

@ -23,9 +23,14 @@
include $(TOPDIR)/config.mk
$(shell mkdir -p $(OBJTREE)/board/freescale/common)
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o
COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS := $(COBJS-y)

62
board/ads5121/ads5121.c
View File

@ -39,17 +39,35 @@
#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
CLOCK_SCCR2_SPDIF_EN | \
CLOCK_SCCR2_DIU_EN | \
CLOCK_SCCR2_I2C_EN)
#define CSAW_START(start) ((start) & 0xFFFF0000)
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
#define MPC5121_IOCTL_PSC6_0 (0x284/4)
#define MPC5121_IO_DIU_START (0x288/4)
#define MPC5121_IO_DIU_END (0x2fc/4)
/* Functional pin muxing */
#define MPC5121_IO_FUNC1 (0 << 7)
#define MPC5121_IO_FUNC2 (1 << 7)
#define MPC5121_IO_FUNC3 (2 << 7)
#define MPC5121_IO_FUNC4 (3 << 7)
#define MPC5121_IO_ST (1 << 2)
#define MPC5121_IO_DS_1 (0)
#define MPC5121_IO_DS_2 (1)
#define MPC5121_IO_DS_3 (2)
#define MPC5121_IO_DS_4 (3)
long int fixed_sdram(void);
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 lpcaw;
u32 lpcaw, tmp32;
volatile ioctrl512x_t *ioctl = &(im->io_ctrl);
int i;
/*
* Initialize Local Window for the CPLD registers access (CS2 selects
@ -81,6 +99,16 @@ int board_early_init_f (void)
im->clk.sccr[0] = SCCR1_CLOCKS_EN;
im->clk.sccr[1] = SCCR2_CLOCKS_EN;
/* Configure DIU clock pin */
tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0];
tmp32 &= ~0x1ff;
tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4;
ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32;
/* Initialize IO pins (pin mux) for DIU function */
for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++)
ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4);
return 0;
}
@ -186,6 +214,38 @@ long int fixed_sdram (void)
return msize;
}
int misc_init_r(void)
{
u8 tmp_val;
/* Using this for DIU init before the driver in linux takes over
* Enable the TFP410 Encoder (I2C address 0x38)
*/
i2c_set_bus_num(2);
tmp_val = 0xBF;
i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
#ifdef CONFIG_FSL_DIU_FB
#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
ads5121_diu_init();
#endif
#endif
return 0;
}
int checkboard (void)
{
ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);

165
board/ads5121/ads5121_diu.c Normal file
View File

@ -0,0 +1,165 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#ifdef CONFIG_FSL_DIU_FB
#include "../freescale/common/pixis.h"
#include "../freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
#include <devices.h>
#include <video_fb.h>
#endif
extern unsigned int FSL_Logo_BMP[];
static int xres, yres;
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile clk512x_t *clk = &immap->clk;
volatile unsigned int *clkdvdr = &clk->scfr[0];
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0) * 4;
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
temp = *clkdvdr & 0xFFFFFF00;
*clkdvdr = temp | (pixval & 0x1F);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
}
int ads5121_diu_init(void)
{
unsigned int pixel_format;
xres = 1024;
yres = 768;
pixel_format = 0x88883316;
return fsl_diu_init(xres, pixel_format, 0,
(unsigned char *)FSL_Logo_BMP);
}
int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
{
unsigned int addr;
if (argc < 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (!strncmp(argv[1], "init", 4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
fsl_diu_clear_screen();
drv_video_init();
#else
return ads5121_diu_init();
#endif
} else {
addr = simple_strtoul(argv[1], NULL, 16);
fsl_diu_clear_screen();
fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
}
return 0;
}
U_BOOT_CMD(
diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
"diufb init | addr - Init or Display BMP file\n",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"
);
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
/*
* The Graphic Device
*/
GraphicDevice ctfb;
void *video_hw_init(void)
{
GraphicDevice *pGD = (GraphicDevice *) &ctfb;
struct fb_info *info;
if (ads5121_diu_init() < 0)
return;
/* fill in Graphic device struct */
sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
xres, yres, 32, 64, 60);
pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
pGD->winSizeX = xres;
pGD->winSizeY = yres - info->logo_height;
pGD->plnSizeX = pGD->winSizeX;
pGD->plnSizeY = pGD->winSizeY;
pGD->gdfBytesPP = 4;
pGD->gdfIndex = GDF_32BIT_X888RGB;
pGD->isaBase = 0;
pGD->pciBase = 0;
pGD->memSize = info->screen_size - info->logo_size;
/* Cursor Start Address */
pGD->dprBase = 0;
pGD->vprBase = 0;
pGD->cprBase = 0;
return (void *)pGD;
}
/**
* Set the LUT
*
* @index: color number
* @r: red
* @b: blue
* @g: green
*/
void video_set_lut
(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
{
return;
}
#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
#endif /* CONFIG_FSL_DIU_FB */

16
board/amcc/taihu/taihu.c
View File

@ -165,16 +165,20 @@ unsigned char spi_read(void)
return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
}
void taihu_spi_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
gpio_write_bit(SPI_CS_GPIO0, cs);
return bus == 0 && cs == 0;
}
spi_chipsel_type spi_chipsel[]= {
taihu_spi_chipsel
};
void spi_cs_activate(struct spi_slave *slave)
{
gpio_write_bit(SPI_CS_GPIO0, 1);
}
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
gpio_write_bit(SPI_CS_GPIO0, 0);
}
#ifdef CONFIG_PCI
static unsigned char int_lines[32] = {

4
board/atmel/at91cap9adk/Makefile
View File

@ -2,6 +2,10 @@
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#

100
board/atmel/at91cap9adk/at91cap9adk.c
View File

@ -30,6 +30,8 @@
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
@ -70,6 +72,33 @@ static void at91cap9_serial_hw_init(void)
#endif
}
static void at91cap9_slowclock_hw_init(void)
{
/*
* On AT91CAP9 revC CPUs, the slow clock can be based on an
* internal impreciseRC oscillator or an external 32kHz oscillator.
* Switch to the latter.
*/
#define ARCH_ID_AT91CAP9_REVB 0x399
#define ARCH_ID_AT91CAP9_REVC 0x601
if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
unsigned i, tmp = at91_sys_read(AT91_SCKCR);
if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
extern void timer_init(void);
timer_init();
tmp |= AT91CAP9_SCKCR_OSC32EN;
at91_sys_write(AT91_SCKCR, tmp);
for (i = 0; i < 1200; i++)
udelay(1000);
tmp |= AT91CAP9_SCKCR_OSCSEL_32;
at91_sys_write(AT91_SCKCR, tmp);
udelay(200);
tmp &= ~AT91CAP9_SCKCR_RCEN;
at91_sys_write(AT91_SCKCR, tmp);
}
}
}
static void at91cap9_nor_hw_init(void)
{
unsigned long csa;
@ -116,7 +145,12 @@ static void at91cap9_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
@ -228,6 +262,65 @@ static void at91cap9_uhp_hw_init(void)
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91CAP9_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
}
static void at91cap9_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
gd->fb_base = 0;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
@ -239,6 +332,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91cap9_serial_hw_init();
at91cap9_slowclock_hw_init();
at91cap9_nor_hw_init();
#ifdef CONFIG_CMD_NAND
at91cap9_nand_hw_init();
@ -252,7 +346,9 @@ int board_init(void)
#ifdef CONFIG_USB_OHCI_NEW
at91cap9_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91cap9_lcd_hw_init();
#endif
return 0;
}

3
board/atmel/at91cap9adk/nand.c
View File

@ -63,6 +63,9 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;

4
board/atmel/at91sam9260ek/Makefile
View File

@ -2,6 +2,10 @@
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#

7
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@ -90,7 +90,12 @@ static void at91sam9260ek_nand_hw_init(void)
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);

3
board/atmel/at91sam9260ek/nand.c
View File

@ -68,6 +68,9 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20;

57
board/atmel/at91sam9260ek/u-boot.lds
View File

@ -1,57 +0,0 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm926ejs/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

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#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9261ek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9261ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PC15, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PC14, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9261ek_spi_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
}
#endif
#ifdef CONFIG_DRIVER_DM9000
static void at91sam9261ek_dm9000_hw_init(void)
{
/* Configure SMC CS2 for DM9000 */
at91_sys_write(AT91_SMC_SETUP(2),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(2),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
at91_sys_write(AT91_SMC_CYCLE(2),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(2),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_(1));
/* Configure Reset signal as output */
at91_set_gpio_output(AT91_PIN_PC10, 0);
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PC11, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9261_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
}
static void at91sam9261ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
gd->fb_base = AT91SAM9261_SRAM_BASE;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9261EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9261ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9261ek_spi_hw_init();
#endif
#ifdef CONFIG_DRIVER_DM9000
at91sam9261ek_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9261ek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

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TEXT_BASE = 0x23f00000

78
board/atmel/at91sam9261ek/led.c Normal file
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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PA23 /* this is the power led */
#define GREEN_LED AT91_PIN_PA13 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PC15);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
nand->dev_ready = at91sam9261ek_nand_ready;
nand->chip_delay = 20;
return 0;
}

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/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

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#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9263ek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9263ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9263ek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(2));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOCDE);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PA22, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PD15, 1);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9263ek_spi_hw_init(void)
{
at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
}
#endif
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
/*
* Disable pull-up on:
* RXDV (PC25) => PHY normal mode (not Test mode)
* ERX0 (PE25) => PHY ADDR0
* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
#endif
}
#endif
#ifdef CONFIG_USB_OHCI_NEW
static void at91sam9263ek_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
at91_set_gpio_output(AT91_PIN_PA21, 0);
at91_set_gpio_output(AT91_PIN_PA24, 0);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9263_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
}
static void at91sam9263ek_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
gd->fb_base = AT91SAM9263_SRAM0_BASE;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9263ek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9263ek_spi_hw_init();
#endif
#ifdef CONFIG_MACB
at91sam9263ek_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91sam9263ek_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9263ek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif

1
board/atmel/at91sam9263ek/config.mk Normal file
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@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

78
board/atmel/at91sam9263ek/led.c Normal file
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@ -0,0 +1,78 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PB7 /* this is the power led */
#define GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

79
board/atmel/at91sam9263ek/nand.c Normal file
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@ -0,0 +1,79 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PD15, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PA22);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
nand->dev_ready = at91sam9263ek_nand_ready;
nand->chip_delay = 20;
return 0;
}

39
cpu/at32ap/pm.c → board/atmel/at91sam9263ek/partition.c
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@ -1,8 +1,6 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -18,25 +16,24 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
#ifdef CFG_POWER_MANAGER
#include <asm/errno.h>
#include <asm/io.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
#include <asm/arch/memory-map.h>
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
#include "sm.h"
#ifdef CONFIG_PLL
#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
#else
#define MAIN_CLK_RATE (CFG_OSC0_HZ)
#endif
DECLARE_GLOBAL_DATA_PTR;
#endif /* CFG_POWER_MANAGER */
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

57
board/atmel/at91sam9rlek/Makefile Normal file
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@ -0,0 +1,57 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian.pop@leadtechdesign.com>
# Lead Tech Design <www.leadtechdesign.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9rlek.o
COBJS-y += led.o
COBJS-y += partition.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

215
board/atmel/at91sam9rlek/at91sam9rlek.c Normal file
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/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91sam9rl_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9rlek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
#ifdef CONFIG_CMD_NAND
static void at91sam9rlek_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
AT91_SMC_DBW_8 |
#endif
AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
/* Configure RDY/BSY */
at91_set_gpio_input(AT91_PIN_PD17, 1);
/* Enable NandFlash */
at91_set_gpio_output(AT91_PIN_PB6, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91sam9rlek_spi_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PA28, 0); /* SPI0_NPCS0 */
at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_clk: 4965000,
vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
vl_bpix: 3,
vl_tft: 1,
vl_hsync_len: 5,
vl_left_margin: 1,
vl_right_margin:33,
vl_vsync_len: 1,
vl_upper_margin:1,
vl_lower_margin:0,
mmio: AT91SAM9RL_LCDC_BASE,
};
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
}
static void at91sam9rlek_lcd_hw_init(void)
{
at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
gd->fb_base = 0;
}
#endif
int board_init(void)
{
/* Enable Ctrlc */
console_init_f();
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
at91sam9rlek_serial_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9rlek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91sam9rlek_spi_hw_init();
#endif
#ifdef CONFIG_LCD
at91sam9rlek_lcd_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}

1
board/atmel/at91sam9rlek/config.mk Normal file
View File

@ -0,0 +1 @@
TEXT_BASE = 0x23f00000

77
board/atmel/at91sam9rlek/led.c Normal file
View File

@ -0,0 +1,77 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91_PIN_PD14 /* this is the power led */
#define GREEN_LED AT91_PIN_PD15 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */
void red_LED_on(void)
{
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
at91_set_gpio_value(YELLOW_LED, 1);
}

79
board/atmel/at91sam9rlek/nand.c Normal file
View File

@ -0,0 +1,79 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PB6, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PB6, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(AT91_PIN_PD17);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
nand->dev_ready = at91sam9rlek_nand_ready;
nand->chip_delay = 20;
return 0;
}

39
board/atmel/at91sam9rlek/partition.c Normal file
View File

@ -0,0 +1,39 @@
/*
* (C) Copyright 2008
* Ulf Samuelsson <ulf@atmel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};

27
board/atmel/atngw100/atngw100.c
View File

@ -25,12 +25,12 @@
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
#include <asm/arch/hmatrix.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_info sdram = {
.phys_addr = CFG_SDRAM_BASE,
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_16BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
@ -47,8 +47,8 @@ static const struct sdram_info sdram = {
int board_early_init_f(void)
{
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(SFR4, 1 << 1);
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
gpio_enable_ebi();
gpio_enable_usart1();
@ -66,7 +66,22 @@ int board_early_init_f(void)
long int initdram(int board_type)
{
return sdram_init(&sdram);
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
if (expected_size != actual_size)
printf("Warning: Only %u of %u MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
void board_init_info(void)

9
board/atmel/atngw100/u-boot.lds
View File

@ -29,17 +29,10 @@ SECTIONS
. = 0;
_text = .;
.text : {
*(.exception.text)
*(.text)
*(.text.*)
}
. = ALIGN(32);
__flashprog_start = .;
.flashprog : {
*(.flashprog)
}
. = ALIGN(32);
__flashprog_end = .;
_etext = .;
.rodata : {

54
board/atmel/atstk1000/atstk1000.c
View File

@ -25,13 +25,39 @@
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
#include <asm/arch/hmatrix.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_info sdram = {
.phys_addr = CFG_SDRAM_BASE,
static const struct sdram_config sdram_config = {
#if defined(CONFIG_ATSTK1006)
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 2,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 4,
.txsr = 7,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
#else
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
#ifdef CONFIG_ATSTK1004
.data_bits = SDRAM_DATA_16BIT,
#else
.data_bits = SDRAM_DATA_32BIT,
#endif
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
.row_bits = 12,
#else
.row_bits = 11,
#endif
.col_bits = 8,
.bank_bits = 2,
.cas = 3,
@ -43,12 +69,13 @@ static const struct sdram_info sdram = {
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
#endif
};
int board_early_init_f(void)
{
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
hmatrix2_writel(SFR4, 1 << 1);
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
gpio_enable_ebi();
gpio_enable_usart1();
@ -65,7 +92,22 @@ int board_early_init_f(void)
long int initdram(int board_type)
{
return sdram_init(&sdram);
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
if (expected_size != actual_size)
printf("Warning: Only %u of %u MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
void board_init_info(void)

6
board/atmel/atstk1000/flash.c
View File

@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
flash_info_t flash_info[1];
static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
static void flash_identify(uint16_t *flash, flash_info_t *info)
{
unsigned long flags;
@ -76,7 +76,7 @@ void flash_print_info(flash_info_t *info)
info->size >> 10, info->sector_count);
}
int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
unsigned long flags;
unsigned long start_time;
@ -154,7 +154,7 @@ int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
return ERR_OK;
}
int __flashprog write_buff(flash_info_t *info, uchar *src,
int write_buff(flash_info_t *info, uchar *src,
ulong addr, ulong count)
{
unsigned long flags;

9
board/atmel/atstk1000/u-boot.lds
View File

@ -29,17 +29,10 @@ SECTIONS
. = 0;
_text = .;
.text : {
*(.exception.text)
*(.text)
*(.text.*)
}
. = ALIGN(32);
__flashprog_start = .;
.flashprog : {
*(.flashprog)
}
. = ALIGN(32);
__flashprog_end = .;
_etext = .;
.rodata : {

2
board/dbau1x00/dbau1x00.c
View File

@ -52,7 +52,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
switch (proc_id >> 24) {
case 0:

107
board/eric/flash.c
View File

@ -981,22 +981,22 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 2 - Flash not erased
*/
#ifndef CFG_FLASH_16BIT
static int write_word (flash_info_t *info, ulong dest, ulong data)
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start,barf;
vu_long *addr = (vu_long *) (info->start[0]);
ulong start, barf;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
if ((*((vu_long *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
if(info->flash_id > FLASH_AMD_COMP) {
if (info->flash_id > FLASH_AMD_COMP) {
/* AMD stuff */
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
@ -1005,42 +1005,47 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* intel stuff */
*addr = 0x00400040;
}
*((vu_long *)dest) = data;
*((vu_long *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
if(info->flash_id > FLASH_AMD_COMP) {
if (info->flash_id > FLASH_AMD_COMP) {
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
while ((*((vu_long *) dest) & 0x00800080) !=
(data & 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
} else {
while(!(addr[0] & 0x00800080)){ /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
while (!(addr[0] & 0x00800080)) { /* wait for error or finish */
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
if( addr[0] & 0x003A003A) { /* check for error */
if (addr[0] & 0x003A003A) { /* check for error */
barf = addr[0] & 0x003A0000;
if( barf ) {
barf >>=16;
if (barf) {
barf >>= 16;
} else {
barf = addr[0] & 0x0000003A;
}
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
return(2);
printf ("\nFlash write error at address %lx\n",
(unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
@ -1048,25 +1053,25 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
return (0);
}
}
#else
static int write_short (flash_info_t *info, ulong dest, ushort data)
static int write_short (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short*)(info->start[0]);
ulong start,barf;
vu_short *addr = (vu_short *) (info->start[0]);
ulong start, barf;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_short *)dest) & data) != data) {
if ((*((vu_short *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
if(info->flash_id < FLASH_AMD_COMP) {
if (info->flash_id < FLASH_AMD_COMP) {
/* AMD stuff */
addr[0x0555] = 0x00AA;
addr[0x02AA] = 0x0055;
@ -1076,53 +1081,51 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
*addr = 0x00D0;
*addr = 0x0040;
}
*((vu_short *)dest) = data;
*((vu_short *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
if(info->flash_id < FLASH_AMD_COMP) {
if (info->flash_id < FLASH_AMD_COMP) {
/* AMD stuff */
while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
} else {
/* intel stuff */
while(!(addr[0] & 0x0080)){ /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
if( addr[0] & 0x003A) { /* check for error */
if (addr[0] & 0x003A) { /* check for error */
barf = addr[0] & 0x003A;
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
return(2);
printf ("\nFlash write error at address %lx\n",
(unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
*addr = 0x00B0;
*addr = 0x0070;
while(!(addr[0] & 0x0080)){ /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
*addr = 0x00FF;
}
return (0);
}
#endif
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------*/

21
board/esd/cpci750/sdram_init.c
View File

@ -134,16 +134,15 @@ typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL
/* SDRAM/DDR information struct */
typedef struct _gtMemoryDimmInfo
{
typedef struct _gtMemoryDimmInfo {
MEMORY_TYPE memoryType;
unsigned int numOfRowAddresses;
unsigned int numOfColAddresses;
unsigned int numOfModuleBanks;
unsigned int dataWidth;
VOLTAGE_INTERFACE voltageInterface;
unsigned int errorCheckType; /* ECC , PARITY..*/
unsigned int sdramWidth; /* 4,8,16 or 32 */;
unsigned int errorCheckType; /* ECC , PARITY.. */
unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
unsigned int minClkDelay;
unsigned int burstLengthSupported;
@ -151,7 +150,7 @@ typedef struct _gtMemoryDimmInfo
unsigned int suportedCasLatencies;
unsigned int RefreshInterval;
unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns)*/
unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
MAX_CL_SUPPORTED_SD maxClSupported_SD;
unsigned int moduleBankDensity;
@ -183,20 +182,20 @@ typedef struct _gtMemoryDimmInfo
int dataInputHoldTime; /* LoP left of point (measured in ns) */
/* tAC times for highest 2nd and 3rd highest CAS Latency values */
unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns)*/
unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns)*/
unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns)*/
unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns)*/
unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns)*/
unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns)*/
unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
/* Parameters calculated from
the extracted DIMM information */

418
board/esteem192e/flash.c
View File

@ -38,49 +38,49 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
* Functions
*/
ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
#ifndef CONFIG_FLASH_16BIT
static int write_word (flash_info_t *info, ulong dest, ulong data);
static int write_word (flash_info_t * info, ulong dest, ulong data);
#else
static int write_short (flash_info_t *info, ulong dest, ushort data);
static int write_short (flash_info_t * info, ulong dest, ushort data);
#endif
/*int flash_write (uchar *, ulong, ulong); */
/*flash_info_t *addr2info (ulong); */
static void flash_get_offsets (ulong base, flash_info_t *info);
static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0, size_b1;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM,
&flash_info[0]);
size_b0 =
flash_get_size ((volatile FLASH_WORD_SIZE *)
FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
}
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM,
&flash_info[1]);
size_b1 =
flash_get_size ((volatile FLASH_WORD_SIZE *)
FLASH_BASE1_PRELIM, &flash_info[1]);
if (size_b1 > size_b0) {
printf ("## ERROR: "
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
size_b1, size_b1<<20,
size_b0, size_b0<<20
);
size_b1, size_b1 << 20, size_b0, size_b0 << 20);
flash_info[0].flash_id = FLASH_UNKNOWN;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[0].sector_count = -1;
@ -92,40 +92,44 @@ unsigned long flash_init (void)
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;*/
memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE,
size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE,
&flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
(void) flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
if (size_b1) {
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
memctl->memc_or1 =
CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
memctl->memc_br1 =
(CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
/*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
BR_MS_GPCM | BR_V;*/
BR_MS_GPCM | BR_V; */
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0),
size_b1 =
flash_get_size ((volatile FLASH_WORD_SIZE
*) (CFG_FLASH_BASE + size_b0),
&flash_info[1]);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
(void) flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[1]);
CFG_MONITOR_BASE + monitor_flash_len -
1, &flash_info[1]);
#endif
} else {
memctl->memc_br1 = 0; /* invalidate bank */
@ -142,7 +146,7 @@ unsigned long flash_init (void)
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
@ -161,17 +165,18 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[6] = base + 0x00018000;
info->start[7] = base + 0x0001C000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x000E0000;
info->start[i] =
base + (i * 0x00020000) - 0x000E0000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
info->start[i] =
base + (i * 0x00020000) - 0x00060000;
}
}
#else
@ -185,17 +190,18 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[6] = base + 0x0000C000;
info->start[7] = base + 0x0000E000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00070000;
info->start[i] =
base + (i * 0x00010000) - 0x00070000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
}
#endif
@ -254,12 +260,12 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
void flash_print_info (flash_info_t * info)
{
int i;
uchar *boottype;
uchar botboot[]=", bottom boot sect)\n";
uchar topboot[]=", top boot sector)\n";
uchar botboot[] = ", bottom boot sect)\n";
uchar topboot[] = ", top boot sector)\n";
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
@ -267,59 +273,88 @@ void flash_print_info (flash_info_t *info)
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
case FLASH_MAN_SST:
printf ("SST ");
break;
case FLASH_MAN_STM:
printf ("STM ");
break;
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
if (info->flash_id & 0x0001 ) {
if (info->flash_id & 0x0001) {
boottype = botboot;
} else {
boottype = topboot;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype);
case FLASH_AM400B:
printf ("AM29LV400B (4 Mbit%s", boottype);
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype);
case FLASH_AM400T:
printf ("AM29LV400T (4 Mbit%s", boottype);
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype);
case FLASH_AM800B:
printf ("AM29LV800B (8 Mbit%s", boottype);
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype);
case FLASH_AM800T:
printf ("AM29LV800T (8 Mbit%s", boottype);
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype);
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit%s", boottype);
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype);
case FLASH_AM160T:
printf ("AM29LV160T (16 Mbit%s", boottype);
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype);
case FLASH_AM320B:
printf ("AM29LV320B (32 Mbit%s", boottype);
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype);
case FLASH_AM320T:
printf ("AM29LV320T (32 Mbit%s", boottype);
break;
case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype);
case FLASH_INTEL800B:
printf ("INTEL28F800B (8 Mbit%s", boottype);
break;
case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype);
case FLASH_INTEL800T:
printf ("INTEL28F800T (8 Mbit%s", boottype);
break;
case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype);
case FLASH_INTEL160B:
printf ("INTEL28F160B (16 Mbit%s", boottype);
break;
case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype);
case FLASH_INTEL160T:
printf ("INTEL28F160T (16 Mbit%s", boottype);
break;
case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype);
case FLASH_INTEL320B:
printf ("INTEL28F320B (32 Mbit%s", boottype);
break;
case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype);
case FLASH_INTEL320T:
printf ("INTEL28F320T (32 Mbit%s", boottype);
break;
#if 0 /* enable when devices are available */
case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype);
case FLASH_INTEL640B:
printf ("INTEL28F640B (64 Mbit%s", boottype);
break;
case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype);
case FLASH_INTEL640T:
printf ("INTEL28F640T (64 Mbit%s", boottype);
break;
#endif
default: printf ("Unknown Chip Type\n");
default:
printf ("Unknown Chip Type\n");
break;
}
@ -327,13 +362,11 @@ void flash_print_info (flash_info_t *info)
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
@ -349,10 +382,10 @@ void flash_print_info (flash_info_t *info)
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
{
short i;
ulong base = (ulong)addr;
ulong base = (ulong) addr;
FLASH_WORD_SIZE value;
/* Write auto select command: read Manufacturer ID */
@ -367,7 +400,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
*/
addr[0x0000] = 0x00900090;
if(addr[0x0000] != 0x00890089){
if (addr[0x0000] != 0x00890089) {
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00900090;
@ -381,7 +414,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
addr[0x0000] = 0x0090;
if(addr[0x0000] != 0x0089){
if (addr[0x0000] != 0x0089) {
addr[0x0555] = 0x00AA;
addr[0x02AA] = 0x0055;
addr[0x0555] = 0x0090;
@ -536,17 +569,18 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
info->start[6] = base + 0x00018000;
info->start[7] = base + 0x0001C000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x000E0000;
info->start[i] =
base + (i * 0x00020000) - 0x000E0000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
info->start[i] =
base + (i * 0x00020000) - 0x00060000;
}
}
#else
@ -560,17 +594,18 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
info->start[6] = base + 0x0000C000;
info->start[7] = base + 0x0000E000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00070000;
info->start[i] =
base + (i * 0x00010000) - 0x00070000;
}
}
else {
} else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
}
#endif
@ -628,7 +663,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
info->protect[i] = addr[2] & 1;
}
@ -636,8 +671,8 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
*addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
} else {
*addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
@ -651,10 +686,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
volatile FLASH_WORD_SIZE *addr =
(volatile FLASH_WORD_SIZE *) (info->start[0]);
int flag, prot, sect, l_sect, barf;
ulong start, now, last;
int rcode = 0;
@ -670,21 +706,20 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
if ((info->flash_id == FLASH_UNKNOWN) ||
((info->flash_id > FLASH_AMD_COMP) &&
( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
@ -692,8 +727,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
if(info->flash_id < FLASH_AMD_COMP) {
flag = disable_interrupts ();
if (info->flash_id < FLASH_AMD_COMP) {
#ifndef CONFIG_FLASH_16BIT
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
@ -708,9 +743,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
addr[0x02AA] = 0x0055;
#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
addr[0] = (0x00300030 & FLASH_ID_MASK);
l_sect = sect;
}
@ -718,7 +753,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
@ -731,11 +766,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
start = get_timer (0);
last = start;
addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
(0x00800080&FLASH_ID_MASK) )
{
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
(0x00800080 & FLASH_ID_MASK)) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -746,50 +780,53 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
}
DONE:
DONE:
/* reset to read mode */
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
} else {
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
barf = 0;
#ifndef CONFIG_FLASH_16BIT
addr = (vu_long*)(info->start[sect]);
addr = (vu_long *) (info->start[sect]);
addr[0] = 0x00200020;
addr[0] = 0x00D000D0;
while(!(addr[0] & 0x00800080)); /* wait for error or finish */
if( addr[0] & 0x003A003A) { /* check for error */
while (!(addr[0] & 0x00800080)); /* wait for error or finish */
if (addr[0] & 0x003A003A) { /* check for error */
barf = addr[0] & 0x003A0000;
if( barf ) {
barf >>=16;
if (barf) {
barf >>= 16;
} else {
barf = addr[0] & 0x0000003A;
}
}
#else
addr = (vu_short*)(info->start[sect]);
addr = (vu_short *) (info->start[sect]);
addr[0] = 0x0020;
addr[0] = 0x00D0;
while(!(addr[0] & 0x0080)); /* wait for error or finish */
if( addr[0] & 0x003A) /* check for error */
while (!(addr[0] & 0x0080)); /* wait for error or finish */
if (addr[0] & 0x003A) /* check for error */
barf = addr[0] & 0x003A;
#endif
if(barf) {
printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if((barf & 0x0030) == 0x0030)
printf("Command Sequence error.\n");
if((barf & 0x0030) == 0x0020)
printf("Block Erase error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
if (barf) {
printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if ((barf & 0x0030) == 0x0030)
printf ("Command Sequence error.\n");
if ((barf & 0x0030) == 0x0020)
printf ("Block Erase error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
rcode = 1;
} else printf(".");
} else
printf (".");
l_sect = sect;
}
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
}
@ -809,7 +846,7 @@ DONE:
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
#ifndef CONFIG_FLASH_16BIT
ulong cp, wp, data;
@ -830,19 +867,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i<4 && cnt>0; ++i) {
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
@ -853,10 +890,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
@ -871,15 +908,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word(info, wp, data));
return (write_word (info, wp, data));
#else
wp = (addr & ~1); /* get lower word aligned address */
@ -891,7 +928,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
data = 0;
data = (data << 8) | *src++;
--cnt;
if ((rc = write_short(info, wp, data)) != 0) {
if ((rc = write_short (info, wp, data)) != 0) {
return (rc);
}
wp += 2;
@ -903,7 +940,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
/* l = 0; used for debuging */
while (cnt >= 2) {
data = 0;
for (i=0; i<2; ++i) {
for (i = 0; i < 2; ++i) {
data = (data << 8) | *src++;
}
@ -912,7 +949,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
l = 1;
} used for debuging */
if ((rc = write_short(info, wp, data)) != 0) {
if ((rc = write_short (info, wp, data)) != 0) {
return (rc);
}
wp += 2;
@ -927,15 +964,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<2; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; i < 2; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_short(info, wp, data));
return (write_short (info, wp, data));
#endif
@ -948,22 +985,22 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 2 - Flash not erased
*/
#ifndef CONFIG_FLASH_16BIT
static int write_word (flash_info_t *info, ulong dest, ulong data)
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start,barf;
vu_long *addr = (vu_long *) (info->start[0]);
ulong start, barf;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
if ((*((vu_long *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
if(info->flash_id > FLASH_AMD_COMP) {
if (info->flash_id > FLASH_AMD_COMP) {
/* AMD stuff */
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
@ -972,42 +1009,46 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* intel stuff */
*addr = 0x00400040;
}
*((vu_long *)dest) = data;
*((vu_long *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
if(info->flash_id > FLASH_AMD_COMP) {
if (info->flash_id > FLASH_AMD_COMP) {
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
while ((*((vu_long *) dest) & 0x00800080) !=
(data & 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
} else {
while(!(addr[0] & 0x00800080)){ /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
while (!(addr[0] & 0x00800080)) { /* wait for error or finish */
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
if( addr[0] & 0x003A003A) { /* check for error */
if (addr[0] & 0x003A003A) { /* check for error */
barf = addr[0] & 0x003A0000;
if( barf ) {
barf >>=16;
if (barf) {
barf >>= 16;
} else {
barf = addr[0] & 0x0000003A;
}
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
return(2);
printf ("\nFlash write error at address %lx\n", (unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
@ -1015,25 +1056,25 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
return (0);
}
}
#else
static int write_short (flash_info_t *info, ulong dest, ushort data)
static int write_short (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short*)(info->start[0]);
ulong start,barf;
vu_short *addr = (vu_short *) (info->start[0]);
ulong start, barf;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_short *)dest) & data) != data) {
if ((*((vu_short *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
if(info->flash_id < FLASH_AMD_COMP) {
if (info->flash_id < FLASH_AMD_COMP) {
/* AMD stuff */
addr[0x0555] = 0x00AA;
addr[0x02AA] = 0x0055;
@ -1043,53 +1084,52 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
*addr = 0x00D0;
*addr = 0x0040;
}
*((vu_short *)dest) = data;
*((vu_short *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
if(info->flash_id < FLASH_AMD_COMP) {
if (info->flash_id < FLASH_AMD_COMP) {
/* AMD stuff */
while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
} else {
/* intel stuff */
while(!(addr[0] & 0x0080)){ /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
if( addr[0] & 0x003A) { /* check for error */
if (addr[0] & 0x003A) { /* check for error */
barf = addr[0] & 0x003A;
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
return(2);
printf ("\nFlash write error at address %lx\n",
(unsigned long) dest);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if (barf & 0x0010)
printf ("Programming error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
return (2);
}
*addr = 0x00B0;
*addr = 0x0070;
while(!(addr[0] & 0x0080)){ /* wait for error or finish */
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
while (!(addr[0] & 0x0080)) { /* wait for error or finish */
if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
return (1);
}
*addr = 0x00FF;
}
return (0);
}
#endif
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------*/

101
board/freescale/common/fsl_diu_fb.c
View File

@ -29,12 +29,6 @@
#include "fsl_diu_fb.h"
#ifdef DEBUG
#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
#else
#define DPRINTF(fmt, args...)
#endif
struct fb_videomode {
const char *name; /* optional */
unsigned int refresh; /* optional */
@ -163,8 +157,6 @@ struct diu_addr {
unsigned int offset;
};
#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */
/*
* Modes of operation of DIU
*/
@ -197,7 +189,7 @@ static void disable_lcdc(void);
static int fsl_diu_enable_panel(struct fb_info *info);
static int fsl_diu_disable_panel(struct fb_info *info);
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
static u32 get_busfreq(void);
void diu_set_pixel_clock(unsigned int pixclock);
int fsl_diu_init(int xres,
unsigned int pixel_format,
@ -209,15 +201,11 @@ int fsl_diu_init(int xres,
struct diu *hw;
struct fb_info *info = &fsl_fb_info;
struct fb_var_screeninfo *var = &info->var;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned char *gamma_table_base;
unsigned int i, j;
unsigned long speed_ccb, temp, pixval;
DPRINTF("Enter fsl_diu_init\n");
dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
debug("Enter fsl_diu_init\n");
dr.diu_reg = (struct diu *) (CFG_DIU_ADDR);
hw = (struct diu *) dr.diu_reg;
disable_lcdc();
@ -230,10 +218,10 @@ int fsl_diu_init(int xres,
if (0 == fb_initialized) {
allocate_buf(&gamma, 768, 32);
DPRINTF("gamma is allocated @ 0x%x\n",
debug("gamma is allocated @ 0x%x\n",
(unsigned int)gamma.paddr);
allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
DPRINTF("curosr is allocated @ 0x%x\n",
debug("curosr is allocated @ 0x%x\n",
(unsigned int)cursor.paddr);
/* create a dummy fb and dummy ad */
@ -261,8 +249,8 @@ int fsl_diu_init(int xres,
dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
/* read mode info */
var->xres = fsl_diu_mode_db->xres;
@ -300,7 +288,7 @@ int fsl_diu_init(int xres,
ad->ckmin_b = 255;
gamma_table_base = gamma.paddr;
DPRINTF("gamma_table_base is allocated @ 0x%x\n",
debug("gamma_table_base is allocated @ 0x%x\n",
(unsigned int)gamma_table_base);
/* Prep for DIU init - gamma table */
@ -310,7 +298,7 @@ int fsl_diu_init(int xres,
*gamma_table_base++ = j;
if (gamma_fix == 1) { /* fix the gamma */
DPRINTF("Fix gamma table\n");
debug("Fix gamma table\n");
gamma_table_base = gamma.paddr;
for (i = 0; i < 256*3; i++) {
gamma_table_base[i] = (gamma_table_base[i] << 2)
@ -318,7 +306,7 @@ int fsl_diu_init(int xres,
}
}
DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
debug("update-lcdc: HW - %p\n Disabling DIU\n", hw);
/* Program DIU registers */
@ -336,37 +324,22 @@ int fsl_diu_init(int xres,
var->vsync_len << 11 | /* PW_V */
var->lower_margin; /* FP_V */
/* Pixel Clock configuration */
DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
speed_ccb = get_busfreq();
DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
temp = 1;
temp *= 1000000000;
temp /= var->pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
DPRINTF("DIU pixval = %lu\n", pixval);
hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
hw->thresholds = 0x00037800; /* The Thresholds */
hw->int_status = 0; /* INTERRUPT STATUS */
hw->int_mask = 0; /* INT MASK */
hw->plut = 0x01F5F666;
/* Modify PXCLK in GUTS CLKDVDR */
DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
temp = *guts_clkdvdr & 0x2000FFFF;
*guts_clkdvdr = temp; /* turn off clock */
*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
/* Pixel Clock configuration */
debug("DIU pixclock in ps - %d\n", var->pixclock);
diu_set_pixel_clock(var->pixclock);
fb_initialized = 1;
if (splash_bmp) {
info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
info->logo_size = info->logo_height * info->line_length;
DPRINTF("logo height %d, logo_size 0x%x\n",
debug("logo height %d, logo_size 0x%x\n",
info->logo_height,info->logo_size);
}
@ -395,10 +368,10 @@ static int fsl_diu_enable_panel(struct fb_info *info)
struct diu *hw = dr.diu_reg;
struct diu_ad *ad = &fsl_diu_fb_ad;
DPRINTF("Entered: enable_panel\n");
debug("Entered: enable_panel\n");
if (hw->desc[0] != (unsigned int)ad)
hw->desc[0] = (unsigned int)ad;
DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
debug("desc[0] = 0x%x\n", hw->desc[0]);
return 0;
}
@ -406,7 +379,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: disable_panel\n");
debug("Entered: disable_panel\n");
if (hw->desc[0] != (unsigned int)&dummy_ad)
hw->desc[0] = (unsigned int)&dummy_ad;
return 0;
@ -417,10 +390,10 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
unsigned long offset;
unsigned long mask;
DPRINTF("Entered: map_video_memory\n");
debug("Entered: map_video_memory\n");
/* allocate maximum 1280*1024 with 32bpp */
info->smem_len = 1280 * 4 *1024 + bytes_align;
DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
debug("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
info->screen_base = malloc(info->smem_len);
if (info->screen_base == NULL) {
printf("Unable to allocate fb memory\n");
@ -437,7 +410,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
info->screen_size = info->smem_len;
DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
debug("Allocated fb @ 0x%08lx, size=%d.\n",
info->smem_start, info->smem_len);
return 0;
@ -447,33 +420,25 @@ static void enable_lcdc(void)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
if (!fb_enabled) {
hw->diu_mode = dr.mode;
fb_enabled++;
}
DPRINTF("diu_mode = %d\n", hw->diu_mode);
debug("diu_mode = %d\n", hw->diu_mode);
}
static void disable_lcdc(void)
{
struct diu *hw = dr.diu_reg;
DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
if (fb_enabled) {
hw->diu_mode = 0;
fb_enabled = 0;
}
}
static u32 get_busfreq(void)
{
u32 fs_busfreq = 0;
fs_busfreq = get_bus_freq(0);
return fs_busfreq;
}
/*
* Align to 64-bit(8-byte), 32-byte, etc.
*/
@ -482,7 +447,7 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
u32 offset, ssize;
u32 mask;
DPRINTF("Entered: allocate_buf\n");
debug("Entered: allocate_buf\n");
ssize = size + bytes_align;
buf->paddr = malloc(ssize);
if (!buf->paddr)
@ -524,16 +489,16 @@ int fsl_diu_display_bmp(unsigned char *bmp,
bitmap = bmp + raster;
cpp = info->var.bits_per_pixel / 8;
DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
DPRINTF("width = %d\n", width);
DPRINTF("height = %d\n", height);
DPRINTF("bpp = %d\n", bpp);
DPRINTF("ncolors = %d\n", ncolors);
debug("bmp = 0x%08x\n", (unsigned int)bmp);
debug("bitmap = 0x%08x\n", (unsigned int)bitmap);
debug("width = %d\n", width);
debug("height = %d\n", height);
debug("bpp = %d\n", bpp);
debug("ncolors = %d\n", ncolors);
DPRINTF("xres = %d\n", info->var.xres);
DPRINTF("yres = %d\n", info->var.yres);
DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
debug("xres = %d\n", info->var.xres);
debug("yres = %d\n", info->var.yres);
debug("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
if (((width+xoffset) > info->var.xres) ||
((height+yoffset) > info->var.yres)) {

23
board/freescale/mpc8349emds/mpc8349emds.c
View File

@ -257,25 +257,24 @@ void sdram_init(void)
#define SPI_CS_MASK 0x80000000
void spi_eeprom_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
if (cs)
iopd->dat &= ~SPI_CS_MASK;
else
iopd->dat |= SPI_CS_MASK;
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_eeprom_chipsel,
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
iopd->dat |= SPI_CS_MASK;
}
#endif /* CONFIG_HARD_SPI */
#if defined(CONFIG_OF_BOARD_SETUP)

20
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
View File

@ -41,6 +41,26 @@ extern unsigned int FSL_Logo_BMP[];
static int xres, yres;
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0);
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
temp = *guts_clkdvdr & 0x2000FFFF;
*guts_clkdvdr = temp; /* turn off clock */
*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
}
void mpc8610hpcd_diu_init(void)
{

2
board/gen860t/README
View File

@ -142,5 +142,3 @@ Sr. Staff Engineer
Microvision, Inc.
<keith_outwater@mvis.com>
<outwater@eskimo.com>
vim: set ts=4 sw=4 tw=78:

98
board/gen860t/beeper.c
View File

@ -34,7 +34,6 @@
* drives the amplifier input.
*/
/*
* Initialize beeper-related hardware. Initialize timer 1 for use with
* the beeper. Use 66 Mhz internal clock with prescale of 33 to get
@ -42,10 +41,9 @@
* FIXME: we should really compute the prescale based on the reported
* core clock frequency.
*/
void
init_beeper(void)
void init_beeper (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
@ -55,53 +53,47 @@ init_beeper(void)
immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
}
/*
* Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit
* is mostly arbitrary, but the beeper isn't really much good beyond this
* frequency.
*/
void
set_beeper_frequency(uint frequency)
void set_beeper_frequency (uint frequency)
{
#define FREQ_LIMIT 2500
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
/*
* Compute timer ticks given desired frequency. The timer is set up
* to count 0.5 uS per tick and it takes two ticks per cycle (Hz).
*/
if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT;
frequency = 1000000/frequency;
immap->im_cpmtimer.cpmt_trr1 = (ushort)frequency;
if (frequency > FREQ_LIMIT)
frequency = FREQ_LIMIT;
frequency = 1000000 / frequency;
immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency;
}
/*
* Turn the beeper on
*/
void
beeper_on(void)
void beeper_on (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
}
/*
* Turn the beeper off
*/
void
beeper_off(void)
void beeper_off (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
}
/*
* Increase or decrease the beeper volume. Volume can be set
* from off to full in 64 steps. To increase volume, the output
@ -110,31 +102,28 @@ beeper_off(void)
* change pin mode to tristate) then output a high to go back to
* tristate.
*/
void
set_beeper_volume(int steps)
void set_beeper_volume (int steps)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
int i;
if (steps >= 0) {
for (i = 0; i < (steps >= 64 ? 64 : steps); i++) {
immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19);
udelay(1);
udelay (1);
immap->im_cpm.cp_pbodr |= (0x80000000 >> 19);
udelay(1);
udelay (1);
}
}
else {
} else {
for (i = 0; i > (steps <= -64 ? -64 : steps); i--) {
immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19);
udelay(1);
udelay (1);
immap->im_cpm.cp_pbdat |= (0x80000000 >> 19);
udelay(1);
udelay (1);
}
}
}
/*
* Check the environment to see if the beeper needs beeping.
* Controlled by a sequence of the form:
@ -146,24 +135,23 @@ set_beeper_volume(int steps)
*
* Return 1 on success, 0 on failure
*/
int
do_beeper(char *sequence)
int do_beeper (char *sequence)
{
#define DELIMITER ';'
int args[4];
int i;
int val;
char *p = sequence;
char *tp;
int args[4];
int i;
int val;
char *p = sequence;
char *tp;
/*
* Parse the control sequence. This is a really simple parser
* without any real error checking. You can probably blow it
* up really easily.
*/
if (*p == '\0' || !isdigit(*p)) {
printf("%s:%d: null or invalid string (%s)\n",
if (*p == '\0' || !isdigit (*p)) {
printf ("%s:%d: null or invalid string (%s)\n",
__FILE__, __LINE__, p);
return 0;
}
@ -171,14 +159,14 @@ char *tp;
i = 0;
while (*p != '\0') {
while (*p != DELIMITER) {
if (i > 3) i = 0;
val = (int) simple_strtol(p, &tp, 0);
if (i > 3)
i = 0;
val = (int) simple_strtol (p, &tp, 0);
if (tp == p) {
printf("%s:%d: no digits or bad format\n",
__FILE__,__LINE__);
printf ("%s:%d: no digits or bad format\n",
__FILE__, __LINE__);
return 0;
}
else {
} else {
args[i] = val;
}
@ -195,19 +183,17 @@ char *tp;
*/
#if 0
for (i = 0; i < 4; i++) {
printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]);
printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i,
args[i]);
}
printf("\n");
printf ("\n");
#endif
set_beeper_frequency(args[0]);
set_beeper_volume(args[1]);
beeper_on();
udelay(1000 * args[2]);
beeper_off();
udelay(1000 * args[3]);
set_beeper_frequency (args[0]);
set_beeper_volume (args[1]);
beeper_on ();
udelay (1000 * args[2]);
beeper_off ();
udelay (1000 * args[3]);
}
return 1;
}
/* vim: set ts=4 sw=4 tw=78: */

2
board/gen860t/beeper.h
View File

@ -27,5 +27,3 @@ void beeper_on(void);
void beeper_off(void);
void set_beeper_volume(int steps);
int do_beeper(char *sequence);
/* vim: set ts=4 tw=78 sw=4: */

2
board/gen860t/fpga.c
View File

@ -376,5 +376,3 @@ int fpga_busy_fn (int cookie)
return 0;
}
#endif
/* vim: set ts=4 tw=78 sw=4: */

2
board/gen860t/fpga.h
View File

@ -41,5 +41,3 @@ extern int fpga_busy_fn(int cookie);
extern int fpga_abort_fn(int cookie );
extern int fpga_pre_config_fn(int cookie );
extern int fpga_post_config_fn(int cookie );
/* vim: set ts=4 sw=4 tw=78: */

2
board/gen860t/ioport.h
View File

@ -40,5 +40,3 @@ typedef struct {
} mpc8xx_iop_conf_t;
extern void config_mpc8xx_ioports(volatile immap_t *immr);
/* vim: set ts=4 tw=78 sw=4: */

2
board/gth2/gth2.c
View File

@ -135,7 +135,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
switch (proc_id >> 24) {
case 0:

98
board/mpl/common/kbd.c
View File

@ -197,8 +197,7 @@ int isa_kbd_init(void)
irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
return (1);
}
else {
} else {
printf("%s\n",result);
return (-1);
}
@ -313,106 +312,106 @@ void kbd_set_leds(void)
}
void handle_keyboard_event(unsigned char scancode)
void handle_keyboard_event (unsigned char scancode)
{
unsigned char keycode;
/* Convert scancode to keycode */
PRINTF("scancode %x\n",scancode);
if(scancode==0xe0) {
e0=1; /* special charakters */
PRINTF ("scancode %x\n", scancode);
if (scancode == 0xe0) {
e0 = 1; /* special charakters */
return;
}
if(e0==1) {
e0=0; /* delete flag */
if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */
((scancode&0x7F)==0x1D)|| /* the right alt key */
((scancode&0x7F)==0x35)|| /* the right '/' key */
((scancode&0x7F)==0x1C) )) /* the right enter key */
if (e0 == 1) {
e0 = 0; /* delete flag */
if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
((scancode & 0x7F) == 0x1D) || /* the right alt key */
((scancode & 0x7F) == 0x35) || /* the right '/' key */
((scancode & 0x7F) == 0x1C)))
/* the right enter key */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
switch(scancode)
{
switch (scancode) {
case 0x2A:
case 0x36: /* shift pressed */
shift=1;
shift = 1;
return; /* do nothing else */
case 0xAA:
case 0xB6: /* shift released */
shift=0;
shift = 0;
return; /* do nothing else */
case 0x38: /* alt pressed */
alt=1;
alt = 1;
return; /* do nothing else */
case 0xB8: /* alt released */
alt=0;
alt = 0;
return; /* do nothing else */
case 0x1d: /* ctrl pressed */
ctrl=1;
ctrl = 1;
return; /* do nothing else */
case 0x9d: /* ctrl released */
ctrl=0;
ctrl = 0;
return; /* do nothing else */
case 0x46: /* scrollock pressed */
scroll_lock=~scroll_lock;
kbd_set_leds();
scroll_lock = ~scroll_lock;
kbd_set_leds ();
return; /* do nothing else */
case 0x3A: /* capslock pressed */
caps_lock=~caps_lock;
kbd_set_leds();
caps_lock = ~caps_lock;
kbd_set_leds ();
return;
case 0x45: /* numlock pressed */
num_lock=~num_lock;
kbd_set_leds();
num_lock = ~num_lock;
kbd_set_leds ();
return;
case 0xC6: /* scroll lock released */
case 0xC5: /* num lock released */
case 0xBA: /* caps lock released */
return; /* just swallow */
}
if((scancode&0x80)==0x80) /* key released */
if ((scancode & 0x80) == 0x80) /* key released */
return;
/* now, decide which table we need */
if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF("unkown scancode %X\n",scancode);
if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown scancode %X\n", scancode);
return; /* swallow it */
}
/* setup plain code first */
keycode=kbd_plain_xlate[scancode];
if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown caps-locked scancode %X\n",scancode);
keycode = kbd_plain_xlate[scancode];
if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown caps-locked scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
if(keycode<'A') { /* we only want the alphas capital */
keycode=kbd_plain_xlate[scancode];
keycode = kbd_shift_xlate[scancode];
if (keycode < 'A') { /* we only want the alphas capital */
keycode = kbd_plain_xlate[scancode];
}
}
if(shift==1) { /* shift overwrites caps_lock */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown shifted scancode %X\n",scancode);
if (shift == 1) { /* shift overwrites caps_lock */
if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown shifted scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
keycode = kbd_shift_xlate[scancode];
}
if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF("unkown ctrl scancode %X\n",scancode);
if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown ctrl scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_ctrl_xlate[scancode];
keycode = kbd_ctrl_xlate[scancode];
}
/* check if valid keycode */
if(keycode==0xff) {
PRINTF("unkown scancode %X\n",scancode);
if (keycode == 0xff) {
PRINTF ("unkown scancode %X\n", scancode);
return; /* swallow unknown codes */
}
kbd_put_queue(keycode);
PRINTF("%x\n",keycode);
kbd_put_queue (keycode);
PRINTF ("%x\n", keycode);
}
/*
@ -583,8 +582,7 @@ char * kbd_initialize(void)
status = kbd_wait_for_input();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
{
if (status != KBD_REPLY_RESEND) {
PRINTF("status: %X\n",status);
return "Kbd: reset failed, no ACK";
}

2
board/pb1x00/pb1x00.c
View File

@ -51,7 +51,7 @@ int checkboard (void)
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
switch (proc_id >> 24) {
case 0:

174
board/pcippc2/cpc710_init_ram.c
View File

@ -28,8 +28,7 @@
#include "pcippc2.h"
#include "i2c.h"
typedef struct cpc710_mem_org_s
{
typedef struct cpc710_mem_org_s {
u8 rows;
u8 cols;
u8 banks2;
@ -37,15 +36,11 @@ typedef struct cpc710_mem_org_s
} cpc710_mem_org_t;
static int cpc710_compute_mcer (u32 * mcer,
unsigned long *
size,
unsigned int sdram);
unsigned long *size, unsigned int sdram);
static int cpc710_eeprom_checksum (unsigned int sdram);
static u8 cpc710_eeprom_read (unsigned int sdram,
unsigned int offset);
static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset);
static u32 cpc710_mcer_mem [] =
{
static u32 cpc710_mcer_mem[] = {
0x000003f3, /* 18 lines, 4 Mb */
0x000003e3, /* 19 lines, 8 Mb */
0x000003c3, /* 20 lines, 16 Mb */
@ -56,29 +51,28 @@ static u32 cpc710_mcer_mem [] =
0x00000002, /* 25 lines, 512 Mb */
0x00000001 /* 26 lines, 1024 Mb */
};
static cpc710_mem_org_t cpc710_mem_org [] =
{
{ 0x0c, 0x09, 0x02, 0x00 }, /* 0000: 12/ 9/2 */
{ 0x0d, 0x09, 0x02, 0x00 }, /* 0000: 13/ 9/2 */
{ 0x0d, 0x0a, 0x02, 0x00 }, /* 0000: 13/10/2 */
{ 0x0d, 0x0b, 0x02, 0x00 }, /* 0000: 13/11/2 */
{ 0x0d, 0x0c, 0x02, 0x00 }, /* 0000: 13/12/2 */
{ 0x0e, 0x0c, 0x02, 0x00 }, /* 0000: 14/12/2 */
{ 0x0b, 0x08, 0x02, 0x01 }, /* 0001: 11/ 8/2 */
{ 0x0b, 0x09, 0x01, 0x02 }, /* 0010: 11/ 9/1 */
{ 0x0b, 0x0a, 0x01, 0x03 }, /* 0011: 11/10/1 */
{ 0x0c, 0x08, 0x02, 0x04 }, /* 0100: 12/ 8/2 */
{ 0x0c, 0x0a, 0x02, 0x05 }, /* 0101: 12/10/2 */
{ 0x0d, 0x08, 0x01, 0x06 }, /* 0110: 13/ 8/1 */
{ 0x0d, 0x08, 0x02, 0x07 }, /* 0111: 13/ 8/2 */
{ 0x0d, 0x09, 0x01, 0x08 }, /* 1000: 13/ 9/1 */
{ 0x0d, 0x0a, 0x01, 0x09 }, /* 1001: 13/10/1 */
{ 0x0b, 0x08, 0x01, 0x0a }, /* 1010: 11/ 8/1 */
{ 0x0c, 0x08, 0x01, 0x0b }, /* 1011: 12/ 8/1 */
{ 0x0c, 0x09, 0x01, 0x0c }, /* 1100: 12/ 9/1 */
{ 0x0e, 0x09, 0x02, 0x0d }, /* 1101: 14/ 9/2 */
{ 0x0e, 0x0a, 0x02, 0x0e }, /* 1110: 14/10/2 */
{ 0x0e, 0x0b, 0x02, 0x0f } /* 1111: 14/11/2 */
static cpc710_mem_org_t cpc710_mem_org[] = {
{0x0c, 0x09, 0x02, 0x00}, /* 0000: 12/ 9/2 */
{0x0d, 0x09, 0x02, 0x00}, /* 0000: 13/ 9/2 */
{0x0d, 0x0a, 0x02, 0x00}, /* 0000: 13/10/2 */
{0x0d, 0x0b, 0x02, 0x00}, /* 0000: 13/11/2 */
{0x0d, 0x0c, 0x02, 0x00}, /* 0000: 13/12/2 */
{0x0e, 0x0c, 0x02, 0x00}, /* 0000: 14/12/2 */
{0x0b, 0x08, 0x02, 0x01}, /* 0001: 11/ 8/2 */
{0x0b, 0x09, 0x01, 0x02}, /* 0010: 11/ 9/1 */
{0x0b, 0x0a, 0x01, 0x03}, /* 0011: 11/10/1 */
{0x0c, 0x08, 0x02, 0x04}, /* 0100: 12/ 8/2 */
{0x0c, 0x0a, 0x02, 0x05}, /* 0101: 12/10/2 */
{0x0d, 0x08, 0x01, 0x06}, /* 0110: 13/ 8/1 */
{0x0d, 0x08, 0x02, 0x07}, /* 0111: 13/ 8/2 */
{0x0d, 0x09, 0x01, 0x08}, /* 1000: 13/ 9/1 */
{0x0d, 0x0a, 0x01, 0x09}, /* 1001: 13/10/1 */
{0x0b, 0x08, 0x01, 0x0a}, /* 1010: 11/ 8/1 */
{0x0c, 0x08, 0x01, 0x0b}, /* 1011: 12/ 8/1 */
{0x0c, 0x09, 0x01, 0x0c}, /* 1100: 12/ 9/1 */
{0x0e, 0x09, 0x02, 0x0d}, /* 1101: 14/ 9/2 */
{0x0e, 0x0a, 0x02, 0x0e}, /* 1110: 14/10/2 */
{0x0e, 0x0b, 0x02, 0x0f} /* 1111: 14/11/2 */
};
unsigned long cpc710_ram_init (void)
@ -90,54 +84,52 @@ unsigned long cpc710_ram_init (void)
#ifndef CFG_RAMBOOT
/* Clear memory banks
*/
out32(REG(SDRAM0, MCER0), 0);
out32(REG(SDRAM0, MCER1), 0);
out32(REG(SDRAM0, MCER2), 0);
out32(REG(SDRAM0, MCER3), 0);
out32(REG(SDRAM0, MCER4), 0);
out32(REG(SDRAM0, MCER5), 0);
out32(REG(SDRAM0, MCER6), 0);
out32(REG(SDRAM0, MCER7), 0);
iobarrier_rw();
out32 (REG (SDRAM0, MCER0), 0);
out32 (REG (SDRAM0, MCER1), 0);
out32 (REG (SDRAM0, MCER2), 0);
out32 (REG (SDRAM0, MCER3), 0);
out32 (REG (SDRAM0, MCER4), 0);
out32 (REG (SDRAM0, MCER5), 0);
out32 (REG (SDRAM0, MCER6), 0);
out32 (REG (SDRAM0, MCER7), 0);
iobarrier_rw ();
/* Disable memory
*/
out32(REG(SDRAM0,MCCR), 0x13b06000);
iobarrier_rw();
out32 (REG (SDRAM0, MCCR), 0x13b06000);
iobarrier_rw ();
#endif
/* Only the first memory bank is initialised now
*/
if (! cpc710_compute_mcer(& mcer, & bank_size, 0))
{
puts("Unsupported SDRAM type !\n");
hang();
if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
puts ("Unsupported SDRAM type !\n");
hang ();
}
memsize += bank_size;
#ifndef CFG_RAMBOOT
/* Enable bank, zero start
*/
out32(REG(SDRAM0, MCER0), mcer | 0x80000000);
iobarrier_rw();
out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
iobarrier_rw ();
#endif
#ifndef CFG_RAMBOOT
/* Enable memory
*/
out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000);
out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
/* Wait until initialisation finished
*/
while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000))
{
iobarrier_rw();
while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
iobarrier_rw ();
}
/* Clear Memory Error Status and Address registers
*/
out32(REG(SDRAM0, MESR), 0);
out32(REG(SDRAM0, MEAR), 0);
iobarrier_rw();
out32 (REG (SDRAM0, MESR), 0);
out32 (REG (SDRAM0, MEAR), 0);
iobarrier_rw ();
/* ECC is not configured now
*/
@ -145,15 +137,12 @@ unsigned long cpc710_ram_init (void)
/* Memory size counter
*/
out32(REG(CPC0, RGBAN1), memsize);
out32 (REG (CPC0, RGBAN1), memsize);
return memsize;
}
static int cpc710_compute_mcer (
u32 * mcer,
unsigned long * size,
unsigned int sdram)
static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram)
{
u8 rows;
u8 cols;
@ -161,53 +150,47 @@ static int cpc710_compute_mcer (
unsigned int lines;
u32 mc = 0;
unsigned int i;
cpc710_mem_org_t * org = 0;
cpc710_mem_org_t *org = 0;
if (! i2c_reset())
{
puts("Can't reset I2C!\n");
hang();
if (!i2c_reset ()) {
puts ("Can't reset I2C!\n");
hang ();
}
if (! cpc710_eeprom_checksum(sdram))
{
puts("Invalid EEPROM checksum !\n");
hang();
if (!cpc710_eeprom_checksum (sdram)) {
puts ("Invalid EEPROM checksum !\n");
hang ();
}
rows = cpc710_eeprom_read(sdram, 3);
cols = cpc710_eeprom_read(sdram, 4);
rows = cpc710_eeprom_read (sdram, 3);
cols = cpc710_eeprom_read (sdram, 4);
/* Can be 2 or 4 banks; divide by 2
*/
banks2 = cpc710_eeprom_read(sdram, 17) / 2;
banks2 = cpc710_eeprom_read (sdram, 17) / 2;
lines = rows + cols + banks2;
if (lines < 18 || lines > 26)
{
if (lines < 18 || lines > 26) {
/* Unsupported configuration
*/
return 0;
}
mc |= cpc710_mcer_mem[lines - 18] << 6;
mc |= cpc710_mcer_mem [lines - 18] << 6;
for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t);
i++) {
cpc710_mem_org_t *corg = cpc710_mem_org + i;
for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++)
{
cpc710_mem_org_t * corg = cpc710_mem_org + i;
if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2)
{
if (corg->rows == rows && corg->cols == cols
&& corg->banks2 == banks2) {
org = corg;
break;
}
}
if (! org)
{
if (!org) {
/* Unsupported configuration
*/
return 0;
@ -223,31 +206,26 @@ static int cpc710_compute_mcer (
return 1;
}
static int cpc710_eeprom_checksum (
unsigned int sdram)
static int cpc710_eeprom_checksum (unsigned int sdram)
{
u8 sum = 0;
unsigned int i;
for (i = 0; i < 63; i++)
{
sum += cpc710_eeprom_read(sdram, i);
for (i = 0; i < 63; i++) {
sum += cpc710_eeprom_read (sdram, i);
}
return sum == cpc710_eeprom_read(sdram, 63);
return sum == cpc710_eeprom_read (sdram, 63);
}
static u8 cpc710_eeprom_read (
unsigned int sdram,
unsigned int offset)
static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset)
{
u8 dev = (sdram << 1) | 0xa0;
u8 data;
if (! i2c_read_byte(& data, dev,offset))
{
puts("I2C error !\n");
hang();
if (!i2c_read_byte (&data, dev, offset)) {
puts ("I2C error !\n");
hang ();
}
return data;

5
board/pcippc2/sconsole.h
View File

@ -26,13 +26,12 @@
#include <config.h>
typedef struct sconsole_buffer_s
{
typedef struct sconsole_buffer_s {
unsigned long size;
unsigned long max_size;
unsigned long pos;
unsigned long baud;
char data [1];
char data[1];
} sconsole_buffer_t;
#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)

3
board/purple/purple.c
View File

@ -184,8 +184,7 @@ static void copydwords (ulong *source, ulong *destination, ulong nlongs)
ulong temp,temp1;
ulong *dstend = destination + nlongs;
while (destination < dstend)
{
while (destination < dstend) {
temp = *source++;
/* dummy read from sdram */
temp1 = *(ulong *)0xa0000000;

5
board/purple/sconsole.h
View File

@ -26,12 +26,11 @@
#include <config.h>
typedef struct sconsole_buffer_s
{
typedef struct sconsole_buffer_s {
unsigned long size;
unsigned long max_size;
unsigned long pos;
char data [1];
char data[1];
} sconsole_buffer_t;
#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)

6
board/qemu-mips/qemu-mips.c
View File

@ -38,7 +38,7 @@ int checkboard(void)
u32 proc_id;
u32 config1;
proc_id = read_32bit_cp0_register(CP0_PRID);
proc_id = read_c0_prid();
printf("Board: Qemu -M mips CPU: ");
switch (proc_id) {
case 0x00018000:
@ -51,7 +51,7 @@ int checkboard(void)
printf("4KEc");
break;
case 0x00019300:
config1 = read_mips32_cp0_config1();
config1 = read_c0_config1();
if (config1 & 1)
printf("24Kf");
else
@ -64,7 +64,7 @@ int checkboard(void)
printf("R4000");
break;
case 0x00018100:
config1 = read_mips32_cp0_config1();
config1 = read_c0_config1();
if (config1 & 1)
printf("5Kf");
else

51
board/quad100hd/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o nand.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/quad100hd/config.mk Normal file
View File

@ -0,0 +1,24 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

79
board/quad100hd/nand.c Normal file
View File

@ -0,0 +1,79 @@
/*
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#if defined(CONFIG_CMD_NAND)
#include <asm/gpio.h>
#include <nand.h>
/*
* hardware specific access to control-lines
*/
static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd)
{
switch(cmd) {
case NAND_CTL_SETCLE:
gpio_write_bit(CFG_NAND_CLE, 1);
break;
case NAND_CTL_CLRCLE:
gpio_write_bit(CFG_NAND_CLE, 0);
break;
case NAND_CTL_SETALE:
gpio_write_bit(CFG_NAND_ALE, 1);
break;
case NAND_CTL_CLRALE:
gpio_write_bit(CFG_NAND_ALE, 0);
break;
case NAND_CTL_SETNCE:
gpio_write_bit(CFG_NAND_CE, 0);
break;
case NAND_CTL_CLRNCE:
gpio_write_bit(CFG_NAND_CE, 1);
break;
}
}
static int quad100hd_nand_ready(struct mtd_info *mtd)
{
return gpio_read_in_bit(CFG_NAND_RDY);
}
/*
* Main initialization routine
*/
int board_nand_init(struct nand_chip *nand)
{
/* Set address of hardware control function */
nand->hwcontrol = quad100hd_hwcontrol;
nand->dev_ready = quad100hd_nand_ready;
nand->eccmode = NAND_ECC_SOFT;
/* 15 us command delay time */
nand->chip_delay = 20;
/* Return happy */
return 0;
}
#endif /* CONFIG_CMD_NAND */

93
board/quad100hd/quad100hd.c Normal file
View File

@ -0,0 +1,93 @@
/*
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
* Based in part on board/icecube/icecube.c from PPCBoot
* (C) Copyright 2003 Intrinsyc Software
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <environment.h>
#include <logbuff.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* taken from PPCBoot */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
#ifdef DISPLAY_BOARD_INFO
sys_info_t sysinfo;
#endif
puts("Board: Quad100hd");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef DISPLAY_BOARD_INFO
/* taken from ppcboot */
get_sys_info(&sysinfo);
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
1000000));
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
#endif
return 0;
}
long int initdram(int board_type)
{
return CFG_SDRAM_SIZE;
}

133
board/quad100hd/u-boot.lds Normal file
View File

@ -0,0 +1,133 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1
board/quantum/fpga.h
View File

@ -31,4 +31,3 @@ int fpga_boot(unsigned char *fpgadata, int size);
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
/* vim: set ts=4 sw=4 tw=78: */

51
board/sacsng/sacsng.c
View File

@ -842,36 +842,29 @@ void show_boot_progress (int status)
#define SPI_ADC_CS_MASK 0x00000800
#define SPI_DAC_CS_MASK 0x00001000
void spi_adc_chipsel(int cs)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
if(cs)
iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */
else
iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */
}
void spi_dac_chipsel(int cs)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
if(cs)
iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */
else
iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects: it calls the appropriate function to control the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_adc_chipsel,
spi_dac_chipsel
static const u32 cs_mask[] = {
SPI_ADC_CS_MASK,
SPI_DAC_CS_MASK,
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
iopd->pdat &= ~cs_mask[slave->cs];
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
iopd->pdat |= cs_mask[slave->cs];
}
#endif

95
board/snmc/qs860t/flash.c
View File

@ -79,8 +79,7 @@ unsigned long flash_init (void)
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1)
{
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
@ -98,15 +97,11 @@ unsigned long flash_init (void)
#endif
size_b1 = 0 ;
flash_info[0].size = size_b0;
}
/* 2 banks */
else
{
} else { /* 2 banks */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1)
{
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
@ -115,8 +110,7 @@ unsigned long flash_init (void)
mtdcr(ebccfgd, pbcr);
}
if (size_b0)
{
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
@ -613,10 +607,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
volatile FLASH_WORD_SIZE *addr =
(volatile FLASH_WORD_SIZE *) (info->start[0]);
int flag, prot, sect, l_sect, barf;
ulong start, now, last;
int rcode = 0;
@ -632,21 +627,20 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
if ((info->flash_id == FLASH_UNKNOWN) ||
((info->flash_id > FLASH_AMD_COMP) &&
( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
@ -654,8 +648,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
if(info->flash_id < FLASH_AMD_COMP) {
flag = disable_interrupts ();
if (info->flash_id < FLASH_AMD_COMP) {
#ifndef CFG_FLASH_16BIT
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
@ -670,9 +664,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
addr[0x02AA] = 0x0055;
#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
addr[0] = (0x00300030 & FLASH_ID_MASK);
l_sect = sect;
}
@ -680,7 +674,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
@ -693,11 +687,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
start = get_timer (0);
last = start;
addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
(0x00800080&FLASH_ID_MASK) )
{
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
(0x00800080 & FLASH_ID_MASK)) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -708,50 +701,54 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
}
DONE:
DONE:
/* reset to read mode */
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
} else {
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
barf = 0;
#ifndef CFG_FLASH_16BIT
addr = (vu_long*)(info->start[sect]);
addr = (vu_long *) (info->start[sect]);
addr[0] = 0x00200020;
addr[0] = 0x00D000D0;
while(!(addr[0] & 0x00800080)); /* wait for error or finish */
if( addr[0] & 0x003A003A) { /* check for error */
while (!(addr[0] & 0x00800080)); /* wait for error or finish */
if (addr[0] & 0x003A003A) { /* check for error */
barf = addr[0] & 0x003A0000;
if( barf ) {
barf >>=16;
if (barf) {
barf >>= 16;
} else {
barf = addr[0] & 0x0000003A;
}
}
#else
addr = (vu_short*)(info->start[sect]);
addr = (vu_short *) (info->start[sect]);
addr[0] = 0x0020;
addr[0] = 0x00D0;
while(!(addr[0] & 0x0080)); /* wait for error or finish */
if( addr[0] & 0x003A) /* check for error */
while (!(addr[0] & 0x0080)); /* wait for error or finish */
if (addr[0] & 0x003A) /* check for error */
barf = addr[0] & 0x003A;
#endif
if(barf) {
printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if((barf & 0x0030) == 0x0030)
printf("Command Sequence error.\n");
if((barf & 0x0030) == 0x0020)
printf("Block Erase error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
if (barf) {
printf ("\nFlash error in sector at %lx\n",
(unsigned long) addr);
if (barf & 0x0002)
printf ("Block locked, not erased.\n");
if ((barf & 0x0030) == 0x0030)
printf ("Command Sequence error.\n");
if ((barf & 0x0030) == 0x0020)
printf ("Block Erase error.\n");
if (barf & 0x0008)
printf ("Vpp Low error.\n");
rcode = 1;
} else printf(".");
} else
printf (".");
l_sect = sect;
}
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
addr = (volatile FLASH_WORD_SIZE *) info->start[0];
addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
}
@ -1113,8 +1110,6 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
return (0);
}
#endif
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------*/

53
board/socrates/Makefile Normal file
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@ -0,0 +1,53 @@
#
# (C) Copyright 2008
# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
#
COBJS := $(BOARD).o law.o tlb.o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

30
board/socrates/config.mk Normal file
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@ -0,0 +1,30 @@
# Copyright 2004 Freescale Semiconductor.
#
# Modified by Sergei Poselenov
# (C) Copyright 2008, Emcraft Systems.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# socrates board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#
TEXT_BASE = 0xfffc0000

57
board/socrates/law.c Normal file
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@ -0,0 +1,57 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

122
board/socrates/sdram.c Normal file
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@ -0,0 +1,122 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
#if !defined(CONFIG_SPD_EEPROM)
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
*
* NOTE: Some of the hardcoded values are hardware dependant,
* so this should be extended for other future boards
* using this routine!
*/
long int sdram_setup(int casl)
{
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
/*
* Disable memory controller.
*/
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL;
ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
asm ("sync;isync;msync");
udelay(1000);
ddr->sdram_cfg = CFG_DDR_CONFIG;
asm ("sync; isync; msync");
udelay(1000);
if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
/*
* OK, size detected -> all done
*/
return CFG_SDRAM_SIZE<<20;
}
return 0; /* nothing found ! */
}
#endif
long int initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
#endif
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif

220
board/socrates/socrates.c Normal file
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@ -0,0 +1,220 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
char *src;
int f;
char *s = getenv("serial#");
puts("Board: Socrates");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef CONFIG_PCI
if (gur->porpllsr & (1<<15)) {
src = "SYSCLK";
f = CONFIG_SYS_CLK_FREQ;
} else {
src = "PCI_CLK";
f = CONFIG_PCI_CLK_FREQ;
}
printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
/*
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
return 0;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
ecm->eedr = 0xffffffff; /* Clear ecm errors */
ecm->eeer = 0xffffffff; /* Enable ecm errors */
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER}},
{}
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
void pci_init_board (void)
{
#ifdef CONFIG_PCI
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
ft_cpu_setup(blob, bd);
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
val[2] = gd->bd->bi_flashstart;
val[3] = gd->bd->bi_flashsize;
rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
val, sizeof(val), 1);
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

117
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@ -0,0 +1,117 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

150
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@ -0,0 +1,150 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* (C) Copyright 2002,2003, Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

25
board/ssv/adnpesc1/adnpesc1.c
View File

@ -69,25 +69,24 @@ long int initdram (int board_type)
#define SPI_RTC_CS_MASK 0x00000001
void spi_rtc_chipsel(int cs)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
if (cs)
spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */
else
spi->slaveselect = 0; /* deactivate (0) */
}
/*
* The SPI command uses this table of functions for controlling the SPI
* chip selects: it calls the appropriate function to control the SPI
* chip selects.
*/
spi_chipsel_type spi_chipsel[] = {
spi_rtc_chipsel
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
void spi_cs_deactivate(struct spi_slave *slave)
{
nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
spi->slaveselect = 0; /* deactivate (0) */
}
#endif

3
board/trab/tsc2000.h
View File

@ -111,8 +111,7 @@
#define TSC2000_DELAY_BASE 500
#define TSC2000_NO_SENSOR -0x10000
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on
* TRAB */
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on TRAB */
void tsc2000_write(unsigned short, unsigned short);
unsigned short tsc2000_read (unsigned short);

2
common/Makefile
View File

@ -113,6 +113,7 @@ COBJS-y += env_dataflash.o
COBJS-y += env_flash.o
COBJS-y += env_eeprom.o
COBJS-y += env_onenand.o
COBJS-y += env_sf.o
COBJS-y += env_nvram.o
COBJS-y += env_nowhere.o
COBJS-y += exports.o
@ -143,6 +144,7 @@ COBJS-y += xyzModem.o
COBJS-y += cmd_mac.o
COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
COBJS-$(CONFIG_MP) += cmd_mp.o
COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
COBJS := $(COBJS-y)
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)

37
common/cmd_df.c Normal file
View File

@ -0,0 +1,37 @@
/*
* Command for accessing DataFlash.
*
* Copyright (C) 2008 Atmel Corporation
*/
#include <common.h>
#include <df.h>
static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
const char *cmd;
/* need at least two arguments */
if (argc < 2)
goto usage;
cmd = argv[1];
if (strcmp(cmd, "init") == 0) {
df_init(0, 0, 1000000);
return 0;
}
if (strcmp(cmd, "info") == 0) {
df_show_info();
return 0;
}
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
sf, 2, 1, do_serial_flash,
"sf - Serial flash sub-system\n",
"probe [bus:]cs - init flash device on given SPI bus and CS\n")

10
common/cmd_fdc.c
View File

@ -46,14 +46,12 @@
#define FALSE 0
#endif
/*#if defined(CONFIG_CMD_DATE) */
/*#include <rtc.h> */
/*#endif */
#if defined(CONFIG_CMD_FDC) || defined(CONFIG_CMD_FDOS)
typedef struct {
int flags; /* connected drives ect */
unsigned long blnr; /* Logical block nr */
@ -61,9 +59,10 @@ typedef struct {
uchar cmdlen; /* cmd length */
uchar cmd[16]; /* cmd desc */
uchar dma; /* if > 0 dma enabled */
uchar result[11];/* status information */
uchar result[11]; /* status information */
uchar resultlen; /* lenght of result */
} FDC_COMMAND_STRUCT;
/* flags: only the lower 8bit used:
* bit 0 if set drive 0 is present
* bit 1 if set drive 1 is present
@ -75,7 +74,6 @@ typedef struct {
* bit 7 if set disk in drive 4 is inserted
*/
/* cmd indexes */
#define COMMAND 0
#define DRIVE 1
@ -158,9 +156,9 @@ typedef struct {
unsigned char gap; /* gap1 size */
unsigned char rate; /* data rate. |= 0x40 for perpendicular */
unsigned char spec1; /* stepping rate, head unload time */
unsigned char fmt_gap; /* gap2 size */
unsigned char fmt_gap;/* gap2 size */
unsigned char hlt; /* head load time */
unsigned char sect_code; /* Sector Size code */
unsigned char sect_code;/* Sector Size code */
const char * name; /* used only for predefined formats */
} FD_GEO_STRUCT;

12
common/cmd_log.c
View File

@ -66,6 +66,12 @@ static logbuff_t *log;
#endif
static char *lbuf;
unsigned long __logbuffer_base(void)
{
return CFG_SDRAM_BASE + gd->bd->bi_memsize - LOGBUFF_LEN;
}
unsigned long logbuffer_base (void) __attribute__((weak, alias("__logbuffer_base")));
void logbuff_init_ptrs (void)
{
unsigned long tag, post_word;
@ -75,7 +81,7 @@ void logbuff_init_ptrs (void)
log = (logbuff_t *)CONFIG_ALT_LH_ADDR;
lbuf = (char *)CONFIG_ALT_LB_ADDR;
#else
log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1;
log = (logbuff_t *)(logbuffer_base ()) - 1;
lbuf = (char *)log->buf;
#endif
@ -107,7 +113,7 @@ void logbuff_init_ptrs (void)
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
gd->post_log_word |= LOGBUFF_INITIALIZED;
gd->flags |= GD_FLG_LOGINIT;
}
void logbuff_reset (void)
@ -168,7 +174,7 @@ static void logbuff_puts (const char *s)
void logbuff_log(char *msg)
{
if ((gd->post_log_word & LOGBUFF_INITIALIZED)) {
if ((gd->flags & GD_FLG_LOGINIT)) {
logbuff_printk (msg);
} else {
/* Can happen only for pre-relocated errors as logging */

2
common/cmd_nand.c
View File

@ -37,8 +37,6 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part);
#endif
extern nand_info_t nand_info[]; /* info for NAND chips */
static int nand_dump_oob(nand_info_t *nand, ulong off)
{
return 0;

3
common/cmd_nvedit.c
View File

@ -58,8 +58,9 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CFG_ENV_IS_IN_DATAFLASH) && \
!defined(CFG_ENV_IS_IN_NAND) && \
!defined(CFG_ENV_IS_IN_ONENAND) && \
!defined(CFG_ENV_IS_IN_SPI_FLASH) && \
!defined(CFG_ENV_IS_NOWHERE)
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|NOWHERE}
# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|SPI_FLASH|NOWHERE}
#endif
#define XMK_STR(x) #x

191
common/cmd_sf.c Normal file
View File

@ -0,0 +1,191 @@
/*
* Command for accessing SPI flash.
*
* Copyright (C) 2008 Atmel Corporation
*/
#include <common.h>
#include <spi_flash.h>
#include <asm/io.h>
#ifndef CONFIG_SF_DEFAULT_SPEED
# define CONFIG_SF_DEFAULT_SPEED 1000000
#endif
#ifndef CONFIG_SF_DEFAULT_MODE
# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#endif
static struct spi_flash *flash;
static int do_spi_flash_probe(int argc, char *argv[])
{
unsigned int bus = 0;
unsigned int cs;
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
struct spi_flash *new;
if (argc < 2)
goto usage;
cs = simple_strtoul(argv[1], &endp, 0);
if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
goto usage;
if (*endp == ':') {
if (endp[1] == 0)
goto usage;
bus = cs;
cs = simple_strtoul(endp + 1, &endp, 0);
if (*endp != 0)
goto usage;
}
if (argc >= 3) {
speed = simple_strtoul(argv[2], &endp, 0);
if (*argv[2] == 0 || *endp != 0)
goto usage;
}
if (argc >= 4) {
mode = simple_strtoul(argv[3], &endp, 0);
if (*argv[3] == 0 || *endp != 0)
goto usage;
}
new = spi_flash_probe(bus, cs, speed, mode);
if (!new) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
if (flash)
spi_flash_free(flash);
flash = new;
printf("%u KiB %s at %u:%u is now current device\n",
flash->size >> 10, flash->name, bus, cs);
return 0;
usage:
puts("Usage: sf probe [bus:]cs [hz] [mode]\n");
return 1;
}
static int do_spi_flash_read_write(int argc, char *argv[])
{
unsigned long addr;
unsigned long offset;
unsigned long len;
void *buf;
char *endp;
int ret;
if (argc < 4)
goto usage;
addr = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
goto usage;
offset = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
goto usage;
len = simple_strtoul(argv[3], &endp, 16);
if (*argv[3] == 0 || *endp != 0)
goto usage;
buf = map_physmem(addr, len, MAP_WRBACK);
if (!buf) {
puts("Failed to map physical memory\n");
return 1;
}
if (strcmp(argv[0], "read") == 0)
ret = spi_flash_read(flash, offset, len, buf);
else
ret = spi_flash_write(flash, offset, len, buf);
unmap_physmem(buf, len);
if (ret) {
printf("SPI flash %s failed\n", argv[0]);
return 1;
}
return 0;
usage:
printf("Usage: sf %s addr offset len\n", argv[0]);
return 1;
}
static int do_spi_flash_erase(int argc, char *argv[])
{
unsigned long offset;
unsigned long len;
char *endp;
int ret;
if (argc < 3)
goto usage;
offset = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
goto usage;
len = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
goto usage;
ret = spi_flash_erase(flash, offset, len);
if (ret) {
printf("SPI flash %s failed\n", argv[0]);
return 1;
}
return 0;
usage:
puts("Usage: sf erase offset len\n");
return 1;
}
static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
const char *cmd;
/* need at least two arguments */
if (argc < 2)
goto usage;
cmd = argv[1];
if (strcmp(cmd, "probe") == 0)
return do_spi_flash_probe(argc - 1, argv + 1);
/* The remaining commands require a selected device */
if (!flash) {
puts("No SPI flash selected. Please run `sf probe'\n");
return 1;
}
if (strcmp(cmd, "read") == 0 || strcmp(cmd, "write") == 0)
return do_spi_flash_read_write(argc - 1, argv + 1);
if (strcmp(cmd, "erase") == 0)
return do_spi_flash_erase(argc - 1, argv + 1);
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
sf, 5, 1, do_spi_flash,
"sf - SPI flash sub-system\n",
"probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n"
" and chip select\n"
"sf read addr offset len - read `len' bytes starting at\n"
" `offset' to memory at `addr'\n"
"sf write addr offset len - write `len' bytes from memory\n"
" at `addr' to flash at `offset'\n"
"sf erase offset len - erase `len' bytes from `offset'\n");

36
common/cmd_spi.c
View File

@ -37,17 +37,17 @@
# define MAX_SPI_BYTES 32 /* Maximum number of bytes we can handle */
#endif
/*
* External table of chip select functions (see the appropriate board
* support for the actual definition of the table).
*/
extern spi_chipsel_type spi_chipsel[];
extern int spi_chipsel_cnt;
#ifndef CONFIG_DEFAULT_SPI_BUS
# define CONFIG_DEFAULT_SPI_BUS 0
#endif
#ifndef CONFIG_DEFAULT_SPI_MODE
# define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
#endif
/*
* Values from last command.
*/
static int device;
static unsigned int device;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
@ -65,6 +65,7 @@ static uchar din[MAX_SPI_BYTES];
int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
struct spi_slave *slave;
char *cp = 0;
uchar tmp;
int j;
@ -101,19 +102,24 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
}
if ((device < 0) || (device >= spi_chipsel_cnt)) {
printf("Invalid device %d, giving up.\n", device);
return 1;
}
if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) {
printf("Invalid bitlen %d, giving up.\n", bitlen);
return 1;
}
debug ("spi_chipsel[%d] = %08X\n",
device, (uint)spi_chipsel[device]);
/* FIXME: Make these parameters run-time configurable */
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave) {
printf("Invalid device %d, giving up.\n", device);
return 1;
}
if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) {
debug ("spi chipsel = %08X\n", device);
spi_claim_bus(slave);
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error with the SPI transaction.\n");
rcode = 1;
} else {
@ -123,6 +129,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("\n");
}
spi_release_bus(slave);
spi_free_slave(slave);
return rcode;
}

4
common/command.c
View File

@ -196,9 +196,7 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
expr = !expr;
#if 0
printf(": returns %d\n", expr);
#endif
debug (": returns %d\n", expr);
return expr;
}

3
common/dlmalloc.c
View File

@ -1,3 +1,5 @@
#include <common.h>
#if 0 /* Moved to malloc.h */
/* ---------- To make a malloc.h, start cutting here ------------ */
@ -947,7 +949,6 @@ void malloc_stats();
#endif /* 0 */
#endif /* 0 */ /* Moved to malloc.h */
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;

3
common/env_common.c
View File

@ -134,7 +134,8 @@ uchar default_environment[] = {
"\0"
};
#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */
#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ \
|| defined(CFG_ENV_IS_IN_SPI_FLASH)
int default_environment_size = sizeof(default_environment);
#endif

3
common/env_nand.c
View File

@ -57,9 +57,6 @@ int nand_legacy_rw (struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
/* info for NAND chips, defined in drivers/mtd/nand/nand.c */
extern nand_info_t nand_info[];
/* references to names in env_common.c */
extern uchar default_environment[];
extern int default_environment_size;

131
common/env_sf.c Normal file
View File

@ -0,0 +1,131 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* (C) Copyright 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#ifdef CFG_ENV_IS_IN_SPI_FLASH
#include <environment.h>
#include <spi_flash.h>
#ifndef CFG_ENV_SPI_BUS
# define CFG_ENV_SPI_BUS 0
#endif
#ifndef CFG_ENV_SPI_CS
# define CFG_ENV_SPI_CS 0
#endif
#ifndef CFG_ENV_SPI_MAX_HZ
# define CFG_ENV_SPI_MAX_HZ 1000000
#endif
#ifndef CFG_ENV_SPI_MODE
# define CFG_ENV_SPI_MODE SPI_MODE_3
#endif
DECLARE_GLOBAL_DATA_PTR;
/* references to names in env_common.c */
extern uchar default_environment[];
extern int default_environment_size;
char * env_name_spec = "SPI Flash";
env_t *env_ptr;
static struct spi_flash *env_flash;
uchar env_get_char_spec(int index)
{
return *((uchar *)(gd->env_addr + index));
}
int saveenv(void)
{
if (!env_flash) {
puts("Environment SPI flash not initialized\n");
return 1;
}
puts("Erasing SPI flash...");
if (spi_flash_erase(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE))
return 1;
puts("Writing to SPI flash...");
if (spi_flash_write(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE, env_ptr))
return 1;
puts("done\n");
return 0;
}
void env_relocate_spec(void)
{
int ret;
env_flash = spi_flash_probe(CFG_ENV_SPI_BUS, CFG_ENV_SPI_CS,
CFG_ENV_SPI_MAX_HZ, CFG_ENV_SPI_MODE);
if (!env_flash)
goto err_probe;
ret = spi_flash_read(env_flash, CFG_ENV_OFFSET, CFG_ENV_SIZE, env_ptr);
if (ret)
goto err_read;
if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)
goto err_crc;
gd->env_valid = 1;
return;
err_read:
spi_flash_free(env_flash);
env_flash = NULL;
err_probe:
err_crc:
puts("*** Warning - bad CRC, using default environment\n\n");
if (default_environment_size > CFG_ENV_SIZE) {
gd->env_valid = 0;
puts("*** Error - default environment is too large\n\n");
return;
}
memset(env_ptr, 0, sizeof(env_t));
memcpy(env_ptr->data, default_environment, default_environment_size);
env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
gd->env_valid = 1;
}
int env_init(void)
{
/* SPI flash isn't usable before relocation */
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 1;
return 0;
}
#endif /* CFG_ENV_IS_IN_SPI_FLASH */

1
common/hush.c
View File

@ -1,4 +1,3 @@
/* vi: set sw=4 ts=4: */
/*
* sh.c -- a prototype Bourne shell grammar parser
* Intended to follow the original Thompson and Ritchie

10
common/image.c
View File

@ -35,6 +35,10 @@
#include <dataflash.h>
#endif
#ifdef CONFIG_LOGBUFFER
#include <logbuff.h>
#endif
#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
#include <rtc.h>
#endif
@ -1013,6 +1017,12 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len,
initrd_high = ~0;
}
#ifdef CONFIG_LOGBUFFER
/* Prevent initrd from overwriting logbuffer */
lmb_reserve(lmb, logbuffer_base() - LOGBUFF_OVERHEAD, LOGBUFF_RESERVE);
#endif
debug ("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
initrd_high, initrd_copy_to_ram);

78
common/lcd.c
View File

@ -50,6 +50,11 @@
#include <lcdvideo.h>
#endif
#if defined(CONFIG_ATMEL_LCD)
#include <atmel_lcdc.h>
#include <nand.h>
#endif
#ifdef CONFIG_LCD
/************************************************************************/
@ -474,14 +479,22 @@ ulong lcd_setmem (ulong addr)
static void lcd_setfgcolor (int color)
{
#ifdef CONFIG_ATMEL_LCD
lcd_color_fg = color;
#else
lcd_color_fg = color & 0x0F;
#endif
}
/*----------------------------------------------------------------------*/
static void lcd_setbgcolor (int color)
{
#ifdef CONFIG_ATMEL_LCD
lcd_color_bg = color;
#else
lcd_color_bg = color & 0x0F;
#endif
}
/*----------------------------------------------------------------------*/
@ -508,7 +521,11 @@ static int lcd_getbgcolor (void)
#ifdef CONFIG_LCD_LOGO
void bitmap_plot (int x, int y)
{
#ifdef CONFIG_ATMEL_LCD
uint *cmap;
#else
ushort *cmap;
#endif
ushort i, j;
uchar *bmap;
uchar *fb;
@ -533,6 +550,8 @@ void bitmap_plot (int x, int y)
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
#elif defined(CONFIG_ATMEL_LCD)
cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
#endif
WATCHDOG_RESET();
@ -540,11 +559,26 @@ void bitmap_plot (int x, int y)
/* Set color map */
for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
ushort colreg = bmp_logo_palette[i];
#ifdef CONFIG_ATMEL_LCD
uint lut_entry;
#ifdef CONFIG_ATMEL_LCD_BGR555
lut_entry = ((colreg & 0x000F) << 11) |
((colreg & 0x00F0) << 2) |
((colreg & 0x0F00) >> 7);
#else /* CONFIG_ATMEL_LCD_RGB565 */
lut_entry = ((colreg & 0x000F) << 1) |
((colreg & 0x00F0) << 3) |
((colreg & 0x0F00) << 4);
#endif
*(cmap + BMP_LOGO_OFFSET) = lut_entry;
cmap++;
#else /* !CONFIG_ATMEL_LCD */
#ifdef CFG_INVERT_COLORS
*cmap++ = 0xffff - colreg;
#else
*cmap++ = colreg;
#endif
#endif /* CONFIG_ATMEL_LCD */
}
WATCHDOG_RESET();
@ -578,7 +612,9 @@ void bitmap_plot (int x, int y)
*/
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
#if !defined(CONFIG_MCC200)
#ifdef CONFIG_ATMEL_LCD
uint *cmap;
#elif !defined(CONFIG_MCC200)
ushort *cmap;
#endif
ushort i, j;
@ -633,6 +669,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
#elif defined(CONFIG_ATMEL_LCD)
cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
#else
# error "Don't know location of color map"
#endif
@ -708,6 +746,10 @@ static void *lcd_logo (void)
#ifdef CONFIG_LCD_INFO
char info[80];
char temp[32];
#ifdef CONFIG_ATMEL_LCD
int i;
ulong dram_size, nand_size;
#endif
#endif /* CONFIG_LCD_INFO */
#ifdef CONFIG_SPLASH_SCREEN
@ -765,6 +807,40 @@ static void *lcd_logo (void)
# endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_ATMEL_LCD
# ifdef CONFIG_LCD_INFO
sprintf (info, "%s", U_BOOT_VERSION);
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info));
sprintf (info, "(C) 2008 ATMEL Corp");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT,
(uchar *)info, strlen(info));
sprintf (info, "at91support@atmel.com");
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
(uchar *)info, strlen(info));
sprintf (info, "%s CPU at %s MHz",
AT91_CPU_NAME,
strmhz(temp, AT91_MAIN_CLOCK));
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
(uchar *)info, strlen(info));
dram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CFG_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
sprintf (info, " %ld MB SDRAM, %ld MB NAND",
dram_size >> 20,
nand_size >> 20 );
lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
(uchar *)info, strlen(info));
# endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_ATMEL_LCD */
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
#else

6
common/main.c
View File

@ -940,12 +940,6 @@ int readline_into_buffer (const char *const prompt, char * buffer)
int rc;
static int initted = 0;
if (!initted) {
hist_init();
initted = 1;
}
/*
* History uses a global array which is not
* writable until after relocation to RAM.

1
common/soft_i2c.c
View File

@ -252,6 +252,7 @@ static uchar read_byte(int ack)
* Read 8 bits, MSB first.
*/
I2C_TRISTATE;
I2C_SDA(1);
data = 0;
for(j = 0; j < 8; j++) {
I2C_SCL(0);

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