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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

This commit is contained in:
Tom Rini 2016-05-25 12:27:44 -04:00
parent 826d06dbdd d7e103c08f
commit 1b80e79586
34 changed files with 426 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/dts/uniphier-ph1-ld11-ref.dts
View File

@ -49,6 +49,18 @@
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
/* for U-Boot only */
/ {
soc {

36
arch/arm/dts/uniphier-ph1-ld11.dtsi
View File

@ -190,6 +190,42 @@
reg = <0x59801000 0x400>;
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 243 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio 3>, <&mio 6>;
};
usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 244 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio 4>, <&mio 6>;
};
usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 245 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio 5>, <&mio 6>;
};
mio: mioctrl@5b3e0000 {
compatible = "socionext,ph1-ld11-mioctrl";
reg = <0x5b3e0000 0x800>;
#clock-cells = <1>;
};
pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld11-pinctrl", "syscon";
reg = <0x5f801000 0xe00>;

5
arch/arm/mach-uniphier/Kconfig
View File

@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
select CPU_V7
config ARCH_UNIPHIER_LD11
bool "UniPhier PH1-LD11 SoC"
select ARM64
select SPL_SEPARATE_BSS
config ARCH_UNIPHIER_LD20
bool "UniPhier PH1-LD20 SoC"
select ARM64

7
arch/arm/mach-uniphier/board_early_init_f.c
View File

@ -62,6 +62,13 @@ int board_early_init_f(void)
uniphier_pxs2_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
case SOC_UNIPHIER_LD11:
uniphier_ld20_pin_init();
led_puts("U1");
uniphier_ld11_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_pin_init();

20
arch/arm/mach-uniphier/boards.c
View File

@ -165,6 +165,23 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
static const struct uniphier_board_data uniphier_ld11_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 16,
},
.dram_ch[1] = {
.base = 0xa0000000,
.size = 0x20000000,
.width = 16,
},
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
@ -216,6 +233,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
{ "socionext,ph1-ld11", &uniphier_ld11_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{ "socionext,ph1-ld20", &uniphier_ld20_data, },
#endif

1
arch/arm/mach-uniphier/boot-mode/Makefile
View File

@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o

2
arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
View File

@ -43,7 +43,7 @@ static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
{BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
{BOOT_DEVICE_NOR, "NOR Boot (XECS1)"},
{BOOT_DEVICE_NOR, "NOR (XECS1)"},
};
static int get_boot_mode_sel(void)

6
arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
View File

@ -36,14 +36,14 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_MMC1, "eMMC (3.3V)"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NOR, "NOR Boot"},
{BOOT_DEVICE_NOR, "NOR (XECS0)"},
};
static int get_boot_mode_sel(void)

2
arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
View File

@ -37,7 +37,7 @@ static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},

14
arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
View File

@ -32,17 +32,17 @@ static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
{BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
{BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
{BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
{BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
{BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
{BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
{BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
{BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
{BOOT_DEVICE_SPI, "SPI (3Byte CS1)"},
{BOOT_DEVICE_SPI, "SPI (4Byte CS1)"},
{BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
{BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
{BOOT_DEVICE_NONE, "Reserved"},
};

2
arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
View File

@ -12,7 +12,7 @@
#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NOR, "NOR boot"},
{BOOT_DEVICE_NOR, "NOR (XECS0)"},
{BOOT_DEVICE_NONE, "External Master"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},

3
arch/arm/mach-uniphier/boot-mode/boot-mode.c
View File

@ -39,7 +39,8 @@ u32 spl_boot_device_raw(void)
case SOC_UNIPHIER_LD6B:
return uniphier_pxs2_boot_device();
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD11:
case SOC_UNIPHIER_LD20:
return uniphier_ld20_boot_device();
#endif

3
arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
View File

@ -39,7 +39,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
uniphier_pxs2_boot_mode_show();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD11:
case SOC_UNIPHIER_LD20:
uniphier_ld20_boot_mode_show();
break;

1
arch/arm/mach-uniphier/clk/Makefile
View File

@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o

28
arch/arm/mach-uniphier/clk/clk-ld11.c Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (C) 2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_ld11_clk_init(void)
{
if (readl(SG_PINMON0) & BIT(27)) {
/* if booted without stand-by MPU */
writel(1, SG_ETPHYPSHUT);
writel(1, SG_ETPHYCNT);
udelay(1); /* wait for regulator level 1.1V -> 2.5V */
writel(3, SG_ETPHYCNT);
writel(3, SG_ETPHYPSHUT);
writel(7, SG_ETPHYCNT);
}
}

2
arch/arm/mach-uniphier/cpu_info.c
View File

@ -45,7 +45,7 @@ int print_cpuinfo(void)
puts("PH1-LD6b (MN2WS0320)");
break;
case 0x31:
puts("PH1-LD11 ()");
puts("PH1-LD11 (SC1405AP1)");
break;
case 0x32:
puts("PH1-LD20 (SC1401AJ1)");

1
arch/arm/mach-uniphier/dram/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else

124
arch/arm/mach-uniphier/dram/umc-ld11.c Normal file
View File

@ -0,0 +1,124 @@
/*
* Copyright (C) 2016 Socionext Inc.
*/
#include <common.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/processor.h>
#include "../init.h"
#include "umc64-regs.h"
#define CONFIG_DDR_FREQ 1866
#define DRAM_CH_NR 2
enum dram_freq {
DRAM_FREQ_1600M,
DRAM_FREQ_NR,
};
enum dram_size {
DRAM_SZ_256M,
DRAM_SZ_512M,
DRAM_SZ_NR,
};
/* umc */
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int ch)
{
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
writel(0x02020200, dc_base + UMC_SPCSETB);
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
return 0;
}
static int umc_ch_init(void __iomem *umc_ch_base,
enum dram_freq freq, unsigned long size, int ch)
{
void __iomem *dc_base = umc_ch_base;
return umc_dc_init(dc_base, freq, size, ch);
}
static void um_init(void __iomem *um_base)
{
writel(0x00000001, um_base + UMC_SIORST);
writel(0x00000001, um_base + UMC_VO0RST);
writel(0x00000001, um_base + UMC_VPERST);
writel(0x00000001, um_base + UMC_RGLRST);
writel(0x00000001, um_base + UMC_A2DRST);
writel(0x00000001, um_base + UMC_DMDRST);
}
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
{
void __iomem *um_base = (void __iomem *)0x5B800000;
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
enum dram_freq freq;
int ch, ret;
switch (bd->dram_freq) {
case 1600:
freq = DRAM_FREQ_1600M;
break;
default:
pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
return -EINVAL;
}
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);
return ret;
}
umc_ch_base += 0x00200000;
}
um_init(um_base);
return 0;
}

6
arch/arm/mach-uniphier/dram/umc-ld20.c
View File

@ -15,7 +15,7 @@
#include "../init.h"
#include "ddrphy-ld20-regs.h"
#include "umc-ld20-regs.h"
#include "umc64-regs.h"
#define DRAM_CH_NR 3
@ -200,9 +200,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
writel(umc_dataset[freq], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
writel(0x00000003, dc_base + UMC_ACSCTLA);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
writel(0x00010200, dc_base + UMC_ACSSETA);
writel(0x00010200, dc_base + UMC_ACSSETB);
writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
writel(0x00004444, dc_base + UMC_FLOWCTLC);

16
arch/arm/mach-uniphier/dram/umc-ld20-regs.h → arch/arm/mach-uniphier/dram/umc64-regs.h
View File

@ -18,13 +18,15 @@
#define UMC_INITSET 0x00000040
#define UMC_INITSTAT 0x00000044
#define UMC_CMDCTLE 0x00000050
#define UMC_CMDCTLF 0x00000054
#define UMC_CMDCTLG 0x00000058
#define UMC_SPCSETB 0x00000084
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
#define UMC_ACSCTLA 0x000000C0
#define UMC_ACSSETA 0x000000C4
#define UMC_ACSSETA 0x000000C0
#define UMC_ACSSETB 0x000000C4
#define UMC_MEMCONF0A 0x00000200
#define UMC_MEMCONF0B 0x00000204
#define UMC_MEMCONFCH 0x00000240
@ -32,6 +34,7 @@
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
#define UMC_ACFETCHCTRL 0x00000460
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
@ -42,6 +45,7 @@
#define UMC_ODTCTL_D1 0x0000061C
#define UMC_RESPCTL 0x00000624
#define UMC_DIRECTBUSCTRLA 0x00000680
#define UMC_DEBUGC 0x00000718
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
@ -70,4 +74,12 @@
#define UMC_MBUS9 0x00002478
#define UMC_MBUS10 0x000024F8
/* UMC1 register */
#define UMC_SIORST 0x00000728
#define UMC_VO0RST 0x0000073c
#define UMC_VPERST 0x00000744
#define UMC_RGLRST 0x00000750
#define UMC_A2DRST 0x00000764
#define UMC_DMDRST 0x00000770
#endif /* UMC_LD20_REGS_H */

1
arch/arm/mach-uniphier/early-clk/Makefile
View File

@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o

32
arch/arm/mach-uniphier/early-clk/early-clk-ld11.c Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sc64-regs.h"
int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL7);
tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
writel(tmp, SC_RSTCTRL7);
/* provide clocks */
tmp = readl(SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_PERI;
writel(tmp, SC_CLKCTRL4);
tmp = readl(SC_CLKCTRL7);
tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
writel(tmp, SC_CLKCTRL7);
return 0;
}

1
arch/arm/mach-uniphier/early-pinctrl/Makefile
View File

@ -3,4 +3,5 @@
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o

4
arch/arm/mach-uniphier/init.h
View File

@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd);
int uniphier_sld8_init(const struct uniphier_board_data *bd);
int uniphier_pro5_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_init(const struct uniphier_board_data *bd);
int uniphier_ld11_init(const struct uniphier_board_data *bd);
int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
@ -81,6 +82,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
@ -91,6 +93,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pin_init(void);
void uniphier_ld4_pin_init(void);
@ -105,6 +108,7 @@ void uniphier_ld4_clk_init(void);
void uniphier_pro4_clk_init(void);
void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);
void uniphier_ld11_clk_init(void);
void uniphier_ld20_clk_init(void);
void cci500_init(int nr_slaves);

1
arch/arm/mach-uniphier/init/Makefile
View File

@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += init-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o

59
arch/arm/mach-uniphier/init/init-ld11.c Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include "../init.h"
#include "../micro-support-card.h"
int uniphier_ld11_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
uniphier_ld20_early_pin_init(bd);
support_card_reset();
support_card_init();
led_puts("L0");
memconf_init(bd);
led_puts("L1");
uniphier_ld11_early_clk_init(bd);
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L4");
{
int res;
res = uniphier_ld11_umc_init(bd);
if (res < 0) {
while (1)
;
}
}
led_puts("L5");
dcache_disable();
led_puts("L6");
return 0;
}

2
arch/arm/mach-uniphier/init/init-ld20.c
View File

@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
led_puts("L5");
dcache_disable();
return 0;
}

5
arch/arm/mach-uniphier/init/init.c
View File

@ -55,6 +55,11 @@ void spl_board_init(void)
uniphier_pxs2_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
case SOC_UNIPHIER_LD11:
uniphier_ld11_init(param);
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_init(param);

1
arch/arm/mach-uniphier/pinctrl/Makefile
View File

@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o

1
arch/arm/mach-uniphier/sbc/Makefile
View File

@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o

3
arch/arm/mach-uniphier/sg-regs.h
View File

@ -59,6 +59,9 @@
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)

31
configs/uniphier_ld11_defconfig Normal file
View File

@ -0,0 +1,31 @@
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

4
drivers/clk/uniphier/clk-uniphier-mio.c
View File

@ -164,6 +164,10 @@ static const struct udevice_id uniphier_mio_clk_match[] = {
.compatible = "socionext,proxstream2-mioctrl",
.data = (ulong)&uniphier_mio_clk_data,
},
{
.compatible = "socionext,ph1-ld11-mioctrl",
.data = (ulong)&uniphier_mio_clk_data,
},
{
.compatible = "socionext,ph1-ld20-mioctrl",
.data = (ulong)&uniphier_mio_clk_data,

12
include/configs/uniphier.h
View File

@ -104,7 +104,11 @@
#define COUNTER_FREQUENCY 50000000
#define CONFIG_GICV3
#define GICD_BASE 0x5fe00000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define GICR_BASE 0x5fe40000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define GICR_BASE 0x5fe80000
#endif
#else
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
@ -270,7 +274,9 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_STACK (0x30014c00)
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK (0x3001c000)
#else
#define CONFIG_SPL_STACK (0x00100000)
@ -301,7 +307,11 @@
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
#define CONFIG_SPL_MAX_SIZE 0x10000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_BSS_START_ADDR 0x30012000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR 0x30016000
#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */