arch: powerpc: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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README
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README
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@ -504,6 +504,9 @@ The following options need to be configured:
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CONFIG_SYS_FSL_IFC_LE
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CONFIG_SYS_FSL_IFC_LE
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Defines the IFC controller register space as Little Endian
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Defines the IFC controller register space as Little Endian
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CONFIG_SYS_FSL_IFC_CLK_DIV
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Defines divider of platform clock(clock input to IFC controller).
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CONFIG_SYS_FSL_PBL_PBI
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CONFIG_SYS_FSL_PBL_PBI
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It enables addition of RCW (Power on reset configuration) in built image.
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It enables addition of RCW (Power on reset configuration) in built image.
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Please refer doc/README.pblimage for more details
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Please refer doc/README.pblimage for more details
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@ -1301,6 +1301,22 @@ config SYS_PPC_E500_DEBUG_TLB
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symbol should be set to the TLB1 entry to be used for this
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symbol should be set to the TLB1 entry to be used for this
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purpose. If unsure, do not change.
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purpose. If unsure, do not change.
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config SYS_FSL_IFC_CLK_DIV
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int "Divider of platform clock"
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depends on FSL_IFC
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default 2 if ARCH_B4420 || \
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ARCH_B4860 || \
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ARCH_T1024 || \
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ARCH_T1023 || \
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ARCH_T1040 || \
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ARCH_T1042 || \
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ARCH_T4160 || \
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ARCH_T4240
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default 1
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help
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Defines divider of platform clock(clock input to
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IFC controller).
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
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void get_sys_info(sys_info_t *sys_info)
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void get_sys_info(sys_info_t *sys_info)
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{
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#ifdef CONFIG_FSL_IFC
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struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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u32 ccr;
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#endif
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_FSL_CORENET
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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unsigned int cpu;
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unsigned int cpu;
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@ -640,10 +636,8 @@ void get_sys_info(sys_info_t *sys_info)
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#endif
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#endif
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#if defined(CONFIG_FSL_IFC)
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#if defined(CONFIG_FSL_IFC)
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ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
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sys_info->freq_localbus = sys_info->freq_systembus /
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ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
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CONFIG_SYS_FSL_IFC_CLK_DIV;
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sys_info->freq_localbus = sys_info->freq_systembus / ccr;
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#endif
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#endif
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}
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}
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