83xx, kmeter: QE_ENET10 errata for Silicon Revision 2.1
old code implemented the QE_ENET10 errata only for Silicon Revision 2.0. New code reads now the Silicon Revision register and sets dependend on the Silicon Revision the values as advised in the QE_ENET10 errata. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -24,6 +24,7 @@
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#include <miiphy.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <pci.h>
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#include <pci.h>
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#include <libfdt.h>
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#include <libfdt.h>
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@ -80,19 +81,22 @@ static int board_init_i2c_busses (void)
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int board_early_init_r (void)
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int board_early_init_r (void)
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{
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{
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void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
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unsigned short svid;
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u32 val;
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/*
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/*
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* Because of errata in the UCCs, we have to write to the reserved
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* Because of errata in the UCCs, we have to write to the reserved
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* registers to slow the clocks down.
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* registers to slow the clocks down.
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*/
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*/
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val = in_be32 (reg);
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svid = SVR_REV(mfspr (SVR));
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/* UCC1 */
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switch (svid) {
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val |= 0x00003000;
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case 0x0020:
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/* UCC2 */
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setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
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val |= 0x0c000000;
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break;
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out_be32 (reg, val);
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case 0x0021:
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clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
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0x00000050, 0x000000a0);
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break;
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}
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/* enable the PHY on the PIGGY */
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/* enable the PHY on the PIGGY */
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setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
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setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
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