x86: Remove sc520 cpu
This x86 CPU variant is no longer required as the boards that use it have been removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
This commit is contained in:
Simon Glass
parent
7e8c53d7d4
commit
1f3a581495
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@ -1,58 +0,0 @@
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#
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# (C) Copyright 2008
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# Graeme Russ, graeme.russ@gmail.com.
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2002
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# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB := $(obj)lib$(SOC).o
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COBJS-$(CONFIG_SYS_SC520) += sc520.o
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COBJS-$(CONFIG_PCI) += sc520_pci.o
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COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o
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COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
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COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
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COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
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SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,45 +0,0 @@
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
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*
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* This program is used to generate definitions needed by
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* assembly language modules.
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*
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* We use the technique used in the OSF Mach kernel code:
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* generate asm statements containing #defines,
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* compile this file to assembler, and then extract the
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* #defines from the assembly-language output.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <asm/arch/sc520.h>
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#include <linux/kbuild.h>
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int main(void)
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{
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DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
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DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
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DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
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DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
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DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
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DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
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DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
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DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
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DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
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DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
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DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
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DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10]));
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DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11]));
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DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12]));
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DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13]));
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DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14]));
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DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15]));
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return 0;
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}
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@ -1,66 +0,0 @@
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/*
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* (C) Copyright 2008-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor-flags.h>
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#include <asm/arch/sc520.h>
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DECLARE_GLOBAL_DATA_PTR;
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sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
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int cpu_init_f(void)
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{
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if (CONFIG_SYS_SC520_HIGH_SPEED) {
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/* set it to 133 MHz and write back */
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writeb(0x02, &sc520_mmcr->cpuctl);
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gd->cpu_clk = 133000000;
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} else {
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/* set it to 100 MHz and write back */
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writeb(0x01, &sc520_mmcr->cpuctl);
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gd->cpu_clk = 100000000;
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}
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/* wait at least one millisecond */
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asm("movl $0x2000, %%ecx\n"
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"0: pushl %%ecx\n"
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"popl %%ecx\n"
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"loop 0b\n" : : : "ecx");
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return x86_cpu_init_f();
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}
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int cpu_init_r(void)
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{
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/* Disable the PAR used for CAR */
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writel(0x0000000, &sc520_mmcr->par[2]);
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/* turn on the SDRAM write buffer */
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writeb(0x11, &sc520_mmcr->dbctl);
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return x86_cpu_init_r();
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}
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@ -1,94 +0,0 @@
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/*
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* (C) Copyright 2010-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/processor-flags.h>
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#include <asm/arch/sc520.h>
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#include <generated/asm-offsets.h>
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.section .text
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.globl car_init
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car_init:
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/*
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* How to enable Cache-As-RAM for the AMD Elan SC520:
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* 1. Turn off the CPU Cache (may not be strictly required)
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* 2. Set code execution PAR (usually the BOOTCS region) to be
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* non-cachable
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* 3. Create a Cachable PAR Region for an area of memory which is
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* a) NOT where the code is being executed
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* b) NOT SDRAM (Controller not initialised yet)
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* c) WILL response to read requests
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* The easiest way to do this is to create a second BOOTCS
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* PAR mappnig with an address != the PAR in step 2
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* 4. Issue a wbinvd to invalidate the CPU cache
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* 5. Turn on the CPU Cache
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* 6. Read 16kB from the cached PAR region setup in step 3
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* 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
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*
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* The following code uses PAR2 as the cached PAR (PAR0 and PAR1
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* are avoided as these are the only two PARs which can be used
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* as PCI BUS Memory regions which the board might require)
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*
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* The configuration of PAR2 must be set in the board configuration
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* file as CONFIG_SYS_SC520_CAR_PAR
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*/
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/* Configure Cache-As-RAM PAR */
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movl $CONFIG_SYS_SC520_CAR_PAR, %eax
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movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
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movl %eax, (%edi)
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/* Trash the cache then turn it on */
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wbinvd
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movl %cr0, %eax
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andl $~(X86_CR0_NW | X86_CR0_CD), %eax
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movl %eax, %cr0
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/*
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* The cache is now enabled and empty. Map a region of memory to
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* it by reading that region.
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*/
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movl $CONFIG_SYS_CAR_ADDR, %esi
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movl $CONFIG_SYS_CAR_SIZE, %ecx
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shrl $2, %ecx /* we are reading longs */
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cld
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rep lodsl
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/* Turn off the cache, but don't trash it */
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movl %cr0, %eax
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orl $(X86_CR0_NW | X86_CR0_CD), %eax
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movl %eax, %cr0
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/* Clear the CAR region */
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xorl %eax, %eax
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movl $CONFIG_SYS_CAR_ADDR, %edi
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movl $CONFIG_SYS_CAR_SIZE, %ecx
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shrl $2, %ecx /* we are writing longs */
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rep stosl
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/*
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* Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
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* Cache-As-RAM
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*/
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jmp car_init_ret
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@ -1,142 +0,0 @@
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/*
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* (C) Copyright 2008-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/pci.h>
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#include <asm/arch/sc520.h>
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static struct {
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u8 priority;
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u16 level_reg;
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u8 level_bit;
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} sc520_irq[] = {
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{ SC520_IRQ0, 0, 0x01 },
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{ SC520_IRQ1, 0, 0x02 },
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{ SC520_IRQ2, 1, 0x02 },
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{ SC520_IRQ3, 0, 0x08 },
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{ SC520_IRQ4, 0, 0x10 },
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{ SC520_IRQ5, 0, 0x20 },
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{ SC520_IRQ6, 0, 0x40 },
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{ SC520_IRQ7, 0, 0x80 },
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{ SC520_IRQ8, 1, 0x01 },
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{ SC520_IRQ9, 1, 0x02 },
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{ SC520_IRQ10, 1, 0x04 },
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{ SC520_IRQ11, 1, 0x08 },
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{ SC520_IRQ12, 1, 0x10 },
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{ SC520_IRQ13, 1, 0x20 },
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{ SC520_IRQ14, 1, 0x40 },
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{ SC520_IRQ15, 1, 0x80 }
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};
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/* The interrupt used for PCI INTA-INTD */
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int sc520_pci_ints[15] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1
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};
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/* utility function to configure a pci interrupt */
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int pci_sc520_set_irq(int pci_pin, int irq)
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{
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int i;
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u8 tmpb;
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u16 tmpw;
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debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
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if (irq < 0 || irq > 15)
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return -1; /* illegal irq */
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if (pci_pin < 0 || pci_pin > 15)
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return -1; /* illegal pci int pin */
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/* first disable any non-pci interrupt source that use
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* this level */
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/* PCI interrupt mapping (A through D)*/
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for (i = 0; i <= 3 ; i++) {
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tmpb = readb(&sc520_mmcr->pci_int_map[i]);
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if (tmpb == sc520_irq[irq].priority)
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
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}
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/* GP IRQ interrupt mapping */
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for (i = 0; i <= 10 ; i++) {
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tmpb = readb(&sc520_mmcr->gp_int_map[i]);
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if (tmpb == sc520_irq[irq].priority)
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
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}
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/* Set the trigger to level */
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tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
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tmpb |= sc520_irq[irq].level_bit;
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writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
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if (pci_pin < 4) {
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/* PCI INTA-INTD */
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/* route the interrupt */
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writeb(sc520_irq[irq].priority,
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&sc520_mmcr->pci_int_map[pci_pin]);
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} else {
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/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
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writeb(sc520_irq[irq].priority,
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&sc520_mmcr->gp_int_map[pci_pin - 4]);
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/* also set the polarity in this case */
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tmpw = readw(&sc520_mmcr->intpinpol);
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tmpw |= (1 << (pci_pin-4));
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writew(tmpw, &sc520_mmcr->intpinpol);
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}
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/* register the pin */
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sc520_pci_ints[pci_pin] = irq;
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return 0; /* OK */
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}
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void pci_sc520_init(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->region_count = pci_set_regions(hose);
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pci_setup_type1(hose);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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/* enable target memory acceses on host brige */
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pci_write_config_word(0, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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}
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@ -1,40 +0,0 @@
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/*
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* (C) Copyright 2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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||||
*
|
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sc520.h>
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DECLARE_GLOBAL_DATA_PTR;
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void reset_cpu(ulong addr)
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{
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printf("Resetting using SC520 MMCR\n");
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/* Write a '1' to the SYS_RST of the RESCFG MMCR */
|
||||
writeb(0x01, &sc520_mmcr->rescfg);
|
||||
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
|
@ -1,479 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* Graeme Russ, <graeme.russ@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor-flags.h>
|
||||
#include <asm/arch/sc520.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct sc520_sdram_info {
|
||||
u8 banks;
|
||||
u8 columns;
|
||||
u8 rows;
|
||||
u8 size;
|
||||
};
|
||||
|
||||
static void sc520_sizemem(void);
|
||||
static void sc520_set_dram_timing(void);
|
||||
static void sc520_set_dram_refresh_rate(void);
|
||||
static void sc520_enable_dram_refresh(void);
|
||||
static void sc520_enable_sdram(void);
|
||||
|
||||
int dram_init_f(void)
|
||||
{
|
||||
sc520_sizemem();
|
||||
sc520_set_dram_timing();
|
||||
sc520_set_dram_refresh_rate();
|
||||
sc520_enable_dram_refresh();
|
||||
sc520_enable_sdram();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void sc520_dummy_write(void)
|
||||
{
|
||||
writew(0x0000, CACHELINESZ);
|
||||
}
|
||||
static inline void sc520_issue_sdram_op_mode_select(u8 command)
|
||||
{
|
||||
writeb(command, &sc520_mmcr->drcctl);
|
||||
sc520_dummy_write();
|
||||
}
|
||||
|
||||
static inline int check_long(u32 test_long)
|
||||
{
|
||||
u8 i;
|
||||
u8 tmp_byte = (u8)(test_long & 0x000000ff);
|
||||
|
||||
for (i = 1; i < 4; i++) {
|
||||
if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int write_and_test(u32 data, u32 address)
|
||||
{
|
||||
writel(data, address);
|
||||
if (readl(address) == data)
|
||||
return 0; /* Good */
|
||||
else
|
||||
return -1; /* Bad */
|
||||
}
|
||||
|
||||
static void sc520_enable_sdram(void)
|
||||
{
|
||||
u32 par_config;
|
||||
|
||||
/* Enable Writes, Caching and Code Execution to SDRAM */
|
||||
par_config = readl(&sc520_mmcr->par[3]);
|
||||
par_config &= ~(SC520_PAR_EXEC_DIS |
|
||||
SC520_PAR_CACHE_DIS |
|
||||
SC520_PAR_WRITE_DIS);
|
||||
writel(par_config, &sc520_mmcr->par[3]);
|
||||
|
||||
par_config = readl(&sc520_mmcr->par[4]);
|
||||
par_config &= ~(SC520_PAR_EXEC_DIS |
|
||||
SC520_PAR_CACHE_DIS |
|
||||
SC520_PAR_WRITE_DIS);
|
||||
writel(par_config, &sc520_mmcr->par[4]);
|
||||
}
|
||||
|
||||
static void sc520_set_dram_timing(void)
|
||||
{
|
||||
u8 drctmctl = 0x00;
|
||||
|
||||
#if defined CONFIG_SYS_SDRAM_DRCTMCTL
|
||||
/* just have your hardware designer _GIVE_ you what you need here! */
|
||||
drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
|
||||
#else
|
||||
switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
|
||||
case 2:
|
||||
break;
|
||||
case 3:
|
||||
drctmctl |= 0x01;
|
||||
break;
|
||||
case 4:
|
||||
default:
|
||||
drctmctl |= 0x02;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
|
||||
case 2:
|
||||
break;
|
||||
case 3:
|
||||
drctmctl |= 0x04;
|
||||
break;
|
||||
case 4:
|
||||
default:
|
||||
drctmctl |= 0x08;
|
||||
break;
|
||||
|
||||
case 6:
|
||||
drctmctl |= 0x0c;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
|
||||
case 2:
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
drctmctl |= 0x10;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
writeb(drctmctl, &sc520_mmcr->drctmctl);
|
||||
|
||||
/* Issue load mode register command */
|
||||
sc520_issue_sdram_op_mode_select(0x03);
|
||||
}
|
||||
|
||||
static void sc520_set_dram_refresh_rate(void)
|
||||
{
|
||||
u8 drctl;
|
||||
|
||||
drctl = readb(&sc520_mmcr->drcctl);
|
||||
drctl &= 0xcf;
|
||||
|
||||
switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
|
||||
case 78:
|
||||
break;
|
||||
case 156:
|
||||
default:
|
||||
drctl |= 0x10;
|
||||
break;
|
||||
case 312:
|
||||
drctl |= 0x20;
|
||||
break;
|
||||
case 624:
|
||||
drctl |= 0x30;
|
||||
break;
|
||||
}
|
||||
|
||||
writeb(drctl, &sc520_mmcr->drcctl);
|
||||
}
|
||||
|
||||
static void sc520_enable_dram_refresh(void)
|
||||
{
|
||||
u8 drctl;
|
||||
|
||||
drctl = readb(&sc520_mmcr->drcctl);
|
||||
drctl &= 0x30; /* keep refresh rate */
|
||||
drctl |= 0x08; /* enable refresh, normal mode */
|
||||
|
||||
writeb(drctl, &sc520_mmcr->drcctl);
|
||||
}
|
||||
|
||||
static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
|
||||
{
|
||||
u32 col_data;
|
||||
u32 row_data;
|
||||
|
||||
u32 drcbendadr;
|
||||
u16 drccfg;
|
||||
|
||||
u8 banks = 0x00;
|
||||
u8 columns = 0x00;
|
||||
u8 rows = 0x00;
|
||||
|
||||
bank_info->banks = 0x00;
|
||||
bank_info->columns = 0x00;
|
||||
bank_info->rows = 0x00;
|
||||
bank_info->size = 0x00;
|
||||
|
||||
if ((bank < 0) || (bank > 3)) {
|
||||
printf("Bad Bank ID\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Save configuration */
|
||||
drcbendadr = readl(&sc520_mmcr->drcbendadr);
|
||||
drccfg = readw(&sc520_mmcr->drccfg);
|
||||
|
||||
/* Setup SDRAM Bank to largest possible size */
|
||||
writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
|
||||
|
||||
/* Set ending address for this bank */
|
||||
writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
|
||||
|
||||
/* write col 11 wrap adr */
|
||||
if (write_and_test(COL11_DATA, COL11_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write col 10 wrap adr */
|
||||
if (write_and_test(COL10_DATA, COL10_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write col 9 wrap adr */
|
||||
if (write_and_test(COL09_DATA, COL09_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write col 8 wrap adr */
|
||||
if (write_and_test(COL08_DATA, COL08_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
col_data = readl(COL11_ADR);
|
||||
|
||||
/* All four bytes in the read long must be the same */
|
||||
if (check_long(col_data) < 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
|
||||
columns = (u8)(col_data & 0x000000ff);
|
||||
else
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write row 14 wrap adr */
|
||||
if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write row 13 wrap adr */
|
||||
if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write row 12 wrap adr */
|
||||
if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/* write row 11 wrap adr */
|
||||
if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
/*
|
||||
* read data @ row 12 wrap adr to determine number of banks,
|
||||
* and read data @ row 14 wrap adr to determine number of rows.
|
||||
* if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
|
||||
* if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
|
||||
* if data @ row 12 wrap == 11 or 12, we have 4 banks,
|
||||
*/
|
||||
row_data = readl(ROW12_ADR);
|
||||
|
||||
/* All four bytes in the read long must be the same */
|
||||
if (check_long(row_data) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
switch (row_data) {
|
||||
case ROW10_DATA:
|
||||
banks = 2;
|
||||
break;
|
||||
|
||||
case ROW11_DATA:
|
||||
case ROW12_DATA:
|
||||
banks = 4;
|
||||
break;
|
||||
|
||||
default:
|
||||
goto restore_and_exit;
|
||||
}
|
||||
|
||||
row_data = readl(ROW14_ADR);
|
||||
|
||||
/* All four bytes in the read long must be the same */
|
||||
if (check_long(row_data) != 0)
|
||||
goto restore_and_exit;
|
||||
|
||||
switch (row_data) {
|
||||
case ROW11_DATA:
|
||||
case ROW12_DATA:
|
||||
case ROW13_DATA:
|
||||
case ROW14_DATA:
|
||||
rows = (u8)(row_data & 0x000000ff);
|
||||
break;
|
||||
|
||||
default:
|
||||
goto restore_and_exit;
|
||||
}
|
||||
|
||||
bank_info->banks = banks;
|
||||
bank_info->columns = columns;
|
||||
bank_info->rows = rows;
|
||||
|
||||
if ((bank_info->banks != 0) &&
|
||||
(bank_info->columns != 0) &&
|
||||
(bank_info->rows != 0)) {
|
||||
bank_info->size = bank_info->rows;
|
||||
bank_info->size >>= (11 - bank_info->columns);
|
||||
bank_info->size++;
|
||||
}
|
||||
|
||||
restore_and_exit:
|
||||
/* Restore configuration */
|
||||
writel(drcbendadr, &sc520_mmcr->drcbendadr);
|
||||
writew(drccfg, &sc520_mmcr->drccfg);
|
||||
}
|
||||
|
||||
static void sc520_setup_sizemem(void)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
/* Disable write buffer */
|
||||
writeb(0x00, &sc520_mmcr->dbctl);
|
||||
|
||||
/* Disable ECC */
|
||||
writeb(0x00, &sc520_mmcr->eccctl);
|
||||
|
||||
/* Set slowest SDRAM timing */
|
||||
writeb(0x1e, &sc520_mmcr->drctmctl);
|
||||
|
||||
/* Issue a NOP to all SDRAM banks */
|
||||
sc520_issue_sdram_op_mode_select(0x01);
|
||||
|
||||
/* Delay for 100 microseconds */
|
||||
udelay(100);
|
||||
|
||||
/* Issue 'All Banks Precharge' command */
|
||||
sc520_issue_sdram_op_mode_select(0x02);
|
||||
|
||||
/* Issue 2 'Auto Refresh Enable' command */
|
||||
sc520_issue_sdram_op_mode_select(0x04);
|
||||
sc520_dummy_write();
|
||||
|
||||
/* Issue 'Load Mode Register' command */
|
||||
sc520_issue_sdram_op_mode_select(0x03);
|
||||
|
||||
/* Issue 8 more 'Auto Refresh Enable' commands */
|
||||
sc520_issue_sdram_op_mode_select(0x04);
|
||||
for (i = 0; i < 7; i++)
|
||||
sc520_dummy_write();
|
||||
|
||||
/* Set control register to 'Normal Mode' */
|
||||
writeb(0x00, &sc520_mmcr->drcctl);
|
||||
}
|
||||
|
||||
static void sc520_sizemem(void)
|
||||
{
|
||||
struct sc520_sdram_info sdram_info[4];
|
||||
u8 bank_config = 0x00;
|
||||
u8 end_addr = 0x00;
|
||||
u16 drccfg = 0x0000;
|
||||
u32 drcbendadr = 0x00000000;
|
||||
u8 i;
|
||||
|
||||
/* Use PARs to disable caching of maximum allowable 256MB SDRAM */
|
||||
writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
|
||||
writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
|
||||
|
||||
sc520_setup_sizemem();
|
||||
|
||||
gd->ram_size = 0;
|
||||
|
||||
/* Size each SDRAM bank */
|
||||
for (i = 0; i <= 3; i++) {
|
||||
sc520_get_bank_info(i, &sdram_info[i]);
|
||||
|
||||
if (sdram_info[i].banks != 0) {
|
||||
/* Update Configuration register */
|
||||
bank_config = sdram_info[i].columns - 8;
|
||||
|
||||
if (sdram_info[i].banks == 4)
|
||||
bank_config |= 0x08;
|
||||
|
||||
drccfg |= bank_config << (i * 4);
|
||||
|
||||
/* Update End Address register */
|
||||
end_addr += sdram_info[i].size;
|
||||
drcbendadr |= (end_addr | 0x80) << (i * 8);
|
||||
|
||||
gd->ram_size += sdram_info[i].size << 22;
|
||||
}
|
||||
|
||||
/* Issue 'All Banks Precharge' command */
|
||||
sc520_issue_sdram_op_mode_select(0x02);
|
||||
|
||||
/* Set control register to 'Normal Mode' */
|
||||
writeb(0x00, &sc520_mmcr->drcctl);
|
||||
}
|
||||
|
||||
writel(drcbendadr, &sc520_mmcr->drcbendadr);
|
||||
writew(drccfg, &sc520_mmcr->drccfg);
|
||||
|
||||
/* Clear PARs preventing caching of SDRAM */
|
||||
writel(0x00000000, &sc520_mmcr->par[3]);
|
||||
writel(0x00000000, &sc520_mmcr->par[4]);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
ulong dram_ctrl;
|
||||
ulong dram_present = 0x00000000;
|
||||
|
||||
/*
|
||||
* We read-back the configuration of the dram
|
||||
* controller that the assembly code wrote
|
||||
*/
|
||||
dram_ctrl = readl(&sc520_mmcr->drcbendadr);
|
||||
|
||||
gd->bd->bi_dram[0].start = 0;
|
||||
if (dram_ctrl & 0x80) {
|
||||
/* bank 0 enabled */
|
||||
gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
|
||||
dram_present = gd->bd->bi_dram[1].start;
|
||||
gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
|
||||
} else {
|
||||
gd->bd->bi_dram[0].size = 0;
|
||||
gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
|
||||
}
|
||||
|
||||
if (dram_ctrl & 0x8000) {
|
||||
/* bank 1 enabled */
|
||||
gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
|
||||
dram_present = gd->bd->bi_dram[2].start;
|
||||
gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
|
||||
gd->bd->bi_dram[1].start;
|
||||
} else {
|
||||
gd->bd->bi_dram[1].size = 0;
|
||||
gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
|
||||
}
|
||||
|
||||
if (dram_ctrl & 0x800000) {
|
||||
/* bank 2 enabled */
|
||||
gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
|
||||
dram_present = gd->bd->bi_dram[3].start;
|
||||
gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
|
||||
gd->bd->bi_dram[2].start;
|
||||
} else {
|
||||
gd->bd->bi_dram[2].size = 0;
|
||||
gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
|
||||
}
|
||||
|
||||
if (dram_ctrl & 0x80000000) {
|
||||
/* bank 3 enabled */
|
||||
dram_present = (dram_ctrl & 0x7f000000) >> 2;
|
||||
gd->bd->bi_dram[3].size = dram_present -
|
||||
gd->bd->bi_dram[3].start;
|
||||
} else {
|
||||
gd->bd->bi_dram[3].size = 0;
|
||||
}
|
||||
|
||||
gd->ram_size = dram_present;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/ssi.h>
|
||||
#include <asm/arch/sc520.h>
|
||||
|
||||
int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
|
||||
{
|
||||
u8 temp = 0;
|
||||
|
||||
if (freq >= 8192)
|
||||
temp |= CTL_CLK_SEL_4;
|
||||
else if (freq >= 4096)
|
||||
temp |= CTL_CLK_SEL_8;
|
||||
else if (freq >= 2048)
|
||||
temp |= CTL_CLK_SEL_16;
|
||||
else if (freq >= 1024)
|
||||
temp |= CTL_CLK_SEL_32;
|
||||
else if (freq >= 512)
|
||||
temp |= CTL_CLK_SEL_64;
|
||||
else if (freq >= 256)
|
||||
temp |= CTL_CLK_SEL_128;
|
||||
else if (freq >= 128)
|
||||
temp |= CTL_CLK_SEL_256;
|
||||
else
|
||||
temp |= CTL_CLK_SEL_512;
|
||||
|
||||
if (!lsb_first)
|
||||
temp |= MSBF_ENB;
|
||||
|
||||
if (inv_clock)
|
||||
temp |= CLK_INV_ENB;
|
||||
|
||||
if (inv_phase)
|
||||
temp |= PHS_INV_ENB;
|
||||
|
||||
writeb(temp, &sc520_mmcr->ssictl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 ssi_txrx_byte(u8 data)
|
||||
{
|
||||
writeb(data, &sc520_mmcr->ssixmit);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
|
||||
;
|
||||
writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
|
||||
;
|
||||
|
||||
return readb(&sc520_mmcr->ssircv);
|
||||
}
|
||||
|
||||
void ssi_tx_byte(u8 data)
|
||||
{
|
||||
writeb(data, &sc520_mmcr->ssixmit);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
|
||||
;
|
||||
writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
|
||||
}
|
||||
|
||||
u8 ssi_rx_byte(void)
|
||||
{
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
|
||||
;
|
||||
writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
|
||||
while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
|
||||
;
|
||||
|
||||
return readb(&sc520_mmcr->ssircv);
|
||||
}
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2008-2011
|
||||
* Graeme Russ, <graeme.russ@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/interrupt.h>
|
||||
#include <asm/arch/sc520.h>
|
||||
|
||||
void sc520_timer_isr(void)
|
||||
{
|
||||
/* Ack the GP Timer Interrupt */
|
||||
writeb(0x02, &sc520_mmcr->gptmrsta);
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
/* Register the SC520 specific timer interrupt handler */
|
||||
register_timer_isr(sc520_timer_isr);
|
||||
|
||||
/* Install interrupt handler for GP Timer 1 */
|
||||
irq_install_handler (0, timer_isr, NULL);
|
||||
|
||||
/* Map GP Timer 1 to Master PIC IR0 */
|
||||
writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
|
||||
|
||||
/* Disable GP Timers 1 & 2 - Allow configuration writes */
|
||||
writew(0x4000, &sc520_mmcr->gptmr1ctl);
|
||||
writew(0x4000, &sc520_mmcr->gptmr2ctl);
|
||||
|
||||
/* Reset GP Timers 1 & 2 */
|
||||
writew(0x0000, &sc520_mmcr->gptmr1cnt);
|
||||
writew(0x0000, &sc520_mmcr->gptmr2cnt);
|
||||
|
||||
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
|
||||
writew(83, &sc520_mmcr->gptmr2maxcmpa);
|
||||
writew(0xc001, &sc520_mmcr->gptmr2ctl);
|
||||
|
||||
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
|
||||
writew(100, &sc520_mmcr->gptmr1maxcmpa);
|
||||
writew(0xe009, &sc520_mmcr->gptmr1ctl);
|
||||
|
||||
unmask_irq(0);
|
||||
|
||||
/* Clear the GP Timer 1 status register to get the show rolling*/
|
||||
writeb(0x02, &sc520_mmcr->gptmrsta);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Allow boards to override udelay implementation */
|
||||
void __udelay(unsigned long usec)
|
||||
__attribute__((weak, alias("sc520_udelay")));
|
||||
|
||||
void sc520_udelay(unsigned long usec)
|
||||
{
|
||||
int m = 0;
|
||||
long u;
|
||||
|
||||
readw(&sc520_mmcr->swtmrmilli);
|
||||
readw(&sc520_mmcr->swtmrmicro);
|
||||
|
||||
do {
|
||||
m += readw(&sc520_mmcr->swtmrmilli);
|
||||
u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
|
||||
} while (u < usec);
|
||||
}
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_IC_SC520_PCI_H_
|
||||
#define _ASM_IC_SC520_PCI_H_ 1
|
||||
|
||||
/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
|
||||
#define SC520_REG_ADDR 0x00000cf8
|
||||
#define SC520_REG_DATA 0x00000cfc
|
||||
|
||||
#define SC520_ISA_MEM_PHYS 0x00000000
|
||||
#define SC520_ISA_MEM_BUS 0x00000000
|
||||
#define SC520_ISA_MEM_SIZE 0x01000000
|
||||
|
||||
#define SC520_ISA_IO_PHYS 0x00000000
|
||||
#define SC520_ISA_IO_BUS 0x00000000
|
||||
#define SC520_ISA_IO_SIZE 0x00001000
|
||||
|
||||
/* PCI I/O space from 0x1000 to 0xdfff
|
||||
* (make 0xe000-0xfdff available for stuff like PCCard boot) */
|
||||
#define SC520_PCI_IO_PHYS 0x00001000
|
||||
#define SC520_PCI_IO_BUS 0x00001000
|
||||
#define SC520_PCI_IO_SIZE 0x0000d000
|
||||
|
||||
/* system memory from 0x00000000 to 0x0fffffff */
|
||||
#define SC520_PCI_MEMORY_PHYS 0x00000000
|
||||
#define SC520_PCI_MEMORY_BUS 0x00000000
|
||||
#define SC520_PCI_MEMORY_SIZE 0x10000000
|
||||
|
||||
/* PCI bus memory from 0x10000000 to 0x26ffffff
|
||||
* (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
|
||||
#define SC520_PCI_MEM_PHYS 0x10000000
|
||||
#define SC520_PCI_MEM_BUS 0x10000000
|
||||
#define SC520_PCI_MEM_SIZE 0x17000000
|
||||
|
||||
/* pin number used for PCI interrupt mappings */
|
||||
#define SC520_PCI_INTA 0
|
||||
#define SC520_PCI_INTB 1
|
||||
#define SC520_PCI_INTC 2
|
||||
#define SC520_PCI_INTD 3
|
||||
#define SC520_PCI_GPIRQ0 4
|
||||
#define SC520_PCI_GPIRQ1 5
|
||||
#define SC520_PCI_GPIRQ2 6
|
||||
#define SC520_PCI_GPIRQ3 7
|
||||
#define SC520_PCI_GPIRQ4 8
|
||||
#define SC520_PCI_GPIRQ5 9
|
||||
#define SC520_PCI_GPIRQ6 10
|
||||
#define SC520_PCI_GPIRQ7 11
|
||||
#define SC520_PCI_GPIRQ8 12
|
||||
#define SC520_PCI_GPIRQ9 13
|
||||
#define SC520_PCI_GPIRQ10 14
|
||||
|
||||
extern int sc520_pci_ints[];
|
||||
|
||||
void pci_sc520_init(struct pci_controller *hose);
|
||||
int pci_set_regions(struct pci_controller *hose);
|
||||
int pci_sc520_set_irq(int pci_pin, int irq);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,372 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_IC_SC520_H_
|
||||
#define _ASM_IC_SC520_H_ 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
void init_sc520(void);
|
||||
unsigned long init_sc520_dram(void);
|
||||
void sc520_udelay(unsigned long usec);
|
||||
|
||||
/* Memory mapped configuration registers */
|
||||
typedef struct sc520_mmcr {
|
||||
u16 revid; /* ElanSC520 microcontroller revision id */
|
||||
u8 cpuctl; /* am5x86 CPU control */
|
||||
|
||||
u8 pad_0x003[0x0d];
|
||||
|
||||
u8 drcctl; /* SDRAM control */
|
||||
u8 pad_0x011[0x01];
|
||||
u8 drctmctl; /* SDRAM timing control */
|
||||
u8 pad_0x013[0x01];
|
||||
u16 drccfg; /* SDRAM bank configuration*/
|
||||
u8 pad_0x016[0x02];
|
||||
u32 drcbendadr; /* SDRAM bank 0-3 ending address*/
|
||||
u8 pad_0x01c[0x04];
|
||||
u8 eccctl; /* ECC control */
|
||||
u8 eccsta; /* ECC status */
|
||||
u8 eccckbpos; /* ECC check bit position */
|
||||
u8 ecccktest; /* ECC Check Code Test */
|
||||
u32 eccsbadd; /* ECC single-bit error address */
|
||||
u32 eccmbadd; /* ECC multi-bit error address */
|
||||
|
||||
u8 pad_0x02c[0x14];
|
||||
|
||||
u8 dbctl; /* SDRAM buffer control */
|
||||
|
||||
u8 pad_0x041[0x0f];
|
||||
|
||||
u16 bootcsctl; /* /BOOTCS control */
|
||||
u8 pad_0x052[0x02];
|
||||
u16 romcs1ctl; /* /ROMCS1 control */
|
||||
u16 romcs2ctl; /* /ROMCS2 control */
|
||||
|
||||
u8 pad_0x058[0x08];
|
||||
|
||||
u16 hbctl; /* host bridge control */
|
||||
u16 hbtgtirqctl; /* host bridge target interrupt control */
|
||||
u16 hbtgtirqsta; /* host bridge target interrupt status */
|
||||
u16 hbmstirqctl; /* host bridge target interrupt control */
|
||||
u16 hbmstirqsta; /* host bridge master interrupt status */
|
||||
u8 pad_0x06a[0x02];
|
||||
u32 mstintadd; /* host bridge master interrupt address */
|
||||
|
||||
u8 sysarbctl; /* system arbiter control */
|
||||
u8 pciarbsta; /* PCI bus arbiter status */
|
||||
u16 sysarbmenb; /* system arbiter master enable */
|
||||
u32 arbprictl; /* arbiter priority control */
|
||||
|
||||
u8 pad_0x078[0x08];
|
||||
|
||||
u8 adddecctl; /* address decode control */
|
||||
u8 pad_0x081[0x01];
|
||||
u16 wpvsta; /* write-protect violation status */
|
||||
u8 pad_0x084[0x04];
|
||||
u32 par[16]; /* programmable address regions */
|
||||
|
||||
u8 pad_0x0c8[0x0b38];
|
||||
|
||||
u8 gpecho; /* GP echo mode */
|
||||
u8 gpcsdw; /* GP chip select data width */
|
||||
u16 gpcsqual; /* GP chip select qualification */
|
||||
u8 pad_0xc04[0x4];
|
||||
u8 gpcsrt; /* GP chip select recovery time */
|
||||
u8 gpcspw; /* GP chip select pulse width */
|
||||
u8 gpcsoff; /* GP chip select offset */
|
||||
u8 gprdw; /* GP read pulse width */
|
||||
u8 gprdoff; /* GP read offset */
|
||||
u8 gpwrw; /* GP write pulse width */
|
||||
u8 gpwroff; /* GP write offset */
|
||||
u8 gpalew; /* GP ale pulse width */
|
||||
u8 gpaleoff; /* GP ale offset */
|
||||
|
||||
u8 pad_0xc11[0x0f];
|
||||
|
||||
u16 piopfs15_0; /* PIO15-PIO0 pin function select */
|
||||
u16 piopfs31_16; /* PIO31-PIO16 pin function select */
|
||||
u8 cspfs; /* chip select pin function select */
|
||||
u8 pad_0xc25[0x01];
|
||||
u8 clksel; /* clock select */
|
||||
u8 pad_0xc27[0x01];
|
||||
u16 dsctl; /* drive strength control */
|
||||
u16 piodir15_0; /* PIO15-PIO0 direction */
|
||||
u16 piodir31_16; /* PIO31-PIO16 direction */
|
||||
u8 pad_0xc2e[0x02];
|
||||
u16 piodata15_0 ; /* PIO15-PIO0 data */
|
||||
u16 piodata31_16; /* PIO31-PIO16 data */
|
||||
u16 pioset15_0; /* PIO15-PIO0 set */
|
||||
u16 pioset31_16; /* PIO31-PIO16 set */
|
||||
u16 pioclr15_0; /* PIO15-PIO0 clear */
|
||||
u16 pioclr31_16; /* PIO31-PIO16 clear */
|
||||
|
||||
u8 pad_0xc3c[0x24];
|
||||
|
||||
u16 swtmrmilli; /* software timer millisecond count */
|
||||
u16 swtmrmicro; /* software timer microsecond count */
|
||||
u8 swtmrcfg; /* software timer configuration */
|
||||
|
||||
u8 pad_0xc65[0x0b];
|
||||
|
||||
u8 gptmrsta; /* GP timers status register */
|
||||
u8 pad_0xc71;
|
||||
u16 gptmr0ctl; /* GP timer 0 mode/control */
|
||||
u16 gptmr0cnt; /* GP timer 0 count */
|
||||
u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
|
||||
u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
|
||||
u16 gptmr1ctl; /* GP timer 1 mode/control */
|
||||
u16 gptmr1cnt; /* GP timer 1 count */
|
||||
u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
|
||||
u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
|
||||
u16 gptmr2ctl; /* GP timer 2 mode/control */
|
||||
u16 gptmr2cnt; /* GP timer 2 count */
|
||||
u8 pad_0xc86[0x08];
|
||||
u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */
|
||||
|
||||
u8 pad_0xc90[0x20];
|
||||
|
||||
u16 wdtmrctl; /* watchdog timer control */
|
||||
u16 wdtmrcntl; /* watchdog timer count low */
|
||||
u16 wdtmrcnth; /* watchdog timer count high */
|
||||
|
||||
u8 pad_0xcb6[0x0a];
|
||||
|
||||
u8 uart1ctl; /* UART 1 general control */
|
||||
u8 uart1sta; /* UART 1 general status */
|
||||
u8 uart1fcrshad; /* UART 1 FIFO control shadow */
|
||||
u8 pad_0xcc3[0x01];
|
||||
u8 uart2ctl; /* UART 2 general control */
|
||||
u8 uart2sta; /* UART 2 general status */
|
||||
u8 uart2fcrshad; /* UART 2 FIFO control shadow */
|
||||
|
||||
u8 pad_0xcc7[0x09];
|
||||
|
||||
u8 ssictl; /* SSI control */
|
||||
u8 ssixmit; /* SSI transmit */
|
||||
u8 ssicmd; /* SSI command */
|
||||
u8 ssista; /* SSI status */
|
||||
u8 ssircv; /* SSI receive */
|
||||
|
||||
u8 pad_0xcd5[0x2b];
|
||||
|
||||
u8 picicr; /* interrupt control */
|
||||
u8 pad_0xd01[0x01];
|
||||
u8 pic_mode[3]; /* PIC interrupt mode */
|
||||
u8 pad_0xd05[0x03];
|
||||
u16 swint16_1; /* software interrupt 16-1 control */
|
||||
u8 swint22_17; /* software interrupt 22-17/NMI control */
|
||||
u8 pad_0xd0b[0x05];
|
||||
u16 intpinpol; /* interrupt pin polarity */
|
||||
u8 pad_0xd12[0x02];
|
||||
u16 pcihostmap; /* PCI host bridge interrupt mapping */
|
||||
u8 pad_0xd16[0x02];
|
||||
u16 eccmap; /* ECC interrupt mapping */
|
||||
u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */
|
||||
u8 pad_0xd1d[0x03];
|
||||
u8 pit_int_map[3]; /* PIT interrupt mapping */
|
||||
u8 pad_0xd23[0x05];
|
||||
u8 uart_int_map[2]; /* UART interrupt mapping */
|
||||
u8 pad_0xd2a[0x06];
|
||||
u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/
|
||||
u8 pad_0xd34[0x0c];
|
||||
u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */
|
||||
u8 ssimap; /* SSI interrupt mapping register */
|
||||
u8 wdtmap; /* watchdog timer interrupt mapping */
|
||||
u8 rtcmap; /* RTC interrupt mapping register */
|
||||
u8 wpvmap; /* write-protect interrupt mapping */
|
||||
u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */
|
||||
u8 ferrmap; /* floating point error interrupt mapping */
|
||||
u8 pad_0xd47[0x09];
|
||||
u8 gp_int_map[11]; /* GP IRQ interrupt mapping */
|
||||
|
||||
u8 pad_0xd5b[0x15];
|
||||
|
||||
u8 sysinfo; /* system board information */
|
||||
u8 pad_0xd71[0x01];
|
||||
u8 rescfg; /* reset configuration */
|
||||
u8 pad_0xd73[0x01];
|
||||
u8 ressta; /* reset status */
|
||||
|
||||
u8 pad_0xd75[0x0b];
|
||||
|
||||
u8 gpdmactl; /* GP-DMA Control */
|
||||
u8 gpdmammio; /* GP-DMA memory-mapped I/O */
|
||||
u16 gpdmaextchmapa; /* GP-DMA resource channel map a */
|
||||
u16 gpdmaextchmapb; /* GP-DMA resource channel map b */
|
||||
u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */
|
||||
u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */
|
||||
u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */
|
||||
u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */
|
||||
u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */
|
||||
u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */
|
||||
u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */
|
||||
u8 pad_0xd8d[0x03];
|
||||
u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
|
||||
u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
|
||||
u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
|
||||
u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
|
||||
u8 pad_0xd94[0x4];
|
||||
u8 gpdmabcctl; /* buffer chaining control */
|
||||
u8 gpdmabcsta; /* buffer chaining status */
|
||||
u8 gpdmabsintenb; /* buffer chaining interrupt enable */
|
||||
u8 gpdmabcval; /* buffer chaining valid */
|
||||
u8 pad_0xd9c[0x04];
|
||||
u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */
|
||||
u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */
|
||||
u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */
|
||||
u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */
|
||||
u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */
|
||||
u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */
|
||||
u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */
|
||||
u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */
|
||||
u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */
|
||||
u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */
|
||||
u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */
|
||||
u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */
|
||||
u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */
|
||||
u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */
|
||||
u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */
|
||||
u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */
|
||||
|
||||
u8 pad_0xdc0[0x0240];
|
||||
} sc520_mmcr_t;
|
||||
|
||||
extern sc520_mmcr_t *sc520_mmcr;
|
||||
|
||||
#endif
|
||||
|
||||
/* Memory Mapped Control Registers (MMCR) Base Address */
|
||||
#define SC520_MMCR_BASE 0xfffef000
|
||||
|
||||
/*
|
||||
* PARs for maximum allowable 256MB of SDRAM @ 0x00000000
|
||||
* Two PARs are required due to maximum PAR size of 128MB
|
||||
* These are used in the SDRAM sizing code to disable caching
|
||||
*
|
||||
* 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
|
||||
* 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
|
||||
* \ / | | | | \----+----/ \-----+------/
|
||||
* | | | | | | +---------- Start at 0x00000000
|
||||
* | | | | | | 0x08000000
|
||||
* | | | | | +----------------------- 128MB Region Size
|
||||
* | | | | | ((2047 + 1) * 64kB)
|
||||
* | | | | +------------------------------ 64kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled
|
||||
* | | +---------------------------------- Caching Enabled
|
||||
* | +------------------------------------ Execution Enabled
|
||||
* +--------------------------------------- SDRAM
|
||||
*/
|
||||
#define SC520_SDRAM1_PAR 0xe3ffc000
|
||||
#define SC520_SDRAM2_PAR 0xe3ffc800
|
||||
|
||||
#define SC520_PAR_WRITE_DIS 0x04000000
|
||||
#define SC520_PAR_CACHE_DIS 0x08000000
|
||||
#define SC520_PAR_EXEC_DIS 0x10000000
|
||||
|
||||
/*
|
||||
* Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
|
||||
* required for DRAM sizing code
|
||||
*/
|
||||
|
||||
/* MMCR Register bits (not all of them :) ) */
|
||||
|
||||
/* SSI Stuff */
|
||||
#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
|
||||
#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
|
||||
#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
|
||||
#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
|
||||
#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
|
||||
#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
|
||||
#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
|
||||
#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
|
||||
|
||||
#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
|
||||
#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
|
||||
#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
|
||||
#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
|
||||
|
||||
#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
|
||||
#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
|
||||
#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
|
||||
#define SSISTA_BSY 0x02 /* SSI Busy */
|
||||
#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
|
||||
|
||||
/* BITS for SC520_ADDDECCTL: */
|
||||
#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
|
||||
#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
|
||||
#define RTC_DIS 0x04 /* RTC Disable */
|
||||
#define UART2_DIS 0x02 /* UART2 Disable */
|
||||
#define UART1_DIS 0x01 /* UART1 Disable */
|
||||
|
||||
/*
|
||||
* Defines used for SDRAM Sizing (number of columns and rows)
|
||||
* Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
|
||||
* Elan SC520 Microcontroller User's Manual (Order #22004B)
|
||||
*/
|
||||
#define CACHELINESZ 0x00000010
|
||||
|
||||
#define COL11_ADR 0x0e001e00
|
||||
#define COL10_ADR 0x0e000e00
|
||||
#define COL09_ADR 0x0e000600
|
||||
#define COL08_ADR 0x0e000200
|
||||
#define COL11_DATA 0x0b0b0b0b
|
||||
#define COL10_DATA 0x0a0a0a0a
|
||||
#define COL09_DATA 0x09090909
|
||||
#define COL08_DATA 0x08080808
|
||||
|
||||
#define ROW14_ADR 0x0f000000
|
||||
#define ROW13_ADR 0x07000000
|
||||
#define ROW12_ADR 0x03000000
|
||||
#define ROW11_ADR 0x01000000
|
||||
#define ROW10_ADR 0x00000000
|
||||
#define ROW14_DATA 0x3f3f3f3f
|
||||
#define ROW13_DATA 0x1f1f1f1f
|
||||
#define ROW12_DATA 0x0f0f0f0f
|
||||
#define ROW11_DATA 0x07070707
|
||||
#define ROW10_DATA 0xaaaaaaaa
|
||||
|
||||
/* 0x28000000 - 0x3fffffff is used by the flash banks */
|
||||
|
||||
/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
|
||||
|
||||
/* priority numbers used for interrupt channel mappings */
|
||||
#define SC520_IRQ_DISABLED 0
|
||||
#define SC520_IRQ0 1
|
||||
#define SC520_IRQ1 2
|
||||
#define SC520_IRQ2 4 /* same as IRQ9 */
|
||||
#define SC520_IRQ3 11
|
||||
#define SC520_IRQ4 12
|
||||
#define SC520_IRQ5 13
|
||||
#define SC520_IRQ6 21
|
||||
#define SC520_IRQ7 22
|
||||
#define SC520_IRQ8 3
|
||||
#define SC520_IRQ9 4
|
||||
#define SC520_IRQ10 5
|
||||
#define SC520_IRQ11 6
|
||||
#define SC520_IRQ12 7
|
||||
#define SC520_IRQ13 8
|
||||
#define SC520_IRQ14 9
|
||||
#define SC520_IRQ15 10
|
||||
|
||||
#endif
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Graeme Russ <graeme.russ@gmail.com>.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_IC_SSI_H_
|
||||
#define _ASM_IC_SSI_H_ 1
|
||||
|
||||
int ssi_set_interface(int, int, int, int);
|
||||
void ssi_chip_select(int);
|
||||
u8 ssi_txrx_byte(u8);
|
||||
void ssi_tx_byte(u8);
|
||||
u8 ssi_rx_byte(void);
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue