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imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation 

The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Ye Li 2016-01-26 22:01:58 +08:00 committed by Stefano Babic
parent 9655ebdd50
commit 23e2da27d3
1 changed files with 0 additions and 4 deletions
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4
arch/arm/cpu/armv7/mx6/clock.c
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@ -638,10 +638,6 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
}
temp = freq * max_pred * max_postd;
if (temp > max) {
puts("Please decrease freq, too large!\n");
return;
}
if (temp < min) {
/*
* Register: PLL_VIDEO