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mx5: Fix clock gate values 

The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-09-27 10:21:22 +00:00 committed by Tom Rini
parent 1f5e4ee0b9
commit 248cdf0b52
2 changed files with 18 additions and 12 deletions
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27
arch/arm/cpu/armv7/mx5/clock.c
View File

@ -101,10 +101,11 @@ void set_usboh3_clk(void)
void enable_usboh3_clk(unsigned char enable)
{
if (enable)
setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
else
clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
clrsetbits_le32(&mxc_ccm->CCGR2,
MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
MXC_CCM_CCGR2_USBOH3_60M(cg));
}
#ifdef CONFIG_I2C_MXC
@ -132,10 +133,11 @@ void set_usb_phy1_clk(void)
void enable_usb_phy1_clk(unsigned char enable)
{
if (enable)
setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
else
clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
clrsetbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
MXC_CCM_CCGR4_USB_PHY1(cg));
}
void set_usb_phy2_clk(void)
@ -145,10 +147,11 @@ void set_usb_phy2_clk(void)
void enable_usb_phy2_clk(unsigned char enable)
{
if (enable)
setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
else
clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
clrsetbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
MXC_CCM_CCGR4_USB_PHY2(cg));
}
/*

3
arch/arm/include/asm/arch-mx5/crm_regs.h
View File

@ -285,6 +285,9 @@ struct mxc_ccm_reg {
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR_CG_OFF 0x0
#define MXC_CCM_CCGR_CG_RUN_ON 0x1
#define MXC_CCM_CCGR_CG_ON 0x3
#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0
#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0)