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ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST 

This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test.
When cache is enabled in the SDRAM area, the values written to SDRAM
need to be flushed from cache to SDRAM using the dcfb instruction.

Without this patch the POST ECC test failed. Now its working again on
platforms with cache enabled in SDRAM.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-11-26 15:45:22 +01:00
parent 844f07d8a1
commit 28e94bb2f7
1 changed files with 4 additions and 0 deletions
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4
post/cpu/ppc4xx/denali_ecc.c
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@ -174,6 +174,7 @@ static int test_ecc(uint32_t ecc_addr)
clear_and_enable_ecc();
out_be32(ecc_mem, ECC_PATTERN);
out_be32(ecc_mem + 1, ECC_PATTERN);
ppcDcbf((u32)ecc_mem);
/* Verify no ECC error reading back */
value = in_be32(ecc_mem);
@ -193,6 +194,7 @@ static int test_ecc(uint32_t ecc_addr)
/* Test for correctable error by creating a one-bit error */
out_be32(ecc_mem, ECC_PATTERN_CORR);
ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
@ -212,6 +214,7 @@ static int test_ecc(uint32_t ecc_addr)
/* Test for uncorrectable error by creating a two-bit error */
out_be32(ecc_mem, ECC_PATTERN_UNCORR);
ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
@ -232,6 +235,7 @@ static int test_ecc(uint32_t ecc_addr)
/* Remove error from SDRAM and enable ECC. */
out_be32(ecc_mem, ECC_PATTERN);
ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
return ret;