mx28evk: Add initial support for MX28EVK board
Add initial support for Freescale MX28EVK board. Tested boot via SD card and by loading a kernel via TFTP through the FEC interface. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Fabio Estevam
Albert ARIBAUD
parent
5bcc6a8901
commit
29f75a5ce5
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@ -642,6 +642,7 @@ Kristoffer Ericson <kristoffer.ericson@gmail.com>
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Fabio Estevam <fabio.estevam@freescale.com>
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mx25pdk i.MX25
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mx28evk i.MX28
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mx31pdk i.MX31
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mx53ard i.MX53
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mx53smd i.MX53
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@ -0,0 +1,49 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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ifndef CONFIG_SPL_BUILD
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COBJS := mx28evk.o
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else
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COBJS := iomux.o
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endif
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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all: $(ALL)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,138 @@
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/*
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* Freescale MX28EVK IOMUX setup
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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const iomux_cfg_t iomux_setup[] = {
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/* DUART */
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MX28_PAD_PWM0__DUART_RX,
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MX28_PAD_PWM1__DUART_TX,
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/* MMC0 */
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MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
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(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SSP0_SCK__SSP0_SCK |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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/* write protect */
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MX28_PAD_SSP1_SCK__GPIO_2_12,
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/* MMC0 slot power enable */
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MX28_PAD_PWM3__GPIO_3_28 |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
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/* FEC0 */
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MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
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/* FEC0 Enable */
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MX28_PAD_SSP1_DATA3__GPIO_2_15 |
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(MXS_PAD_12MA | MXS_PAD_3V3),
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/* FEC0 Reset */
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
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/* FEC1 */
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MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
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/* EMI */
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MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
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};
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void board_init_ll(void)
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{
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mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
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}
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@ -0,0 +1,169 @@
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/*
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* Freescale MX28EVK board
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*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Based on m28evk.c:
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
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return 0;
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}
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int dram_init(void)
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{
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return mx28_dram_init();
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_CMD_MMC
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static int mx28evk_mmc_wp(int id)
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{
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if (id != 0) {
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printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
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return 1;
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}
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return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
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}
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int board_mmc_init(bd_t *bis)
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{
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/* Configure WP as input */
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gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
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/* Configure MMC0 Power Enable */
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gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
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return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp);
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}
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#endif
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#ifdef CONFIG_CMD_NET
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#define MII_OPMODE_STRAP_OVERRIDE 0x16
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#define MII_PHY_CTRL1 0x1e
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#define MII_PHY_CTRL2 0x1f
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int fecmxc_mii_postcall(int phy)
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{
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miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
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miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
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if (phy == 3)
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miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
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writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
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&clkctrl_regs->hw_clkctrl_enet);
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/* Power-on FECs */
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gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
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/* Reset FEC PHYs */
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gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
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udelay(200);
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gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC1\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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puts("FEC MXS: Unable to register FEC0 mii postcall\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC1");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC1 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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puts("FEC MXS: Unable to register FEC1 mii postcall\n");
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return ret;
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}
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return ret;
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}
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#endif
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@ -0,0 +1,14 @@
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sources {
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u_boot_spl="spl/u-boot-spl.bin";
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u_boot="u-boot.bin";
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}
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section (0) {
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load u_boot_spl > 0x0000;
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load ivt (entry = 0x0014) > 0x8000;
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hab call 0x8000;
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load u_boot > 0x40000100;
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load ivt (entry = 0x40000100) > 0x8000;
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hab call 0x8000;
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}
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@ -160,6 +160,7 @@ zmx25 arm arm926ejs zmx25 syteco
|
|||
imx27lite arm arm926ejs imx27lite logicpd mx27
|
||||
magnesium arm arm926ejs imx27lite logicpd mx27
|
||||
m28evk arm arm926ejs - denx mx28
|
||||
mx28evk arm arm926ejs - freescale mx28
|
||||
nhk8815 arm arm926ejs nhk8815 st nomadik
|
||||
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
|
||||
omap1610h2 arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT
|
||||
|
|
|
|||
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* Based on m28evk.h:
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/regs-base.h>
|
||||
|
||||
/*
|
||||
* SoC configurations
|
||||
*/
|
||||
#define CONFIG_MX28 /* i.MX28 SoC */
|
||||
#define CONFIG_MXS_GPIO /* GPIO control */
|
||||
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
/*
|
||||
* SPL
|
||||
*/
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
|
||||
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
|
||||
/*
|
||||
* U-Boot Commands
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
/*
|
||||
* Memory configurations
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x40000000 /* Base address */
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
|
||||
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
/* Point initial SP in SRAM so SPL can use it too. */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/*
|
||||
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
|
||||
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
|
||||
* binary. In case there was more of this mess, 0x100 bytes are skipped.
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000100
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
/*
|
||||
* U-Boot general configurations
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > "
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
/* Print buffer size */
|
||||
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/* Boot argument buffer size */
|
||||
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
|
||||
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command history etc */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* Serial Driver
|
||||
*/
|
||||
#define CONFIG_PL011_SERIAL
|
||||
#define CONFIG_PL011_CLOCK 24000000
|
||||
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
|
||||
#define CONFIG_CONS_INDEX 0
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* MMC Driver
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_ENV_OFFSET (256 * 1024)
|
||||
#define CONFIG_ENV_SIZE (16 * 1024)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MXS_MMC
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Ethernet on SOC (FEC)
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_MXC_MULTI
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_MX28_FEC_MAC_IN_OCOTP
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot Linux
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_BOOTCOMMAND "run bootcmd_net"
|
||||
#define CONFIG_LOADADDR 0x42000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/*
|
||||
* Extra Environments
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console_fsl=console=ttyAM0" \
|
||||
"console_mainline=console=ttyAMA0" \
|
||||
"netargs=setenv bootargs console=${console_mainline}" \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \
|
||||
"bootcmd_net=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"dhcp ${uimage}; bootm\0" \
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue