ARM: Fix for wrong patch version applied for Lyrtech SFF-SDR board (ARM926EJS)
ARM: Fix for incorrect version of patch applied when adding support for the Lyrtech SFF-SDR board. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> Signed-off-by: Philip Balister, OpenSDR <philip@opensdr.com>
This commit is contained in:
Hugo Villeneuve
Wolfgang Denk
parent
47042b363e
commit
2b1fa9d383
5
CREDITS
5
CREDITS
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@ -537,3 +537,8 @@ N: Timo Tuunainen
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E: timo.tuunainen@sysart.fi
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D: Support for Artila M-501 starter kit
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W: http://www.sysart.fi/
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N: Philip Balister
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E: philip@opensdr.com
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D: Port to Lyrtech SFFSDR development board.
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W: www.opensdr.com
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@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := dv_board.o
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COBJS := $(BOARD).o
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SOBJS := board_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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@ -3,8 +3,10 @@
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
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#
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# Lyrtech SFF SDR board (ARM926EJS) cpu
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# see http://www.lyrtech.com/ for more information on Lyrtech
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#
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# SFF SDR board has 1 bank of 128 MB DDR RAM
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# Physical Address:
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@ -16,9 +18,6 @@
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# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
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# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
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#
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# we load ourself to 8400'0000
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#
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#
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# Provide at least 32MB spacing between us and the Integrity kernel image
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# we load ourself to 8400'0000 to provide at least 32MB spacing
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# between us and the Integrity kernel image
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TEXT_BASE = 0x84000000
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@ -1,212 +0,0 @@
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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* -----------------------------------------------------------------
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emac_defs.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void timer_init(void);
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extern int eth_hw_init(void);
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extern phy_t phy;
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/* Works on Always On power domain only (no PD argument) */
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void lpsc_on(unsigned int id)
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{
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dv_reg_p mdstat, mdctl;
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if (id >= DAVINCI_LPSC_GEM)
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return; /* Don't work on DSP Power Domain */
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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while (REG(PSC_PTSTAT) & 0x01);
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if ((*mdstat & 0x1f) == 0x03)
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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/* Special treatment for some modules as for sprue14 p.7.4.2 */
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if ((id == DAVINCI_LPSC_VPSSSLV) ||
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(id == DAVINCI_LPSC_EMAC) ||
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(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
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(id == DAVINCI_LPSC_MDIO) ||
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(id == DAVINCI_LPSC_USB) ||
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(id == DAVINCI_LPSC_ATA) ||
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(id == DAVINCI_LPSC_VLYNQ) ||
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(id == DAVINCI_LPSC_UHPI) ||
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(id == DAVINCI_LPSC_DDR_EMIF) ||
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(id == DAVINCI_LPSC_AEMIF) ||
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(id == DAVINCI_LPSC_MMC_SD) ||
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(id == DAVINCI_LPSC_MEMSTICK) ||
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(id == DAVINCI_LPSC_McBSP) ||
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(id == DAVINCI_LPSC_GPIO))
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* mdctl |= 0x200;
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REG(PSC_PTCMD) = 0x01;
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while (REG(PSC_PTSTAT) & 0x03);
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while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */
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}
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void dsp_on(void)
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{
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int i;
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if (REG(PSC_PDSTAT1) & 0x1f)
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return; /* Already on */
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REG(PSC_GBLCTL) |= 0x01;
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REG(PSC_PDCTL1) |= 0x01;
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REG(PSC_PDCTL1) &= ~0x100;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
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REG(PSC_PTCMD) = 0x02;
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for (i = 0; i < 100; i++) {
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if (REG(PSC_EPCPR) & 0x02)
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break;
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}
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REG(PSC_CHP_SHRTSW) = 0x01;
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REG(PSC_PDCTL1) |= 0x100;
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REG(PSC_EPCCR) = 0x02;
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for (i = 0; i < 100; i++) {
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if (!(REG(PSC_PTSTAT) & 0x02))
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break;
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}
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REG(PSC_GBLCTL) &= ~0x1f;
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}
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* Workaround for TMS320DM6446 errata 1.3.22 */
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REG(PSC_SILVER_BULLET) = 0;
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_EMAC);
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lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
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lpsc_on(DAVINCI_LPSC_MDIO);
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lpsc_on(DAVINCI_LPSC_I2C);
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lpsc_on(DAVINCI_LPSC_UART0);
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lpsc_on(DAVINCI_LPSC_TIMER1);
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lpsc_on(DAVINCI_LPSC_GPIO);
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/* Powerup the DSP */
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dsp_on();
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/* Bringup UART0 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x0000e003;
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/* Enable GIO3.3V cells used for EMAC */
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REG(VDD3P3V_PWDN) = 0;
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/* Enable UART0 MUX lines */
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REG(PINMUX1) |= 1;
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/* Enable EMAC and AEMIF pins */
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REG(PINMUX0) = 0x80000c1f;
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/* Enable I2C pin Mux */
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REG(PINMUX1) |= (1 << 7);
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/* Set the Bus Priority Register to appropriate value */
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REG(VBPR) = 0x20;
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timer_init();
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return(0);
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}
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int misc_init_r(void)
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{
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u_int8_t tmp[20], buf[10];
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int i = 0;
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int clk = 0;
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clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
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printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2);
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printf("DDR Clock: %dMHz\n", (clk / 2));
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/* Configure I2C switch (PCA9543) to enable channel 0. */
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tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0;
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if (i2c_write(CFG_I2C_PCA9543_ADDR, 0,
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CFG_I2C_PCA9543_ADDR_LEN, tmp, 1))
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printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
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/* Set Ethernet MAC address from EEPROM.
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* We must read 8 bytes because data is stored in little-endian. */
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if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8,
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CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) {
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printf("Read from EEPROM @ 0x%02x failed\n",
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CFG_I2C_EEPROM_ADDR);
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} else {
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tmp[0] = 0xff;
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for (i = 0; i < 6; i++)
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tmp[0] &= buf[i];
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if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
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sprintf((char *)&tmp[0],
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"%02x:%02x:%02x:%02x:%02x:%02x",
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buf[3], buf[2], buf[1], buf[0],
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buf[7], buf[6]);
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setenv("ethaddr", (char *)&tmp[0]);
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}
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}
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if (!eth_hw_init()) {
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printf("Ethernet init failed\n");
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} else {
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printf("ETH PHY: %s\n", phy.name);
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}
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return(0);
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return(0);
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}
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@ -0,0 +1,310 @@
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
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*
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* Parts are shamelessly stolen from various TI sources, original copyright
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* follows:
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*
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* Copyright (C) 2004 Texas Instruments.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/emac_defs.h>
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#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
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#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
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#define INTEGRITY_SYSCFG_OFFSET 0x7E8
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#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
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#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
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DECLARE_GLOBAL_DATA_PTR;
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extern void timer_init(void);
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extern int eth_hw_init(void);
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extern phy_t phy;
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/* Works on Always On power domain only (no PD argument) */
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void lpsc_on(unsigned int id)
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{
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dv_reg_p mdstat, mdctl;
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if (id >= DAVINCI_LPSC_GEM)
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return; /* Don't work on DSP Power Domain */
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mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
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mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
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while (REG(PSC_PTSTAT) & 0x01);
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if ((*mdstat & 0x1f) == 0x03)
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return; /* Already on and enabled */
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*mdctl |= 0x03;
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/* Special treatment for some modules as for sprue14 p.7.4.2 */
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switch (id) {
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case DAVINCI_LPSC_VPSSSLV:
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case DAVINCI_LPSC_EMAC:
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case DAVINCI_LPSC_EMAC_WRAPPER:
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case DAVINCI_LPSC_MDIO:
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case DAVINCI_LPSC_USB:
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case DAVINCI_LPSC_ATA:
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case DAVINCI_LPSC_VLYNQ:
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case DAVINCI_LPSC_UHPI:
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case DAVINCI_LPSC_DDR_EMIF:
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case DAVINCI_LPSC_AEMIF:
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case DAVINCI_LPSC_MMC_SD:
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case DAVINCI_LPSC_MEMSTICK:
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case DAVINCI_LPSC_McBSP:
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case DAVINCI_LPSC_GPIO:
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*mdctl |= 0x200;
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break;
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}
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REG(PSC_PTCMD) = 0x01;
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while (REG(PSC_PTSTAT) & 0x03);
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while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */
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}
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#if !defined(CFG_USE_DSPLINK)
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void dsp_on(void)
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{
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int i;
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if (REG(PSC_PDSTAT1) & 0x1f)
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return; /* Already on */
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REG(PSC_GBLCTL) |= 0x01;
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REG(PSC_PDCTL1) |= 0x01;
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REG(PSC_PDCTL1) &= ~0x100;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
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REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
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REG(PSC_PTCMD) = 0x02;
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for (i = 0; i < 100; i++) {
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if (REG(PSC_EPCPR) & 0x02)
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break;
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}
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REG(PSC_CHP_SHRTSW) = 0x01;
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REG(PSC_PDCTL1) |= 0x100;
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REG(PSC_EPCCR) = 0x02;
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for (i = 0; i < 100; i++) {
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if (!(REG(PSC_PTSTAT) & 0x02))
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break;
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}
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REG(PSC_GBLCTL) &= ~0x1f;
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}
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#endif /* CFG_USE_DSPLINK */
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int board_init(void)
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{
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/* arch number of the board */
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gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* Workaround for TMS320DM6446 errata 1.3.22 */
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REG(PSC_SILVER_BULLET) = 0;
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/* Power on required peripherals */
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lpsc_on(DAVINCI_LPSC_EMAC);
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lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
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lpsc_on(DAVINCI_LPSC_MDIO);
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lpsc_on(DAVINCI_LPSC_I2C);
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lpsc_on(DAVINCI_LPSC_UART0);
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lpsc_on(DAVINCI_LPSC_TIMER1);
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lpsc_on(DAVINCI_LPSC_GPIO);
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#if !defined(CFG_USE_DSPLINK)
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/* Powerup the DSP */
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dsp_on();
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#endif /* CFG_USE_DSPLINK */
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/* Bringup UART0 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x0000e003;
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/* Enable GIO3.3V cells used for EMAC */
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REG(VDD3P3V_PWDN) = 0;
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/* Enable UART0 MUX lines */
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REG(PINMUX1) |= 1;
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/* Enable EMAC and AEMIF pins */
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REG(PINMUX0) = 0x80000c1f;
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/* Enable I2C pin Mux */
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REG(PINMUX1) |= (1 << 7);
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/* Set the Bus Priority Register to appropriate value */
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REG(VBPR) = 0x20;
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timer_init();
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return(0);
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}
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/* Read ethernet MAC address from Integrity data structure inside EEPROM. */
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int read_mac_address(uint8_t *buf)
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{
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u_int32_t value, mac[2], address;
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/* Read Integrity data structure checkword. */
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if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
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CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
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goto err;
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if (value != INTEGRITY_CHECKWORD_VALUE)
|
||||
return 1;
|
||||
|
||||
/* Read SYSCFG structure offset. */
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
|
||||
CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
|
||||
goto err;
|
||||
address = 0x800 + (int) value; /* Address of SYSCFG structure. */
|
||||
|
||||
/* Read NET CONFIG structure offset. */
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
|
||||
CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
|
||||
goto err;
|
||||
address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
|
||||
address += 12; /* Address of NET INTERFACE CONFIG structure. */
|
||||
|
||||
/* Read NET INTERFACE CONFIG 2 structure offset. */
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
|
||||
CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
|
||||
goto err;
|
||||
address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
|
||||
* CONFIG 2 structure. */
|
||||
|
||||
/* Read MAC address. */
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
|
||||
CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
|
||||
goto err;
|
||||
|
||||
buf[0] = mac[0] >> 24;
|
||||
buf[1] = mac[0] >> 16;
|
||||
buf[2] = mac[0] >> 8;
|
||||
buf[3] = mac[0];
|
||||
buf[4] = mac[1] >> 24;
|
||||
buf[5] = mac[1] >> 16;
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Platform dependent initialisation. */
|
||||
int misc_init_r(void)
|
||||
{
|
||||
int i;
|
||||
u_int8_t i2cbuf;
|
||||
u_int8_t env_enetaddr[6], eeprom_enetaddr[6];
|
||||
char *tmp = getenv("ethaddr");
|
||||
char *end;
|
||||
int clk;
|
||||
|
||||
/* EMIF-A CS3 configuration for FPGA. */
|
||||
REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
|
||||
|
||||
clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
|
||||
|
||||
printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2);
|
||||
printf("DDR Clock: %dMHz\n", (clk / 2));
|
||||
|
||||
/* Configure I2C switch (PCA9543) to enable channel 0. */
|
||||
i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0;
|
||||
if (i2c_write(CFG_I2C_PCA9543_ADDR, 0,
|
||||
CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
|
||||
printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Read Ethernet MAC address from the U-Boot environment. */
|
||||
for (i = 0; i < 6; i++) {
|
||||
env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
|
||||
if (tmp)
|
||||
tmp = (*end) ? end+1 : end;
|
||||
}
|
||||
|
||||
/* Read Ethernet MAC address from EEPROM. */
|
||||
if (read_mac_address(eeprom_enetaddr) == 0) {
|
||||
if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
|
||||
memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) {
|
||||
printf("\nWarning: MAC addresses don't match:\n");
|
||||
printf("\tHW MAC address: "
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X\n",
|
||||
eeprom_enetaddr[0], eeprom_enetaddr[1],
|
||||
eeprom_enetaddr[2], eeprom_enetaddr[3],
|
||||
eeprom_enetaddr[4], eeprom_enetaddr[5]);
|
||||
printf("\t\"ethaddr\" value: "
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X\n",
|
||||
env_enetaddr[0], env_enetaddr[1],
|
||||
env_enetaddr[2], env_enetaddr[3],
|
||||
env_enetaddr[4], env_enetaddr[5]) ;
|
||||
debug("### Set MAC addr from environment\n");
|
||||
memcpy(eeprom_enetaddr, env_enetaddr, 6);
|
||||
}
|
||||
if (!tmp) {
|
||||
char ethaddr[20];
|
||||
|
||||
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
eeprom_enetaddr[0], eeprom_enetaddr[1],
|
||||
eeprom_enetaddr[2], eeprom_enetaddr[3],
|
||||
eeprom_enetaddr[4], eeprom_enetaddr[5]) ;
|
||||
debug("### Set environment from HW MAC addr = \"%s\"\n",
|
||||
ethaddr);
|
||||
setenv("ethaddr", ethaddr);
|
||||
}
|
||||
}
|
||||
|
||||
if (!eth_hw_init()) {
|
||||
printf("Ethernet init failed\n");
|
||||
} else {
|
||||
printf("ETH PHY: %s\n", phy.name);
|
||||
}
|
||||
|
||||
/* On this platform, U-Boot is copied in RAM by the UBL,
|
||||
* so we are always in the relocated state. */
|
||||
gd->flags |= GD_FLG_RELOC;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
|
@ -1,6 +1,9 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
|
||||
* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
|
|
@ -21,30 +24,24 @@
|
|||
#define __CONFIG_H
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/*=======*/
|
||||
/* Board */
|
||||
/*=======*/
|
||||
#define SFFSDR
|
||||
#define CFG_NAND_LARGEPAGE
|
||||
#define CFG_USE_NAND
|
||||
/*===================*/
|
||||
#define CFG_USE_DSPLINK /* This is to prevent U-Boot from
|
||||
* powering ON the DSP. */
|
||||
/* SoC Configuration */
|
||||
/*===================*/
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
|
||||
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
|
||||
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
|
||||
#define CFG_HZ 1000
|
||||
/*==================================================*/
|
||||
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
|
||||
/*==================================================*/
|
||||
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
/*=============*/
|
||||
/* Memory Info */
|
||||
/*=============*/
|
||||
#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
|
||||
#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
|
||||
|
|
@ -54,9 +51,7 @@
|
|||
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
|
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
|
||||
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
|
||||
/*====================*/
|
||||
/* Serial Driver info */
|
||||
/*====================*/
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
|
||||
|
|
@ -65,16 +60,12 @@
|
|||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
/*===================*/
|
||||
/* I2C Configuration */
|
||||
/*===================*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_DRIVER_DAVINCI_I2C
|
||||
#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
|
||||
#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
|
||||
/*==================================*/
|
||||
/* Network & Ethernet Configuration */
|
||||
/*==================================*/
|
||||
#define CONFIG_DRIVER_TI_EMAC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
|
|
@ -83,9 +74,7 @@
|
|||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
/*=====================*/
|
||||
/* Flash & Environment */
|
||||
/*=====================*/
|
||||
#undef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_NO_FLASH
|
||||
#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
|
||||
|
|
@ -98,28 +87,19 @@
|
|||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
|
||||
/*=====================*/
|
||||
/* Board related stuff */
|
||||
/*=====================*/
|
||||
/*==========================================*/
|
||||
/* I2C switch definitions for PCA9543 chip */
|
||||
/* on Lyrtech SFF SDR board. */
|
||||
/* This chip has a single register. */
|
||||
/*==========================================*/
|
||||
/* I2C switch definitions for PCA9543 chip */
|
||||
#define CFG_I2C_PCA9543_ADDR 0x70
|
||||
#define CFG_I2C_PCA9543_ADDR_LEN 0
|
||||
#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
|
||||
#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
|
||||
/*==============================*/
|
||||
/* U-Boot general configuration */
|
||||
/*==============================*/
|
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
|
||||
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#undef CONFIG_BOOTDELAY
|
||||
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
/* Print buffer size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_PBSIZE \
|
||||
(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel
|
||||
|
|
@ -133,25 +113,20 @@
|
|||
#define CFG_LONGHELP
|
||||
#define CONFIG_CRC32_VERIFY
|
||||
#define CONFIG_MX_CYCLIC
|
||||
/*
|
||||
* Define this to load an Integrity kernel.
|
||||
*
|
||||
#define CONFIG_CMD_ELF
|
||||
*/
|
||||
|
||||
/*===================*/
|
||||
/* Linux Information */
|
||||
/*===================*/
|
||||
#define LINUX_BOOT_PARAM_ADDR 0x80000100
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_BOOTARGS \
|
||||
"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
|
||||
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
|
||||
|
||||
/*=================*/
|
||||
#define CONFIG_BOOTARGS \
|
||||
"mem=56M " \
|
||||
"console=ttyS0,115200n8 " \
|
||||
"root=/dev/nfs rw noinitrd ip=dhcp " \
|
||||
"nfsroot=${serverip}:/nfsroot/sffsdr " \
|
||||
"eth0=${ethaddr}"
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"nand read 87A00000 100000 300000;" \
|
||||
"bootelf 87A00000"
|
||||
/* U-Boot commands */
|
||||
/*=================*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
|
@ -167,9 +142,7 @@
|
|||
#undef CONFIG_CMD_SETGETDCR
|
||||
#undef CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
/*=======================*/
|
||||
/* KGDB support (if any) */
|
||||
/*=======================*/
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
|
||||
|
|
|
|||
Loading…
Reference in New Issue