integratorap: split timer support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Peter Pearse <peter.pearse@arm.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
parent
86baa085c5
commit
2bcef0723e
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@ -34,6 +34,7 @@ SOBJS-y := lowlevel_init.o
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COBJS-y := integratorap.o
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COBJS-y += flash.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-y += timer.o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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COBJS := $(addprefix $(obj),$(COBJS-y))
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@ -149,141 +149,6 @@ extern void dram_query(void);
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return 0;
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}
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/* The Integrator/AP timer1 is clocked at 24MHz
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* can be divided by 16 or 256
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* and is a 16-bit counter
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*/
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/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
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static ulong timestamp; /* U-Boot ticks since startup */
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static ulong total_count = 0; /* Total timer count */
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static ulong lastdec; /* Timer reading at last call */
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static ulong div_clock = 256; /* Divisor applied to the timer clock */
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static ulong div_timer = 1; /* Divisor to convert timer reading
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* change to U-Boot ticks
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*/
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/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
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#define TIMER_LOAD_VAL 0x0000FFFFL
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#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
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/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
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* - unless otherwise stated
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*/
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/* starts a counter
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* - the Integrator/AP timer issues an interrupt
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* each time it reaches zero
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*/
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int timer_init (void)
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{
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/* Load timer with initial value */
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
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/* Set timer to be
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* enabled 1
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* free-running 0
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* XX 00
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* divider 256 10
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* XX 00
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*/
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
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total_count = 0;
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/* init the timestamp and lastdec value */
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reset_timer_masked();
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div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
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div_timer /= div_clock;
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return (0);
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}
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/*
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* timer without interrupts
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*/
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void reset_timer (void)
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{
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reset_timer_masked ();
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}
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ulong get_timer (ulong base_ticks)
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{
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return get_timer_masked () - base_ticks;
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}
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void set_timer (ulong ticks)
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{
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timestamp = ticks;
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total_count = ticks * div_timer;
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reset_timer_masked();
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}
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/* delay x useconds */
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void udelay (unsigned long usec)
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{
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ulong tmo, tmp;
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/* Convert to U-Boot ticks */
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000000L);
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tmp = get_timer_masked(); /* get current timestamp */
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tmo += tmp; /* wake up timestamp */
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while (get_timer_masked () < tmo) { /* loop till event */
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/*NOP*/;
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}
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}
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void reset_timer_masked (void)
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{
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/* reset time */
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lastdec = READ_TIMER; /* capture current decrementer value */
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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/* converts the timer reading to U-Boot ticks */
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/* the timestamp is the number of ticks since reset */
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/* This routine does not detect wraps unless called regularly
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ASSUMES a call at least every 16 seconds to detect every reload */
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ulong get_timer_masked (void)
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{
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ulong now = READ_TIMER; /* current count */
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if (now > lastdec) {
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/* Must have wrapped */
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total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
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} else {
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total_count += lastdec - now;
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}
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lastdec = now;
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timestamp = total_count/div_timer;
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return timestamp;
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}
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/* waits specified delay value and resets timestamp */
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void udelay_masked (unsigned long usec)
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{
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udelay(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* Return the timebase clock frequency
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* i.e. how often the timer decrements
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*/
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ulong get_tbclk (void)
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{
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return CONFIG_SYS_HZ_CLOCK/div_clock;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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@ -0,0 +1,171 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* The Integrator/AP timer1 is clocked at 24MHz
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* can be divided by 16 or 256
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* and is a 16-bit counter
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*/
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/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
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static ulong timestamp; /* U-Boot ticks since startup */
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static ulong total_count = 0; /* Total timer count */
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static ulong lastdec; /* Timer reading at last call */
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static ulong div_clock = 256; /* Divisor applied to the timer clock */
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static ulong div_timer = 1; /* Divisor to convert timer reading
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* change to U-Boot ticks
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*/
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/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
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#define TIMER_LOAD_VAL 0x0000FFFFL
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#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
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/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
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* - unless otherwise stated
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*/
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/* starts a counter
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* - the Integrator/AP timer issues an interrupt
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* each time it reaches zero
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*/
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int timer_init (void)
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{
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/* Load timer with initial value */
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
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/* Set timer to be
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* enabled 1
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* free-running 0
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* XX 00
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* divider 256 10
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* XX 00
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*/
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
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total_count = 0;
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/* init the timestamp and lastdec value */
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reset_timer_masked();
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div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
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div_timer /= div_clock;
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return (0);
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}
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/*
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* timer without interrupts
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*/
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void reset_timer (void)
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{
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reset_timer_masked ();
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}
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ulong get_timer (ulong base_ticks)
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{
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return get_timer_masked () - base_ticks;
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}
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void set_timer (ulong ticks)
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{
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timestamp = ticks;
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total_count = ticks * div_timer;
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reset_timer_masked();
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}
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/* delay x useconds */
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void udelay (unsigned long usec)
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{
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ulong tmo, tmp;
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/* Convert to U-Boot ticks */
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000000L);
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tmp = get_timer_masked(); /* get current timestamp */
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tmo += tmp; /* wake up timestamp */
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while (get_timer_masked () < tmo) { /* loop till event */
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/*NOP*/;
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}
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}
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void reset_timer_masked (void)
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{
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/* reset time */
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lastdec = READ_TIMER; /* capture current decrementer value */
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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/* converts the timer reading to U-Boot ticks */
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/* the timestamp is the number of ticks since reset */
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/* This routine does not detect wraps unless called regularly
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ASSUMES a call at least every 16 seconds to detect every reload */
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ulong get_timer_masked (void)
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{
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ulong now = READ_TIMER; /* current count */
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if (now > lastdec) {
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/* Must have wrapped */
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total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
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} else {
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total_count += lastdec - now;
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}
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lastdec = now;
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timestamp = total_count/div_timer;
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return timestamp;
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}
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/* waits specified delay value and resets timestamp */
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void udelay_masked (unsigned long usec)
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{
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udelay(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* Return the timebase clock frequency
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* i.e. how often the timer decrements
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*/
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ulong get_tbclk (void)
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{
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return CONFIG_SYS_HZ_CLOCK/div_clock;
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}
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