dreamplug: initial board support.
Copied wholeheartedly from board/Marvell/guruplug and modified to add support for SPI NOR flash. CONFIG_MACH_DREAMPLUG defined in include/configs/dreamplug.h until Linus's kernel.org tree adds it to mach-types.h. Once it trickles down, the definition can be removed from include/configs/dreamplug.h. Signed-off-by: Jason Cooper <u-boot@lakedaemon.net>
This commit is contained in:
Jason Cooper
Albert ARIBAUD
parent
77f11a99e1
commit
2e0c1c7d5c
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@ -70,6 +70,10 @@ Conn Clark <clark@esteem.com>
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ESTEEM192E MPC8xx
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Jason Cooper <u-boot@lakedaemon.net>
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dreamplug ARM926EJS (Kirkwood SoC)
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Joe D'Abbraccio <ljd015@freescale.com>
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MPC837xERDB MPC837x
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@ -0,0 +1,54 @@
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#
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# (C) Copyright 2011
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# Jason Cooper <u-boot@lakedaemon.net>
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#
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# Based on work by:
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Siddarth Gore <gores@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := dreamplug.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,151 @@
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/*
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "dreamplug.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
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DREAMPLUG_OE_VAL_HIGH,
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DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_SPI_SCn, /* SPI Flash */
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD, /* Serial */
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MPP11_UART0_RXD,
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MPP12_SD_CLK, /* SDIO Slot */
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GE1_0, /* Gigabit Ethernet */
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MPP21_GE1_1,
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MPP22_GE1_2,
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MPP23_GE1_3,
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MPP24_GE1_4,
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MPP25_GE1_5,
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MPP26_GE1_6,
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MPP27_GE1_7,
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MPP28_GE1_8,
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MPP29_GE1_9,
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MPP30_GE1_10,
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MPP31_GE1_11,
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MPP32_GE1_12,
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MPP33_GE1_13,
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MPP34_GE1_14,
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MPP35_GE1_15,
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MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_TDM_SPI_SCK,
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MPP41_TDM_SPI_MISO,
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MPP42_TDM_SPI_MOSI,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO, /* Bluetooth LED */
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MPP48_GPIO, /* Wifi LED */
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MPP49_GPIO, /* Wifi AP LED */
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void mv_phy_88e1116_init(char *name)
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{
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u16 reg;
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u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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void reset_phy(void)
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{
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/* configure and initialize both PHY's */
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mv_phy_88e1116_init("egiga0");
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mv_phy_88e1116_init("egiga1");
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}
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#endif /* CONFIG_RESET_PHY_R */
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@ -0,0 +1,42 @@
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/*
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __DREAMPLUG_H
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#define __DREAMPLUG_H
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#define DREAMPLUG_OE_LOW (~(0))
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#define DREAMPLUG_OE_HIGH (~(0))
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#define DREAMPLUG_OE_VAL_LOW 0
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#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
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/* PHY related */
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#define MV88E1116_MAC_CTRL2_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __DREAMPLUG_H */
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@ -0,0 +1,163 @@
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#
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# (C) Copyright 2011
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# Jason Cooper <u-boot@lakedaemon.net>
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#
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# Based on work by:
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Siddarth Gore <gores@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0/1 interface pad voltage to 1.8V
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DATA 0xFFD100e0 0x1b1b9b9b
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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# bit3-0: TRAS lsbs
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: zero required
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DATA 0xFFD01410 0x000000cc # DDR Address Control
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# bit1-0: 01, Cs0width=x8
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# bit3-2: 10, Cs0size=1Gb
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# bit5-4: 01, Cs1width=x8
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# bit7-6: 10, Cs1size=1Gb
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# bit9-8: 00, Cs2width=nonexistent
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# bit11-10: 00, Cs2size =nonexistent
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# bit13-12: 00, Cs3width=nonexistent
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# bit15-14: 00, Cs3size =nonexistent
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0 required
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0 required
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DATA 0xFFD01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0 required
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DATA 0xFFD0141C 0x00000C52 # DDR Mode
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# bit2-0: 2, BurstLen=2 required
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# bit3: 0, BurstType=0 required
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# bit6-4: 4, CL=5
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# bit7: 0, TestMode=0 normal
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# bit8: 0, DLL reset=0 normal
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# bit11-9: 6, auto-precharge write recovery ????????????
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# bit12: 0, PD must be zero
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# bit31-13: 0 required
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DATA 0xFFD01420 0x00000040 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 0, DDR drive strenght normal
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# bit2: 0, DDR ODT control lsd (disabled)
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# bit5-3: 000, required
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# bit6: 1, DDR ODT control msb, (disabled)
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# bit9-7: 000, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0 required
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
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# bit2-0: 111, required
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# bit3 : 1 , MBUS Burst Chop disabled
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# bit6-4: 111, required
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# bit7 : 0
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# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
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# bit9 : 0 , no half clock cycle addition to dataout
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 1111 required
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# bit31-16: 0 required
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DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
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DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
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# bit0: 1, Window enabled
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# bit1: 0, Write Protect disabled
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# bit3-2: 00, CS0 hit selected
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# bit23-4: ones, required
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# bit31-24: 0x0F, Size (i.e. 256MB)
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DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
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DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
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DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
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# bit3-2: 01, ODT1 active NEVER!
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# bit31-4: zero, required
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DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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#bit0=1, enable DDR init upon this register write
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# End of Header extension
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DATA 0x0 0x0
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@ -138,6 +138,7 @@ portl2 arm arm926ejs km_arm keymile
|
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inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:INETSPACE_V2
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netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_V2
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netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_MAX_V2
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dreamplug arm arm926ejs - Marvell kirkwood
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guruplug arm arm926ejs - Marvell kirkwood
|
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mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
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openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
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|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Jason Cooper <u-boot@lakedaemon.net>
|
||||
*
|
||||
* Based on work by:
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Siddarth Gore <gores@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_DREAMPLUG_H
|
||||
#define _CONFIG_DREAMPLUG_H
|
||||
|
||||
/*
|
||||
* FIXME: This belongs in mach-types.h. However, we only pull mach-types
|
||||
* from Linus' kernel.org tree. This hasn't been updated primarily due to
|
||||
* the recent arch/arm reshuffling. So, in the meantime, we'll place it
|
||||
* here.
|
||||
*/
|
||||
#include <asm/mach-types.h>
|
||||
#ifdef MACH_TYPE_DREAMPLUG
|
||||
#error "MACH_TYPE_DREAMPLUG has been defined properly, please remove this."
|
||||
#else
|
||||
#define MACH_TYPE_DREAMPLUG 3550
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Version number information
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING "\nMarvell-DreamPlug"
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 1 /* SOC Name */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH 1
|
||||
#define CONFIG_HARD_SPI 1
|
||||
#define CONFIG_KIRKWOOD_SPI 1
|
||||
#define CONFIG_SPI_FLASH_MACRONIX 1
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* max 4k env size is enough, but in case of nand
|
||||
* it has to be rounded to sector size
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* 4k */
|
||||
#define CONFIG_ENV_ADDR 0x100000
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* env starts here */
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
|
||||
"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
|
||||
"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
|
||||
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
|
||||
"bootm 0x6400000;"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"x_bootcmd_ethernet=ping 192.168.2.1\0" \
|
||||
"x_bootcmd_usb=usb start\0" \
|
||||
"x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
|
||||
"x_bootargs=console=ttyS0,115200\0" \
|
||||
"x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* SATA Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_MVSATA_IDE
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
|
||||
#endif /*CONFIG_MVSATA_IDE*/
|
||||
|
||||
/*
|
||||
* RTC driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_MV
|
||||
#endif /* CONFIG_CMD_DATE */
|
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
/*
|
||||
* display enhanced info about the cpu at boot.
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
#endif /* _CONFIG_DREAMPLUG_H */
|
||||
Loading…
Reference in New Issue