From 32c1294d62c134137d4a65b6e9101b1172b60789 Mon Sep 17 00:00:00 2001 From: Holger Hans Peter Freyther Date: Sun, 12 Jun 2016 21:33:56 +0200 Subject: [PATCH] sysmobtsv1/sysmobtsv2: Do not re-configure the AEMIF NAND timings We select CONFIG_SOC_DM644X but we don't want A1CR to be changed. Our UBL sets the A1CR depending on the actual flash chip and the u-boot should not replicate it! Found by Harald and me while debugging a RAUC issue with the barebox bootloader. --- drivers/mtd/nand/davinci_nand.c | 34 +-------------------------------- 1 file changed, 1 insertion(+), 33 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index e8506ddd9b..3d369d13ad 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -568,39 +568,7 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) static void nand_flash_init(void) { - /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! - * Instead, have your board_init() set EMIF timings, based on its - * knowledge of the clocks and what devices are hooked up ... and - * don't even do that unless no UBL handled it. - */ -#ifdef CONFIG_SOC_DM644X - u_int32_t acfg1 = 0x3ffffffc; - - /*------------------------------------------------------------------* - * NAND FLASH CHIP TIMEOUT @ 459 MHz * - * * - * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * - * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * - * * - *------------------------------------------------------------------*/ - acfg1 = 0 - | (0 << 31) /* selectStrobe */ - | (0 << 30) /* extWait */ - | (1 << 26) /* writeSetup 10 ns */ - | (3 << 20) /* writeStrobe 40 ns */ - | (1 << 17) /* writeHold 10 ns */ - | (1 << 13) /* readSetup 10 ns */ - | (5 << 7) /* readStrobe 60 ns */ - | (1 << 4) /* readHold 10 ns */ - | (3 << 2) /* turnAround ?? ns */ - | (0 << 0) /* asyncSize 8-bit bus */ - ; - - __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */ - - /* NAND flash on CS2 */ - __raw_writel(0x00000101, &davinci_emif_regs->nandfcr); -#endif + /* Have your UBL set these timings based on the actual NAND */ } void davinci_nand_init(struct nand_chip *nand)