ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124
This provides SPL support for Tegra124 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Tom Warren
Tom Warren
parent
999c6baf79
commit
32edd2ede2
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@ -112,8 +112,40 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
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{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
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{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
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},
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/*
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* T124: 700 MHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 23:20 4
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* PLLX_BASE n 15: 8 8
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* PLLX_BASE m 7: 0 8
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*/
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{
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{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
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{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
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{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
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{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
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},
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};
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static inline void pllx_set_iddq(void)
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{
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#if defined(CONFIG_TEGRA124)
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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/* Disable IDDQ */
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reg = readl(&clkrst->crc_pllx_misc3);
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reg &= ~PLLX_IDDQ_MASK;
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writel(reg, &clkrst->crc_pllx_misc3);
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udelay(2);
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debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
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readl(&clkrst->crc_pllx_misc3));
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#endif
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}
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int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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u32 divp, u32 cpcon)
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{
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@ -128,6 +160,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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debug(" pllx_set_rate entry\n");
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pllx_set_iddq();
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/* Set BYPASS, m, n and p to PLLX_BASE */
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reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
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reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
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@ -323,7 +357,7 @@ void clock_enable_coresight(int enable)
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if (enable) {
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/*
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* Put CoreSight on PLLP_OUT0 and divide it down as per
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* PLLP base frequency based on SoC type (T20/T30/T114).
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* PLLP base frequency based on SoC type (T20/T30+).
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* Clock divider request would setup CSITE clock as 144MHz
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* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
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*/
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@ -13,7 +13,8 @@
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#if defined(CONFIG_TEGRA20)
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#define NVBL_PLLP_KHZ 216000
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#define CSITE_KHZ 144000
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#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
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#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
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defined(CONFIG_TEGRA124)
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#define NVBL_PLLP_KHZ 408000
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#define CSITE_KHZ 204000
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#else
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@ -70,3 +71,4 @@ int tegra_get_chip(void);
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int tegra_get_sku_info(void);
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int tegra_get_chip_sku(void);
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void adjust_pllp_out_freqs(void);
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void pmic_enable_cpu_vdd(void);
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@ -0,0 +1,8 @@
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#
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# (C) Copyright 2013-2014
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# NVIDIA Corporation <www.nvidia.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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@ -0,0 +1,7 @@
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#
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# (C) Copyright 2010-2013
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# NVIDIA Corporation <www.nvidia.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#/
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USE_PRIVATE_LIBGCC = yes
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@ -0,0 +1,265 @@
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/*
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* (C) Copyright 2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/ahb.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/ap.h>
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#include "../tegra-common/cpu.h"
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/* Tegra124-specific CPU init code */
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static void enable_cpu_power_rail(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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debug("enable_cpu_power_rail entry\n");
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/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
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pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
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pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
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pmic_enable_cpu_vdd();
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/*
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* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
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* set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
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*/
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writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
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/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
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clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
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setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
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}
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static void enable_cpu_clocks(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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debug("enable_cpu_clocks entry\n");
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/* Wait for PLL-X to lock */
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do {
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reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
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debug("%s: PLLX base = 0x%08X\n", __func__, reg);
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} while ((reg & PLL_LOCK_MASK) == 0);
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debug("%s: PLLX locked, delay for stable clocks\n", __func__);
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/* Wait until all clocks are stable */
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udelay(PLL_STABILIZATION_DELAY);
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debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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debug("%s: Enabling clock to all CPUs\n", __func__);
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/* Enable the clock to all CPUs */
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reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
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CLR_CPU0_CLK_STP;
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writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
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debug("%s: Enabling main CPU complex clocks\n", __func__);
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/* Always enable the main CPU complex clocks */
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clock_enable(PERIPH_ID_CPU);
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clock_enable(PERIPH_ID_CPULP);
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clock_enable(PERIPH_ID_CPUG);
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debug("%s: Done\n", __func__);
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}
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static void remove_cpu_resets(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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debug("remove_cpu_resets entry\n");
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/* Take the slow and fast partitions out of reset */
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reg = CLR_NONCPURESET;
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writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
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writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
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/* Clear the SW-controlled reset of the slow cluster */
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reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
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CLR_L2RESET | CLR_PRESETDBG;
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writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
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/* Clear the SW-controlled reset of the fast cluster */
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reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
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CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
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CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
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CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
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CLR_L2RESET | CLR_PRESETDBG;
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writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
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}
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/**
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* The Tegra124 requires some special clock initialization, including setting up
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* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
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*/
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void tegra124_init_clocks(void)
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{
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 val;
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debug("tegra124_init_clocks entry\n");
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/* Set active CPU cluster to G */
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clrbits_le32(&flow->cluster_control, 1);
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/* Change the oscillator drive strength */
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val = readl(&clkrst->crc_osc_ctrl);
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val &= ~OSC_XOFS_MASK;
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val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
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writel(val, &clkrst->crc_osc_ctrl);
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/* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
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val = readl(&pmc->pmc_osc_edpd_over);
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val &= ~PMC_XOFS_MASK;
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val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
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writel(val, &pmc->pmc_osc_edpd_over);
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/* Set HOLD_CKE_LOW_EN to 1 */
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setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
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debug("Setting up PLLX\n");
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init_pllx();
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val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
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writel(val, &clkrst->crc_clk_sys_rate);
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/* Enable clocks to required peripherals. TBD - minimize this list */
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debug("Enabling clocks\n");
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clock_set_enable(PERIPH_ID_CACHE2, 1);
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clock_set_enable(PERIPH_ID_GPIO, 1);
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clock_set_enable(PERIPH_ID_TMR, 1);
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clock_set_enable(PERIPH_ID_CPU, 1);
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clock_set_enable(PERIPH_ID_EMC, 1);
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clock_set_enable(PERIPH_ID_I2C5, 1);
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clock_set_enable(PERIPH_ID_APBDMA, 1);
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clock_set_enable(PERIPH_ID_MEM, 1);
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clock_set_enable(PERIPH_ID_CORESIGHT, 1);
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clock_set_enable(PERIPH_ID_MSELECT, 1);
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clock_set_enable(PERIPH_ID_DVFS, 1);
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/*
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* Set MSELECT clock source as PLLP (00), and ask for a clock
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* divider that would set the MSELECT clock at 102MHz for a
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* PLLP base of 408MHz.
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*/
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clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
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CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
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/* Give clock time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
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clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
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/* Give clock time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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/* Take required peripherals out of reset */
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debug("Taking periphs out of reset\n");
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reset_set_enable(PERIPH_ID_CACHE2, 0);
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reset_set_enable(PERIPH_ID_GPIO, 0);
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reset_set_enable(PERIPH_ID_TMR, 0);
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reset_set_enable(PERIPH_ID_COP, 0);
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reset_set_enable(PERIPH_ID_EMC, 0);
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reset_set_enable(PERIPH_ID_I2C5, 0);
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reset_set_enable(PERIPH_ID_APBDMA, 0);
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reset_set_enable(PERIPH_ID_MEM, 0);
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reset_set_enable(PERIPH_ID_CORESIGHT, 0);
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reset_set_enable(PERIPH_ID_MSELECT, 0);
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reset_set_enable(PERIPH_ID_DVFS, 0);
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debug("tegra124_init_clocks exit\n");
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}
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static bool is_partition_powered(u32 partid)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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/* Get power gate status */
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reg = readl(&pmc->pmc_pwrgate_status);
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return !!(reg & (1 << partid));
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}
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static void power_partition(u32 partid)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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debug("%s: part ID = %08X\n", __func__, partid);
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/* Is the partition already on? */
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if (!is_partition_powered(partid)) {
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/* No, toggle the partition power state (OFF -> ON) */
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debug("power_partition, toggling state\n");
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writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
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/* Wait for the power to come up */
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while (!is_partition_powered(partid))
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;
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/* Give I/O signals time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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}
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}
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void powerup_cpus(void)
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{
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debug("powerup_cpus entry\n");
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/* We boot to the fast cluster */
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debug("powerup_cpus entry: G cluster\n");
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/* Power up the fast cluster rail partition */
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debug("powerup_cpus: CRAIL\n");
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power_partition(CRAIL);
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/* Power up the fast cluster non-CPU partition */
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debug("powerup_cpus: C0NC\n");
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power_partition(C0NC);
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/* Power up the fast cluster CPU0 partition */
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debug("powerup_cpus: CE0\n");
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power_partition(CE0);
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debug("powerup_cpus: done\n");
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}
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void start_cpu(u32 reset_vector)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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debug("start_cpu entry, reset_vector = %x\n", reset_vector);
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tegra124_init_clocks();
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/* Set power-gating timer multiplier */
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clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
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setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
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enable_cpu_power_rail();
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enable_cpu_clocks();
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clock_enable_coresight(1);
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remove_cpu_resets();
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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powerup_cpus();
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debug("start_cpu exit, should continue @ reset_vector\n");
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}
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