powerpc: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
2bf9557744
commit
36aa822880
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@ -1,103 +0,0 @@
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#ifndef I2C_EXPORT_H
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#define I2C_EXPORT_H
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/****************************************************
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*
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* Copyright Motrola 1999
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*
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****************************************************/
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/* These are the defined return values for the I2C_do_transaction function.
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* Any non-zero value indicates failure. Failure modes can be added for
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* more detailed error reporting.
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*/
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typedef enum _i2c_status
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{
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I2C_SUCCESS = 0,
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I2C_ERROR,
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} I2C_Status;
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/* These are the defined tasks for I2C_do_transaction.
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* Modes for SLAVE_RCV and SLAVE_XMIT will be added.
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*/
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typedef enum _i2c_transaction_mode
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{
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I2C_MASTER_RCV = 0,
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I2C_MASTER_XMIT = 1,
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} I2C_TRANSACTION_MODE;
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typedef enum _i2c_interrupt_mode
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{
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I2C_INT_DISABLE = 0,
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I2C_INT_ENABLE = 1,
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} I2C_INTERRUPT_MODE;
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typedef enum _i2c_stop
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{
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I2C_NO_STOP = 0,
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I2C_STOP = 1,
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} I2C_STOP_MODE;
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typedef enum _i2c_restart
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{
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I2C_NO_RESTART = 0,
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I2C_RESTART = 1,
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} I2C_RESTART_MODE;
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/******************** App. API ********************
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* The application API is for user level application
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* to use the functionality provided by I2C driver.
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* This is a "generic" I2C interface, it should contain
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* nothing specific to the Kahlua implementation.
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* Only the generic functions are exported by the library.
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*
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* Note: Its App.s responsibility to swap the data
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* byte. In our API, we just transfer whatever
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* we are given
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**************************************************/
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/* Initialize I2C unit with the following:
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* driver's slave address
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* interrupt enabled
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* optional pointer to application layer print function
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*
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* These parameters may be added:
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* desired clock rate
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* digital filter frequency sampling rate
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*
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* This function must be called before I2C unit can be used.
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*/
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extern I2C_Status I2C_Initialize(
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unsigned char addr, /* driver's I2C slave address */
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I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt
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* 0 - disable I2C interrupt
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*/
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int (*app_print_function)(char *,...)); /* pointer to optional "printf"
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* provided by application
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*/
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/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
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* are implemented. Both are only in polling mode.
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*
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* en_int controls interrupt/polling mode
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* act is the type of transaction
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* addr is the I2C address of the slave device
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* len is the length of data to send or receive
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* buffer is the address of the data buffer
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* stop = I2C_NO_STOP, don't signal STOP at end of transaction
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* I2C_STOP, signal STOP at end of transaction
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* retry is the timeout retry value, currently ignored
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* rsta = I2C_NO_RESTART, this is not continuation of existing transaction
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* I2C_RESTART, this is a continuation of existing transaction
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*/
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extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
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I2C_TRANSACTION_MODE act,
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unsigned char i2c_addr,
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unsigned char data_addr,
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int len,
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char *buffer,
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I2C_STOP_MODE stop,
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int retry,
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I2C_RESTART_MODE rsta);
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#endif
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@ -1,38 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*-----------------------------------------------------------------------
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* Timer value for timer 2, ICLK = 10
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*
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* SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
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* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
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*
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* SPEED_FCOUNT2 timer 2 counting frequency
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* GCLK CPU clock
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* SPEED_TMR2_PS prescaler
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*/
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#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
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/*-----------------------------------------------------------------------
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* Timer value for PIT
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*
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* PIT_TIME = SPEED_PITC / PITRTCLK
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* PITRTCLK = 8192
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*/
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#define SPEED_PITC (82 << 16) /* start counting from 82 */
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/*
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* The new value for PTA is calculated from
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*
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* PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
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*
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* gclk CPU clock (not bus clock !)
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* Trefresh Refresh cycle * 4 (four word bursts used)
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* DFBRG For normal mode (no clock reduction) always 0
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* PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
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* NCS Number of SDRAM banks (chip selects) on this UPM.
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*/
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@ -1,146 +0,0 @@
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/*
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* MPC85xx I/O port pin manipulation functions
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*/
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#ifndef _ASM_IOPIN_85xx_H_
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#define _ASM_IOPIN_85xx_H_
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#include <linux/types.h>
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#include <asm/immap_85xx.h>
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#ifdef __KERNEL__
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typedef struct {
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u_char port:2; /* port number (A=0, B=1, C=2, D=3) */
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u_char pin:5; /* port pin (0-31) */
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u_char flag:1; /* for whatever */
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} iopin_t;
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#define IOPIN_PORTA 0
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#define IOPIN_PORTB 1
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#define IOPIN_PORTC 2
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#define IOPIN_PORTD 3
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extern __inline__ void iopin_set_high (iopin_t * iopin)
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{
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volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
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datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
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}
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extern __inline__ void iopin_set_low (iopin_t * iopin)
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{
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volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
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datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
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}
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extern __inline__ uint iopin_is_high (iopin_t * iopin)
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{
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volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
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return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
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}
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extern __inline__ uint iopin_is_low (iopin_t * iopin)
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{
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volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
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return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
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}
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extern __inline__ void iopin_set_out (iopin_t * iopin)
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{
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volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
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dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
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}
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extern __inline__ void iopin_set_in (iopin_t * iopin)
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{
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volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
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dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
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}
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extern __inline__ uint iopin_is_out (iopin_t * iopin)
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{
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volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
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return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
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}
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extern __inline__ uint iopin_is_in (iopin_t * iopin)
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{
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volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
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return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
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}
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extern __inline__ void iopin_set_odr (iopin_t * iopin)
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{
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volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
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odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
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}
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extern __inline__ void iopin_set_act (iopin_t * iopin)
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{
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volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
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odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
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}
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extern __inline__ uint iopin_is_odr (iopin_t * iopin)
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{
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volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
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return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
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}
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extern __inline__ uint iopin_is_act (iopin_t * iopin)
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{
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volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
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return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
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}
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extern __inline__ void iopin_set_ded (iopin_t * iopin)
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{
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volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
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parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
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}
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extern __inline__ void iopin_set_gen (iopin_t * iopin)
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{
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volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
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parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
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}
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extern __inline__ uint iopin_is_ded (iopin_t * iopin)
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{
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volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
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return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
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}
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extern __inline__ uint iopin_is_gen (iopin_t * iopin)
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{
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volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
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return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
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}
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extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
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{
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volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
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sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
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}
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extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
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{
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volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
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sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
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}
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extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
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{
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volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
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return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
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}
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extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
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{
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volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
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return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_IOPIN_85xx_H_ */
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@ -1,643 +0,0 @@
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/* 11/02/95 */
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/*----------------------------------------------------------------------------*/
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/* Plug and Play header definitions */
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/*----------------------------------------------------------------------------*/
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/* Structure map for PnP on PowerPC Reference Platform */
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/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */
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/* (or later versions) is available on Compuserve in the PLUGPLAY area. */
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/* This code has extensions to that specification, namely new short and */
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/* long tag types for platform dependent information */
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/* Warning: LE notation used throughout this file */
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/* For enum's: if given in hex then they are bit significant, i.e. */
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/* only one bit is on for each enum */
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#ifndef _PNP_
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#define _PNP_
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#ifndef __ASSEMBLY__
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#define MAX_MEM_REGISTERS 9
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#define MAX_IO_PORTS 20
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#define MAX_IRQS 7
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/*#define MAX_DMA_CHANNELS 7*/
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/* Interrupt controllers */
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#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */
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#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */
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#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */
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#define PNPinterrupt3 "PNP0003" /* APIC */
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#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */
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/* Timers */
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#define PNPtimer0 "PNP0100" /* AT Timer */
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#define PNPtimer1 "PNP0101" /* EISA Timer */
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#define PNPtimer2 "PNP0102" /* MCA Timer */
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/* DMA controllers */
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#define PNPdma0 "PNP0200" /* AT DMA Controller */
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#define PNPdma1 "PNP0201" /* EISA DMA Controller */
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#define PNPdma2 "PNP0202" /* MCA DMA Controller */
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/* start of August 15, 1994 additions */
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/* CMOS */
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#define PNPCMOS "IBM0009" /* CMOS */
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/* L2 Cache */
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#define PNPL2 "IBM0007" /* L2 Cache */
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/* NVRAM */
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#define PNPNVRAM "IBM0008" /* NVRAM */
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/* Power Management */
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#define PNPPM "IBM0005" /* Power Management */
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/* end of August 15, 1994 additions */
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/* Keyboards */
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#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */
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#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */
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#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */
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#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */
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#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */
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#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */
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#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */
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#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */
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/* Parallel port controllers */
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#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */
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#define PNPparallel1 "PNP0401" /* ECP Parallel Port */
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#define PNPepp "IBM001C" /* EPP Parallel Port */
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/* Serial port controllers */
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#define PNPserial0 "PNP0500" /* Standard PC Serial port */
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#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */
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/* Disk controllers */
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#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */
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#define PNPdisk1 "PNP0601" /* Plus Hardcard II */
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#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */
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/* Diskette controllers */
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#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */
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/* Display controllers */
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#define PNPdisplay0 "PNP0900" /* VGA Compatible */
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#define PNPdisplay1 "PNP0901" /* Video Seven VGA */
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#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */
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#define PNPdisplay3 "PNP0903" /* Trident VGA */
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#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */
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#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */
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#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */
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#define PNPdisplay7 "PNP0907" /* Western Digital VGA */
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#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */
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#define PNPdisplay9 "PNP0909" /* S3 */
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#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */
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#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */
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#define PNPdisplayC "PNP090C" /* XGA Compatible */
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#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */
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#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */
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#define PNPdisplayF "PNP090F" /* Oak Technology VGA */
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/* Peripheral busses */
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#define PNPbuses0 "PNP0A00" /* ISA Bus */
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#define PNPbuses1 "PNP0A01" /* EISA Bus */
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#define PNPbuses2 "PNP0A02" /* MCA Bus */
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#define PNPbuses3 "PNP0A03" /* PCI Bus */
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#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */
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/* RTC, BIOS, planar devices */
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#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */
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#define PNPrtc0 "PNP0B00" /* AT RTC */
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#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */
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#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */
|
||||
#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */
|
||||
#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */
|
||||
|
||||
/* PCMCIA controller */
|
||||
|
||||
#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */
|
||||
|
||||
/* Mice */
|
||||
|
||||
#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */
|
||||
#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */
|
||||
#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */
|
||||
#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */
|
||||
#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */
|
||||
#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */
|
||||
#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */
|
||||
#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */
|
||||
#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */
|
||||
#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */
|
||||
#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */
|
||||
#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */
|
||||
|
||||
/* Modems */
|
||||
|
||||
#define PNPmodem0 "PNP9000" /* Specific IDs TBD */
|
||||
|
||||
/* Network controllers */
|
||||
|
||||
#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */
|
||||
#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */
|
||||
#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */
|
||||
#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */
|
||||
#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */
|
||||
#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */
|
||||
#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */
|
||||
#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */
|
||||
|
||||
/* SCSI controllers */
|
||||
|
||||
#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */
|
||||
#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */
|
||||
#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/
|
||||
#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */
|
||||
#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */
|
||||
#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */
|
||||
#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */
|
||||
|
||||
/* Sound/Video, Multimedia */
|
||||
|
||||
#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */
|
||||
#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */
|
||||
#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */
|
||||
#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */
|
||||
#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */
|
||||
#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */
|
||||
#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */
|
||||
#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */
|
||||
|
||||
/* Operator Panel */
|
||||
#define PNPopctl "IBM000B" /* Operator's panel */
|
||||
|
||||
/* Service Processor */
|
||||
#define PNPsp "IBM0011" /* IBM Service Processor */
|
||||
#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */
|
||||
#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */
|
||||
|
||||
/* Memory Controller */
|
||||
#define PNPmemctl "IBM000A" /* Memory controller */
|
||||
|
||||
/* Graphics Assist */
|
||||
#define PNPg_assist "IBM0014" /* Graphics Assist */
|
||||
|
||||
/* Miscellaneous Device Controllers */
|
||||
#define PNPtablet "IBM0019" /* IBM Tablet Controller */
|
||||
|
||||
/* PNP Packet Handles */
|
||||
|
||||
#define S1_Packet 0x0A /* Version resource */
|
||||
#define S2_Packet 0x15 /* Logical DEVID (without flags) */
|
||||
#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */
|
||||
#define S3_Packet 0x1C /* Compatible device ID */
|
||||
#define S4_Packet 0x22 /* IRQ resource (without flags) */
|
||||
#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */
|
||||
#define S5_Packet 0x2A /* DMA resource */
|
||||
#define S6_Packet 0x30 /* Depend funct start (w/o priority) */
|
||||
#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */
|
||||
#define S7_Packet 0x38 /* Depend funct end */
|
||||
#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */
|
||||
#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */
|
||||
#define S14_Packet 0x71 /* Vendor defined */
|
||||
#define S15_Packet 0x78 /* End of resource (w/o checksum) */
|
||||
#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */
|
||||
#define L1_Packet 0x81 /* Memory range */
|
||||
#define L1_Shadow 0x20 /* Memory is shadowable */
|
||||
#define L1_32bit_mem 0x18 /* 32-bit memory only */
|
||||
#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */
|
||||
#define L1_Decode_Hi 0x04 /* decode supports high address */
|
||||
#define L1_Cache 0x02 /* read cacheable, write-through */
|
||||
#define L1_Writeable 0x01 /* Memory is writeable */
|
||||
#define L2_Packet 0x82 /* ANSI ID string */
|
||||
#define L3_Packet 0x83 /* Unicode ID string */
|
||||
#define L4_Packet 0x84 /* Vendor defined */
|
||||
#define L5_Packet 0x85 /* Large I/O */
|
||||
#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */
|
||||
#define END_TAG 0x78 /* End of resource */
|
||||
#define DF_START_TAG 0x30 /* Dependent function start */
|
||||
#define DF_START_TAG_priority 0x31 /* Dependent function start */
|
||||
#define DF_END_TAG 0x38 /* Dependent function end */
|
||||
#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */
|
||||
|
||||
/* Device Base Type Codes */
|
||||
|
||||
typedef enum _PnP_BASE_TYPE {
|
||||
Reserved = 0,
|
||||
MassStorageDevice = 1,
|
||||
NetworkInterfaceController = 2,
|
||||
DisplayController = 3,
|
||||
MultimediaController = 4,
|
||||
MemoryController = 5,
|
||||
BridgeController = 6,
|
||||
CommunicationsDevice = 7,
|
||||
SystemPeripheral = 8,
|
||||
InputDevice = 9,
|
||||
ServiceProcessor = 0x0A, /* 11/2/95 */
|
||||
} PnP_BASE_TYPE;
|
||||
|
||||
/* Device Sub Type Codes */
|
||||
|
||||
typedef enum _PnP_SUB_TYPE {
|
||||
SCSIController = 0,
|
||||
IDEController = 1,
|
||||
FloppyController = 2,
|
||||
IPIController = 3,
|
||||
OtherMassStorageController = 0x80,
|
||||
|
||||
EthernetController = 0,
|
||||
TokenRingController = 1,
|
||||
FDDIController = 2,
|
||||
OtherNetworkController = 0x80,
|
||||
|
||||
VGAController= 0,
|
||||
SVGAController= 1,
|
||||
XGAController= 2,
|
||||
OtherDisplayController = 0x80,
|
||||
|
||||
VideoController = 0,
|
||||
AudioController = 1,
|
||||
OtherMultimediaController = 0x80,
|
||||
|
||||
RAM = 0,
|
||||
FLASH = 1,
|
||||
OtherMemoryDevice = 0x80,
|
||||
|
||||
HostProcessorBridge = 0,
|
||||
ISABridge = 1,
|
||||
EISABridge = 2,
|
||||
MicroChannelBridge = 3,
|
||||
PCIBridge = 4,
|
||||
PCMCIABridge = 5,
|
||||
VMEBridge = 6,
|
||||
OtherBridgeDevice = 0x80,
|
||||
|
||||
RS232Device = 0,
|
||||
ATCompatibleParallelPort = 1,
|
||||
OtherCommunicationsDevice = 0x80,
|
||||
|
||||
ProgrammableInterruptController = 0,
|
||||
DMAController = 1,
|
||||
SystemTimer = 2,
|
||||
RealTimeClock = 3,
|
||||
L2Cache = 4,
|
||||
NVRAM = 5,
|
||||
PowerManagement = 6,
|
||||
CMOS = 7,
|
||||
OperatorPanel = 8,
|
||||
ServiceProcessorClass1 = 9,
|
||||
ServiceProcessorClass2 = 0xA,
|
||||
ServiceProcessorClass3 = 0xB,
|
||||
GraphicAssist = 0xC,
|
||||
SystemPlanar = 0xF, /* 10/5/95 */
|
||||
OtherSystemPeripheral = 0x80,
|
||||
|
||||
KeyboardController = 0,
|
||||
Digitizer = 1,
|
||||
MouseController = 2,
|
||||
TabletController = 3, /* 10/27/95 */
|
||||
OtherInputController = 0x80,
|
||||
|
||||
GeneralMemoryController = 0,
|
||||
} PnP_SUB_TYPE;
|
||||
|
||||
/* Device Interface Type Codes */
|
||||
|
||||
typedef enum _PnP_INTERFACE {
|
||||
General = 0,
|
||||
GeneralSCSI = 0,
|
||||
GeneralIDE = 0,
|
||||
ATACompatible = 1,
|
||||
|
||||
GeneralFloppy = 0,
|
||||
Compatible765 = 1,
|
||||
NS398_Floppy = 2, /* NS Super I/O wired to use index
|
||||
register at port 398 and data
|
||||
register at port 399 */
|
||||
NS26E_Floppy = 3, /* Ports 26E and 26F */
|
||||
NS15C_Floppy = 4, /* Ports 15C and 15D */
|
||||
NS2E_Floppy = 5, /* Ports 2E and 2F */
|
||||
CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */
|
||||
|
||||
GeneralIPI = 0,
|
||||
|
||||
GeneralEther = 0,
|
||||
GeneralToken = 0,
|
||||
GeneralFDDI = 0,
|
||||
|
||||
GeneralVGA = 0,
|
||||
GeneralSVGA = 0,
|
||||
GeneralXGA = 0,
|
||||
|
||||
GeneralVideo = 0,
|
||||
GeneralAudio = 0,
|
||||
CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */
|
||||
|
||||
GeneralRAM = 0,
|
||||
GeneralFLASH = 0,
|
||||
PCIMemoryController = 0, /* PCI Config Method */
|
||||
RS6KMemoryController = 1, /* RS6K Config Method */
|
||||
|
||||
GeneralHostBridge = 0,
|
||||
GeneralISABridge = 0,
|
||||
GeneralEISABridge = 0,
|
||||
GeneralMCABridge = 0,
|
||||
GeneralPCIBridge = 0,
|
||||
PCIBridgeDirect = 0,
|
||||
PCIBridgeIndirect = 1,
|
||||
PCIBridgeRS6K = 2,
|
||||
GeneralPCMCIABridge = 0,
|
||||
GeneralVMEBridge = 0,
|
||||
|
||||
GeneralRS232 = 0,
|
||||
COMx = 1,
|
||||
Compatible16450 = 2,
|
||||
Compatible16550 = 3,
|
||||
NS398SerPort = 4, /* NS Super I/O wired to use index
|
||||
register at port 398 and data
|
||||
register at port 399 */
|
||||
NS26ESerPort = 5, /* Ports 26E and 26F */
|
||||
NS15CSerPort = 6, /* Ports 15C and 15D */
|
||||
NS2ESerPort = 7, /* Ports 2E and 2F */
|
||||
|
||||
GeneralParPort = 0,
|
||||
LPTx = 1,
|
||||
NS398ParPort = 2, /* NS Super I/O wired to use index
|
||||
register at port 398 and data
|
||||
register at port 399 */
|
||||
NS26EParPort = 3, /* Ports 26E and 26F */
|
||||
NS15CParPort = 4, /* Ports 15C and 15D */
|
||||
NS2EParPort = 5, /* Ports 2E and 2F */
|
||||
|
||||
GeneralPIC = 0,
|
||||
ISA_PIC = 1,
|
||||
EISA_PIC = 2,
|
||||
MPIC = 3,
|
||||
RS6K_PIC = 4,
|
||||
|
||||
GeneralDMA = 0,
|
||||
ISA_DMA = 1,
|
||||
EISA_DMA = 2,
|
||||
|
||||
GeneralTimer = 0,
|
||||
ISA_Timer = 1,
|
||||
EISA_Timer = 2,
|
||||
GeneralRTC = 0,
|
||||
ISA_RTC = 1,
|
||||
|
||||
StoreThruOnly = 1,
|
||||
StoreInEnabled = 2,
|
||||
RS6KL2Cache = 3,
|
||||
|
||||
IndirectNVRAM = 0, /* Indirectly addressed */
|
||||
DirectNVRAM = 1, /* Memory Mapped */
|
||||
IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */
|
||||
|
||||
GeneralPowerManagement = 0,
|
||||
EPOWPowerManagement = 1,
|
||||
PowerControl = 2, /* d1378 */
|
||||
|
||||
GeneralCMOS = 0,
|
||||
|
||||
GeneralOPPanel = 0,
|
||||
HarddiskLight = 1,
|
||||
CDROMLight = 2,
|
||||
PowerLight = 3,
|
||||
KeyLock = 4,
|
||||
ANDisplay = 5, /* AlphaNumeric Display */
|
||||
SystemStatusLED = 6, /* 3 digit 7 segment LED */
|
||||
CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */
|
||||
|
||||
GeneralServiceProcessor = 0,
|
||||
|
||||
TransferData = 1,
|
||||
IGMC32 = 2,
|
||||
IGMC64 = 3,
|
||||
|
||||
GeneralSystemPlanar = 0, /* 10/5/95 */
|
||||
|
||||
} PnP_INTERFACE;
|
||||
|
||||
/* PnP resources */
|
||||
|
||||
/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
|
||||
|
||||
typedef struct _SERIAL_ID {
|
||||
unsigned char VendorID0; /* Bit(7)=0 */
|
||||
/* Bits(6:2)=1st character in */
|
||||
/* compressed ASCII */
|
||||
/* Bits(1:0)=2nd character in */
|
||||
/* compressed ASCII bits(4:3) */
|
||||
unsigned char VendorID1; /* Bits(7:5)=2nd character in */
|
||||
/* compressed ASCII bits(2:0) */
|
||||
/* Bits(4:0)=3rd character in */
|
||||
/* compressed ASCII */
|
||||
unsigned char VendorID2; /* Product number - vendor assigned */
|
||||
unsigned char VendorID3; /* Product number - vendor assigned */
|
||||
|
||||
/* Serial number is to provide uniqueness if more than one board of same */
|
||||
/* type is in system. Must be "FFFFFFFF" if feature not supported. */
|
||||
|
||||
unsigned char Serial0; /* Unique serial number bits (7:0) */
|
||||
unsigned char Serial1; /* Unique serial number bits (15:8) */
|
||||
unsigned char Serial2; /* Unique serial number bits (23:16) */
|
||||
unsigned char Serial3; /* Unique serial number bits (31:24) */
|
||||
unsigned char Checksum;
|
||||
} SERIAL_ID;
|
||||
|
||||
typedef enum _PnPItemName {
|
||||
Unused = 0,
|
||||
PnPVersion = 1,
|
||||
LogicalDevice = 2,
|
||||
CompatibleDevice = 3,
|
||||
IRQFormat = 4,
|
||||
DMAFormat = 5,
|
||||
StartDepFunc = 6,
|
||||
EndDepFunc = 7,
|
||||
IOPort = 8,
|
||||
FixedIOPort = 9,
|
||||
Res1 = 10,
|
||||
Res2 = 11,
|
||||
Res3 = 12,
|
||||
SmallVendorItem = 14,
|
||||
EndTag = 15,
|
||||
MemoryRange = 1,
|
||||
ANSIIdentifier = 2,
|
||||
UnicodeIdentifier = 3,
|
||||
LargeVendorItem = 4,
|
||||
MemoryRange32 = 5,
|
||||
MemoryRangeFixed32 = 6,
|
||||
} PnPItemName;
|
||||
|
||||
/* Define a bunch of access functions for the bits in the tag field */
|
||||
|
||||
/* Tag type - 0 = small; 1 = large */
|
||||
#define tag_type(t) (((t) & 0x80)>>7)
|
||||
#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
|
||||
|
||||
/* Small item name is 4 bits - one of PnPItemName enum above */
|
||||
#define tag_small_item_name(t) (((t) & 0x78)>>3)
|
||||
#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
|
||||
|
||||
/* Small item count is 3 bits - count of further bytes in packet */
|
||||
#define tag_small_count(t) ((t) & 0x07)
|
||||
#define set_tag_count(t,v) (t = (t & 0x78) | (v))
|
||||
|
||||
/* Large item name is 7 bits - one of PnPItemName enum above */
|
||||
#define tag_large_item_name(t) ((t) & 0x7f)
|
||||
#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
|
||||
|
||||
/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
|
||||
|
||||
typedef union _PnP_TAG_PACKET {
|
||||
struct _S1_Pack{ /* VERSION PACKET */
|
||||
unsigned char Tag; /* small tag = 0x0a */
|
||||
unsigned char Version[2]; /* PnP version, Vendor version */
|
||||
} S1_Pack;
|
||||
|
||||
struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */
|
||||
unsigned char Tag; /* small tag = 0x15 or 0x16 */
|
||||
unsigned char DevId[4]; /* Logical device id */
|
||||
unsigned char Flags[2]; /* bit(0) boot device; */
|
||||
/* bit(7:1) cmd in range x31-x37 */
|
||||
/* bit(7:0) cmd in range x28-x3f (opt)*/
|
||||
} S2_Pack;
|
||||
|
||||
struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */
|
||||
unsigned char Tag; /* small tag = 0x1c */
|
||||
unsigned char CompatId[4]; /* Compatible device id */
|
||||
} S3_Pack;
|
||||
|
||||
struct _S4_Pack{ /* IRQ PACKET */
|
||||
unsigned char Tag; /* small tag = 0x22 or 0x23 */
|
||||
unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */
|
||||
/* bit(0) is IRQ8 ... */
|
||||
unsigned char IRQInfo; /* optional; assume bit(0)=1; else */
|
||||
/* bit(0) - high true edge sensitive */
|
||||
/* bit(1) - low true edge sensitive */
|
||||
/* bit(2) - high true level sensitive*/
|
||||
/* bit(3) - low true level sensitive */
|
||||
/* bit(7:4) - must be 0 */
|
||||
} S4_Pack;
|
||||
|
||||
struct _S5_Pack{ /* DMA PACKET */
|
||||
unsigned char Tag; /* small tag = 0x2a */
|
||||
unsigned char DMAMask; /* bit(0) is channel 0 ... */
|
||||
unsigned char DMAInfo;
|
||||
} S5_Pack;
|
||||
|
||||
struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */
|
||||
unsigned char Tag; /* small tag = 0x30 or 0x31 */
|
||||
unsigned char Priority; /* Optional; if missing then x01; else*/
|
||||
/* x00 = best possible */
|
||||
/* x01 = acceptible */
|
||||
/* x02 = sub-optimal but functional */
|
||||
} S6_Pack;
|
||||
|
||||
struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */
|
||||
unsigned char Tag; /* small tag = 0x38 */
|
||||
} S7_Pack;
|
||||
|
||||
struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */
|
||||
unsigned char Tag; /* small tag x47 */
|
||||
unsigned char IOInfo; /* x0 = decode only bits(9:0); */
|
||||
#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */
|
||||
unsigned char RangeMin[2]; /* Min base address */
|
||||
unsigned char RangeMax[2]; /* Max base address */
|
||||
unsigned char IOAlign; /* base alignmt, incr in 1B blocks */
|
||||
unsigned char IONum; /* number of contiguous I/O ports */
|
||||
} S8_Pack;
|
||||
|
||||
struct _S9_Pack{ /* FIXED I/O PORT PACKET */
|
||||
unsigned char Tag; /* small tag = 0x4b */
|
||||
unsigned char Range[2]; /* base address 10 bits */
|
||||
unsigned char IONum; /* number of contiguous I/O ports */
|
||||
} S9_Pack;
|
||||
|
||||
struct _S14_Pack{ /* VENDOR DEFINED PACKET */
|
||||
unsigned char Tag; /* small tag = 0x7m m = 1-7 */
|
||||
union _S14_Data{
|
||||
unsigned char Data[7]; /* Vendor defined */
|
||||
struct _S14_PPCPack{ /* Pr*p s14 pack */
|
||||
unsigned char Type; /* 00=non-IBM */
|
||||
unsigned char PPCData[6]; /* Vendor defined */
|
||||
} S14_PPCPack;
|
||||
} S14_Data;
|
||||
} S14_Pack;
|
||||
|
||||
struct _S15_Pack{ /* END PACKET */
|
||||
unsigned char Tag; /* small tag = 0x78 or 0x79 */
|
||||
unsigned char Check; /* optional - checksum */
|
||||
} S15_Pack;
|
||||
|
||||
struct _L1_Pack{ /* MEMORY RANGE PACKET */
|
||||
unsigned char Tag; /* large tag = 0x81 */
|
||||
unsigned char Count0; /* x09 */
|
||||
unsigned char Count1; /* x00 */
|
||||
unsigned char Data[9]; /* a variable array of bytes, */
|
||||
/* count in tag */
|
||||
} L1_Pack;
|
||||
|
||||
struct _L2_Pack{ /* ANSI ID STRING PACKET */
|
||||
unsigned char Tag; /* large tag = 0x82 */
|
||||
unsigned char Count0; /* Length of string */
|
||||
unsigned char Count1;
|
||||
unsigned char Identifier[1]; /* a variable array of bytes, */
|
||||
/* count in tag */
|
||||
} L2_Pack;
|
||||
|
||||
struct _L3_Pack{ /* UNICODE ID STRING PACKET */
|
||||
unsigned char Tag; /* large tag = 0x83 */
|
||||
unsigned char Count0; /* Length + 2 of string */
|
||||
unsigned char Count1;
|
||||
unsigned char Country0; /* TBD */
|
||||
unsigned char Country1; /* TBD */
|
||||
unsigned char Identifier[1]; /* a variable array of bytes, */
|
||||
/* count in tag */
|
||||
} L3_Pack;
|
||||
|
||||
struct _L4_Pack{ /* VENDOR DEFINED PACKET */
|
||||
unsigned char Tag; /* large tag = 0x84 */
|
||||
unsigned char Count0;
|
||||
unsigned char Count1;
|
||||
union _L4_Data{
|
||||
unsigned char Data[1]; /* a variable array of bytes, */
|
||||
/* count in tag */
|
||||
struct _L4_PPCPack{ /* Pr*p L4 packet */
|
||||
unsigned char Type; /* 00=non-IBM */
|
||||
unsigned char PPCData[1]; /* a variable array of bytes, */
|
||||
/* count in tag */
|
||||
} L4_PPCPack;
|
||||
} L4_Data;
|
||||
} L4_Pack;
|
||||
|
||||
struct _L5_Pack{
|
||||
unsigned char Tag; /* large tag = 0x85 */
|
||||
unsigned char Count0; /* Count = 17 */
|
||||
unsigned char Count1;
|
||||
unsigned char Data[17];
|
||||
} L5_Pack;
|
||||
|
||||
struct _L6_Pack{
|
||||
unsigned char Tag; /* large tag = 0x86 */
|
||||
unsigned char Count0; /* Count = 9 */
|
||||
unsigned char Count1;
|
||||
unsigned char Data[9];
|
||||
} L6_Pack;
|
||||
|
||||
} PnP_TAG_PACKET;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* ndef _PNP_ */
|
||||
|
|
@ -1,331 +0,0 @@
|
|||
/* 7/18/95 */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Residual Data header definitions and prototypes */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/* Structure map for RESIDUAL on PowerPC Reference Platform */
|
||||
/* residual.h - Residual data structure passed in r3. */
|
||||
/* Load point passed in r4 to boot image. */
|
||||
/* For enum's: if given in hex then they are bit significant, */
|
||||
/* i.e. only one bit is on for each enum */
|
||||
/* Reserved fields must be filled with zeros. */
|
||||
|
||||
#ifndef _RESIDUAL_
|
||||
#define _RESIDUAL_
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define MAX_CPUS 32 /* These should be set to the maximum */
|
||||
#define MAX_MEMS 64 /* number possible for this system. */
|
||||
#define MAX_DEVICES 256 /* Changing these will change the */
|
||||
#define AVE_PNP_SIZE 32 /* structure, hence the version of */
|
||||
#define MAX_MEM_SEGS 64 /* this header file. */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Public structures... */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "pnp.h"
|
||||
|
||||
typedef enum _L1CACHE_TYPE {
|
||||
NoneCAC = 0,
|
||||
SplitCAC = 1,
|
||||
CombinedCAC = 2
|
||||
} L1CACHE_TYPE;
|
||||
|
||||
typedef enum _TLB_TYPE {
|
||||
NoneTLB = 0,
|
||||
SplitTLB = 1,
|
||||
CombinedTLB = 2
|
||||
} TLB_TYPE;
|
||||
|
||||
typedef enum _FIRMWARE_SUPPORT {
|
||||
Conventional = 0x01,
|
||||
OpenFirmware = 0x02,
|
||||
Diagnostics = 0x04,
|
||||
LowDebug = 0x08,
|
||||
Multiboot = 0x10,
|
||||
LowClient = 0x20,
|
||||
Hex41 = 0x40,
|
||||
FAT = 0x80,
|
||||
ISO9660 = 0x0100,
|
||||
SCSI_InitiatorID_Override = 0x0200,
|
||||
Tape_Boot = 0x0400,
|
||||
FW_Boot_Path = 0x0800
|
||||
} FIRMWARE_SUPPORT;
|
||||
|
||||
typedef enum _FIRMWARE_SUPPLIERS {
|
||||
IBMFirmware = 0x00,
|
||||
MotoFirmware = 0x01, /* 7/18/95 */
|
||||
FirmWorks = 0x02, /* 10/5/95 */
|
||||
Bull = 0x03, /* 04/03/96 */
|
||||
} FIRMWARE_SUPPLIERS;
|
||||
|
||||
typedef enum _ENDIAN_SWITCH_METHODS {
|
||||
UsePort92 = 0x01,
|
||||
UsePCIConfigA8 = 0x02,
|
||||
UseFF001030 = 0x03,
|
||||
} ENDIAN_SWITCH_METHODS;
|
||||
|
||||
typedef enum _SPREAD_IO_METHODS {
|
||||
UsePort850 = 0x00,
|
||||
/*UsePCIConfigA8 = 0x02,*/
|
||||
} SPREAD_IO_METHODS;
|
||||
|
||||
typedef struct _VPD {
|
||||
|
||||
/* Box dependent stuff */
|
||||
unsigned char PrintableModel[32]; /* Null terminated string.
|
||||
Must be of the form:
|
||||
vvv,<20h>,<model designation>,<0x0>
|
||||
where vvv is the vendor ID
|
||||
e.g. IBM PPS MODEL 6015<0x0> */
|
||||
unsigned char Serial[16]; /* 12/94:
|
||||
Serial Number; must be of the form:
|
||||
vvv<serial number> where vvv is the
|
||||
vendor ID.
|
||||
e.g. IBM60151234567<20h><20h> */
|
||||
unsigned char Reserved[48];
|
||||
unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */
|
||||
unsigned long FirmwareSupports; /* See FirmwareSupport enum */
|
||||
unsigned long NvramSize; /* Size of nvram in bytes */
|
||||
unsigned long NumSIMMSlots;
|
||||
unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */
|
||||
unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */
|
||||
unsigned long SmpIar;
|
||||
unsigned long RAMErrLogOffset; /* Heap offset to error log */
|
||||
unsigned long Reserved5;
|
||||
unsigned long Reserved6;
|
||||
unsigned long ProcessorHz; /* Processor clock frequency in Hertz */
|
||||
unsigned long ProcessorBusHz; /* Processor bus clock frequency */
|
||||
unsigned long Reserved7;
|
||||
unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */
|
||||
unsigned long WordWidth; /* Word width in bits */
|
||||
unsigned long PageSize; /* Page size in bytes */
|
||||
unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache
|
||||
for which coherency is maintained;
|
||||
normally <= CacheLineSize. */
|
||||
unsigned long GranuleSize; /* Unit of lock allocation to avoid */
|
||||
/* false sharing of locks. */
|
||||
|
||||
/* L1 Cache variables */
|
||||
unsigned long CacheSize; /* L1 Cache size in KB. This is the */
|
||||
/* total size of the L1, whether */
|
||||
/* combined or split */
|
||||
unsigned long CacheAttrib; /* L1CACHE_TYPE */
|
||||
unsigned long CacheAssoc; /* L1 Cache associativity. Use this
|
||||
for combined cache. If split, put
|
||||
zeros here. */
|
||||
unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use
|
||||
for combined cache. If split, put
|
||||
zeros here. */
|
||||
/* For split L1 Cache: (= combined if combined cache) */
|
||||
unsigned long I_CacheSize;
|
||||
unsigned long I_CacheAssoc;
|
||||
unsigned long I_CacheLineSize;
|
||||
unsigned long D_CacheSize;
|
||||
unsigned long D_CacheAssoc;
|
||||
unsigned long D_CacheLineSize;
|
||||
|
||||
/* Translation Lookaside Buffer variables */
|
||||
unsigned long TLBSize; /* Total number of TLBs on the system */
|
||||
unsigned long TLBAttrib; /* Combined I+D or split TLB */
|
||||
unsigned long TLBAssoc; /* TLB Associativity. Use this for
|
||||
combined TLB. If split, put zeros
|
||||
here. */
|
||||
/* For split TLB: (= combined if combined TLB) */
|
||||
unsigned long I_TLBSize;
|
||||
unsigned long I_TLBAssoc;
|
||||
unsigned long D_TLBSize;
|
||||
unsigned long D_TLBAssoc;
|
||||
|
||||
unsigned long ExtendedVPD; /* Offset to extended VPD area;
|
||||
null if unused */
|
||||
} VPD;
|
||||
|
||||
typedef enum _DEVICE_FLAGS {
|
||||
Enabled = 0x4000, /* 1 - PCI device is enabled */
|
||||
Integrated = 0x2000,
|
||||
Failed = 0x1000, /* 1 - device failed POST code tests */
|
||||
Static = 0x0800, /* 0 - dynamically configurable
|
||||
1 - static */
|
||||
Dock = 0x0400, /* 0 - not a docking station device
|
||||
1 - is a docking station device */
|
||||
Boot = 0x0200, /* 0 - device cannot be used for BOOT
|
||||
1 - can be a BOOT device */
|
||||
Configurable = 0x0100, /* 1 - device is configurable */
|
||||
Disableable = 0x80, /* 1 - device can be disabled */
|
||||
PowerManaged = 0x40, /* 0 - not managed; 1 - managed */
|
||||
ReadOnly = 0x20, /* 1 - device is read only */
|
||||
Removable = 0x10, /* 1 - device is removable */
|
||||
ConsoleIn = 0x08,
|
||||
ConsoleOut = 0x04,
|
||||
Input = 0x02,
|
||||
Output = 0x01
|
||||
} DEVICE_FLAGS;
|
||||
|
||||
typedef enum _BUS_ID {
|
||||
ISADEVICE = 0x01,
|
||||
EISADEVICE = 0x02,
|
||||
PCIDEVICE = 0x04,
|
||||
PCMCIADEVICE = 0x08,
|
||||
PNPISADEVICE = 0x10,
|
||||
MCADEVICE = 0x20,
|
||||
MXDEVICE = 0x40, /* Devices on mezzanine bus */
|
||||
PROCESSORDEVICE = 0x80, /* Devices on processor bus */
|
||||
VMEDEVICE = 0x100,
|
||||
} BUS_ID;
|
||||
|
||||
typedef struct _DEVICE_ID {
|
||||
unsigned long BusId; /* See BUS_ID enum above */
|
||||
unsigned long DevId; /* Big Endian format */
|
||||
unsigned long SerialNum; /* For multiple usage of a single
|
||||
DevId */
|
||||
unsigned long Flags; /* See DEVICE_FLAGS enum above */
|
||||
unsigned char BaseType; /* See pnp.h for bit definitions */
|
||||
unsigned char SubType; /* See pnp.h for bit definitions */
|
||||
unsigned char Interface; /* See pnp.h for bit definitions */
|
||||
unsigned char Spare;
|
||||
} DEVICE_ID;
|
||||
|
||||
typedef union _BUS_ACCESS {
|
||||
struct _PnPAccess{
|
||||
unsigned char CSN;
|
||||
unsigned char LogicalDevNumber;
|
||||
unsigned short ReadDataPort;
|
||||
} PnPAccess;
|
||||
struct _ISAAccess{
|
||||
unsigned char SlotNumber; /* ISA Slot Number generally not
|
||||
available; 0 if unknown */
|
||||
unsigned char LogicalDevNumber;
|
||||
unsigned short ISAReserved;
|
||||
} ISAAccess;
|
||||
struct _MCAAccess{
|
||||
unsigned char SlotNumber;
|
||||
unsigned char LogicalDevNumber;
|
||||
unsigned short MCAReserved;
|
||||
} MCAAccess;
|
||||
struct _PCMCIAAccess{
|
||||
unsigned char SlotNumber;
|
||||
unsigned char LogicalDevNumber;
|
||||
unsigned short PCMCIAReserved;
|
||||
} PCMCIAAccess;
|
||||
struct _EISAAccess{
|
||||
unsigned char SlotNumber;
|
||||
unsigned char FunctionNumber;
|
||||
unsigned short EISAReserved;
|
||||
} EISAAccess;
|
||||
struct _PCIAccess{
|
||||
unsigned char BusNumber;
|
||||
unsigned char DevFuncNumber;
|
||||
unsigned short PCIReserved;
|
||||
} PCIAccess;
|
||||
struct _ProcBusAccess{
|
||||
unsigned char BusNumber;
|
||||
unsigned char BUID;
|
||||
unsigned short ProcBusReserved;
|
||||
} ProcBusAccess;
|
||||
} BUS_ACCESS;
|
||||
|
||||
/* Per logical device information */
|
||||
typedef struct _PPC_DEVICE {
|
||||
DEVICE_ID DeviceId;
|
||||
BUS_ACCESS BusAccess;
|
||||
|
||||
/* The following three are offsets into the DevicePnPHeap */
|
||||
/* All are in PnP compressed format */
|
||||
unsigned long AllocatedOffset; /* Allocated resource description */
|
||||
unsigned long PossibleOffset; /* Possible resource description */
|
||||
unsigned long CompatibleOffset; /* Compatible device identifiers */
|
||||
} PPC_DEVICE;
|
||||
|
||||
typedef enum _CPU_STATE {
|
||||
CPU_GOOD = 0, /* CPU is present, and active */
|
||||
CPU_GOOD_FW = 1, /* CPU is present, and in firmware */
|
||||
CPU_OFF = 2, /* CPU is present, but inactive */
|
||||
CPU_FAILED = 3, /* CPU is present, but failed POST */
|
||||
CPU_NOT_PRESENT = 255 /* CPU not present */
|
||||
} CPU_STATE;
|
||||
|
||||
typedef struct _PPC_CPU {
|
||||
unsigned long CpuType; /* Result of mfspr from Processor
|
||||
Version Register (PVR).
|
||||
PVR(0-15) = Version (e.g. 601)
|
||||
PVR(16-31 = EC Level */
|
||||
unsigned char CpuNumber; /* CPU Number for this processor */
|
||||
unsigned char CpuState; /* CPU State, see CPU_STATE enum */
|
||||
unsigned short Reserved;
|
||||
} PPC_CPU;
|
||||
|
||||
typedef struct _PPC_MEM {
|
||||
unsigned long SIMMSize; /* 0 - absent or bad
|
||||
8M, 32M (in MB) */
|
||||
} PPC_MEM;
|
||||
|
||||
typedef enum _MEM_USAGE {
|
||||
Other = 0x8000,
|
||||
ResumeBlock = 0x4000, /* for use by power management */
|
||||
SystemROM = 0x2000, /* Flash memory (populated) */
|
||||
UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */
|
||||
IOMemory = 0x0800,
|
||||
SystemIO = 0x0400,
|
||||
SystemRegs = 0x0200,
|
||||
PCIAddr = 0x0100,
|
||||
PCIConfig = 0x80,
|
||||
ISAAddr = 0x40,
|
||||
Unpopulated = 0x20, /* Unpopulated part of System Memory */
|
||||
Free = 0x10, /* Free part of System Memory */
|
||||
BootImage = 0x08, /* BootImage part of System Memory */
|
||||
FirmwareCode = 0x04, /* FirmwareCode part of System Memory */
|
||||
FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */
|
||||
FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/
|
||||
} MEM_USAGE;
|
||||
|
||||
typedef struct _MEM_MAP {
|
||||
unsigned long Usage; /* See MEM_USAGE above */
|
||||
unsigned long BasePage; /* Page number measured in 4KB pages */
|
||||
unsigned long PageCount; /* Page count measured in 4KB pages */
|
||||
} MEM_MAP;
|
||||
|
||||
typedef struct _RESIDUAL {
|
||||
unsigned long ResidualLength; /* Length of Residual */
|
||||
unsigned char Version; /* of this data structure */
|
||||
unsigned char Revision; /* of this data structure */
|
||||
unsigned short EC; /* of this data structure */
|
||||
/* VPD */
|
||||
VPD VitalProductData;
|
||||
/* CPU */
|
||||
unsigned short MaxNumCpus; /* Max CPUs in this system */
|
||||
unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */
|
||||
/* that there are unpopulated or */
|
||||
/* otherwise unusable cpu locations */
|
||||
PPC_CPU Cpus[MAX_CPUS];
|
||||
/* Memory */
|
||||
unsigned long TotalMemory; /* Total amount of memory installed */
|
||||
unsigned long GoodMemory; /* Total amount of good memory */
|
||||
unsigned long ActualNumMemSegs;
|
||||
MEM_MAP Segs[MAX_MEM_SEGS];
|
||||
unsigned long ActualNumMemories;
|
||||
PPC_MEM Memories[MAX_MEMS];
|
||||
/* Devices */
|
||||
unsigned long ActualNumDevices;
|
||||
PPC_DEVICE Devices[MAX_DEVICES];
|
||||
unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
|
||||
} RESIDUAL;
|
||||
|
||||
|
||||
extern RESIDUAL *res;
|
||||
extern void print_residual_device_info(void);
|
||||
extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
|
||||
unsigned char * DevID, int BaseType,
|
||||
int SubType, int Interface, int n);
|
||||
extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
|
||||
int n);
|
||||
extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
|
||||
unsigned packet_type,
|
||||
int n);
|
||||
extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
|
||||
unsigned packet_type,
|
||||
int n);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* ndef _RESIDUAL_ */
|
||||
Loading…
Reference in New Issue