- Fix bug for initial stack in data cache as pointed out by Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in data cache can be used even if the chip select is in use.
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stroese
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f3e0de60a6
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3720878599
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@ -30,6 +30,73 @@
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#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
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#ifdef CFG_INIT_DCACHE_CS
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# if (CFG_INIT_DCACHE_CS == 0)
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# define PBxAP pb0ap
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# define PBxCR pb0cr
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# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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# define PBxAP_VAL CFG_EBC_PB0AP
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# define PBxCR_VAL CFG_EBC_PB0CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 1)
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# define PBxAP pb1ap
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# define PBxCR pb1cr
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# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
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# define PBxAP_VAL CFG_EBC_PB1AP
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# define PBxCR_VAL CFG_EBC_PB1CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 2)
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# define PBxAP pb2ap
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# define PBxCR pb2cr
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# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
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# define PBxAP_VAL CFG_EBC_PB2AP
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# define PBxCR_VAL CFG_EBC_PB2CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 3)
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# define PBxAP pb3ap
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# define PBxCR pb3cr
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# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
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# define PBxAP_VAL CFG_EBC_PB3AP
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# define PBxCR_VAL CFG_EBC_PB3CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 4)
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# define PBxAP pb4ap
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# define PBxCR pb4cr
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# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
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# define PBxAP_VAL CFG_EBC_PB4AP
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# define PBxCR_VAL CFG_EBC_PB4CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 5)
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# define PBxAP pb5ap
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# define PBxCR pb5cr
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# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
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# define PBxAP_VAL CFG_EBC_PB5AP
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# define PBxCR_VAL CFG_EBC_PB5CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 6)
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# define PBxAP pb6ap
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# define PBxCR pb6cr
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# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
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# define PBxAP_VAL CFG_EBC_PB6AP
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# define PBxCR_VAL CFG_EBC_PB6CR
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# endif
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# endif
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# if (CFG_INIT_DCACHE_CS == 7)
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# define PBxAP pb7ap
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# define PBxCR pb7cr
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# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
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# define PBxAP_VAL CFG_EBC_PB7AP
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# define PBxCR_VAL CFG_EBC_PB7CR
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# endif
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# endif
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#endif /* CFG_INIT_DCACHE_CS */
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/*
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* Breath some life into the CPU...
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@ -82,37 +149,37 @@ cpu_init_f (void)
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mtebc(pb0cr, CFG_EBC_PB0CR);
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#endif
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#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
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#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
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mtebc(pb1ap, CFG_EBC_PB1AP);
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mtebc(pb1cr, CFG_EBC_PB1CR);
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#endif
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#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
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#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
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mtebc(pb2ap, CFG_EBC_PB2AP);
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mtebc(pb2cr, CFG_EBC_PB2CR);
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#endif
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#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
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#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
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mtebc(pb3ap, CFG_EBC_PB3AP);
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mtebc(pb3cr, CFG_EBC_PB3CR);
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#endif
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#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
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#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
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mtebc(pb4ap, CFG_EBC_PB4AP);
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mtebc(pb4cr, CFG_EBC_PB4CR);
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#endif
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#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
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#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
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mtebc(pb5ap, CFG_EBC_PB5AP);
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mtebc(pb5cr, CFG_EBC_PB5CR);
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#endif
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#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
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#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
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mtebc(pb6ap, CFG_EBC_PB6AP);
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mtebc(pb6cr, CFG_EBC_PB6CR);
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#endif
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#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
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#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
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mtebc(pb7ap, CFG_EBC_PB7AP);
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mtebc(pb7cr, CFG_EBC_PB7CR);
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#endif
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@ -146,6 +213,24 @@ int cpu_init_r (void)
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uint pvr = get_pvr();
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#endif
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#ifdef CFG_INIT_DCACHE_CS
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/*
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* Flush and invalidate dcache, then disable CS for temporary stack.
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* Afterwards, this CS can be used for other purposes
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*/
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dcache_disable(); /* flush and invalidate dcache */
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mtebc(PBxAP, 0);
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mtebc(PBxCR, 0); /* disable CS for temporary stack */
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#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
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/*
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* Write new value into CS register
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*/
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mtebc(PBxAP, PBxAP_VAL);
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mtebc(PBxCR, PBxCR_VAL);
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#endif
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#endif /* CFG_INIT_DCACHE_CS */
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/*
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* Write Ethernetaddress into on-chip register
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*/
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