imx6: add Bachmann OT1200 board
This patch adds support for the OT1200 series of devices. Following components are used in u-boot: + ethernet + i2c + emmc + gpio For more details see README. Changes v1 > v2 - make use of enable_cspi_clock(..) - fix usage of OUTPUT_40OHM define - added README Changes v2 > v3 - improve spelling in README - added own copy of mx6q_4x_mt41j128.cfg Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This commit is contained in:
Christian Gmeiner
Stefano Babic
parent
252499e603
commit
39d0973300
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@ -414,6 +414,9 @@ config TARGET_HUMMINGBOARD
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config TARGET_TQMA6
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bool "TQ Systems TQMa6 board"
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config TARGET_OT1200
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bool "Bachmann OT1200"
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config OMAP34XX
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bool "OMAP34XX SoC"
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@ -577,6 +580,7 @@ source "board/atmel/at91sam9rlek/Kconfig"
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source "board/atmel/at91sam9x5ek/Kconfig"
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source "board/atmel/sama5d3_xplained/Kconfig"
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source "board/atmel/sama5d3xek/Kconfig"
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source "board/bachmann/ot1200/Kconfig"
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source "board/balloon3/Kconfig"
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source "board/barco/titanium/Kconfig"
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source "board/bluegiga/apx4devkit/Kconfig"
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@ -0,0 +1,23 @@
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if TARGET_OT1200
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config SYS_CPU
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string
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default "armv7"
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config SYS_BOARD
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string
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default "ot1200"
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config SYS_VENDOR
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string
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default "bachmann"
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config SYS_SOC
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string
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default "mx6"
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config SYS_CONFIG_NAME
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string
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default "ot1200"
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endif
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@ -0,0 +1,6 @@
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BACHMANN ELECTRONIC OT1200 BOARD
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M: Christian Gmeiner <christian.gmeiner@gmail.com>
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S: Maintained
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F: board/bachmann/ot1200
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F: include/configs/ot1200.h
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F: configs/ot1200*_defconfig
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@ -0,0 +1,9 @@
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#
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# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
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# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
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# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := ot1200.o
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@ -0,0 +1,20 @@
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U-Boot for the Bachmann electronic GmbH OT1200 devices
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There are two different versions of the base board, which differ
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in the way ethernet is done. The variant detection is done during
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runtime based on the address of the found phy.
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- "mr" variant
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FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
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port is always up and auto-negotiation is not possible.
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- normal variant
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FEC is connected to a normal phy and auto-negotiation is possible.
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The variant name is part of the dtb file name loaded by u-boot. This
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make is possible to boot the linux kernel and make use variant specific
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devicetree (fixed-phy link).
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In order to support different display resoltuions/sizes the OT1200 devices
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are making use of EDID data stored in an i2c EEPROM.
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@ -0,0 +1,169 @@
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x020e05a8 0x00000030
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DATA 4 0x020e05b0 0x00000030
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DATA 4 0x020e0524 0x00000030
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DATA 4 0x020e051c 0x00000030
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DATA 4 0x020e0518 0x00000030
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DATA 4 0x020e050c 0x00000030
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DATA 4 0x020e05b8 0x00000030
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DATA 4 0x020e05c0 0x00000030
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DATA 4 0x020e05ac 0x00020030
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DATA 4 0x020e05b4 0x00020030
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DATA 4 0x020e0528 0x00020030
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DATA 4 0x020e0520 0x00020030
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DATA 4 0x020e0514 0x00020030
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DATA 4 0x020e0510 0x00020030
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DATA 4 0x020e05bc 0x00020030
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DATA 4 0x020e05c4 0x00020030
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DATA 4 0x020e056c 0x00020030
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DATA 4 0x020e0578 0x00020030
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DATA 4 0x020e0588 0x00020030
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DATA 4 0x020e0594 0x00020030
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DATA 4 0x020e057c 0x00020030
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DATA 4 0x020e0590 0x00003000
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DATA 4 0x020e0598 0x00003000
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DATA 4 0x020e058c 0x00000000
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DATA 4 0x020e059c 0x00003030
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DATA 4 0x020e05a0 0x00003030
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DATA 4 0x020e0784 0x00000030
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DATA 4 0x020e0788 0x00000030
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DATA 4 0x020e0794 0x00000030
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DATA 4 0x020e079c 0x00000030
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DATA 4 0x020e07a0 0x00000030
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DATA 4 0x020e07a4 0x00000030
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DATA 4 0x020e07a8 0x00000030
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DATA 4 0x020e0748 0x00000030
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DATA 4 0x020e074c 0x00000030
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DATA 4 0x020e0750 0x00020000
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DATA 4 0x020e0758 0x00000000
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DATA 4 0x020e0774 0x00020000
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DATA 4 0x020e078c 0x00000030
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DATA 4 0x020e0798 0x000C0000
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b481c 0x33333333
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DATA 4 0x021b4820 0x33333333
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DATA 4 0x021b4824 0x33333333
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DATA 4 0x021b4828 0x33333333
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DATA 4 0x021b0018 0x00081740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b000c 0x555A7974
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DATA 4 0x021b0010 0xDB538F64
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DATA 4 0x021b0014 0x01FF00DB
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DATA 4 0x021b002c 0x000026D2
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DATA 4 0x021b0030 0x005A1023
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DATA 4 0x021b0008 0x09444040
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DATA 4 0x021b0004 0x00025576
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DATA 4 0x021b0040 0x00000027
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DATA 4 0x021b0000 0x831A0000
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DATA 4 0x021b001c 0x04088032
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DATA 4 0x021b001c 0x0408803A
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DATA 4 0x021b001c 0x00008033
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DATA 4 0x021b001c 0x0000803B
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DATA 4 0x021b001c 0x00428031
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DATA 4 0x021b001c 0x00428039
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DATA 4 0x021b001c 0x19308030
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DATA 4 0x021b001c 0x19308038
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DATA 4 0x021b001c 0x04008040
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DATA 4 0x021b001c 0x04008048
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DATA 4 0x021b0800 0xA1380003
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DATA 4 0x021b4800 0xA1380003
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DATA 4 0x021b0020 0x00005800
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DATA 4 0x021b0818 0x00022227
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DATA 4 0x021b4818 0x00022227
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DATA 4 0x021b083c 0x434B0350
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DATA 4 0x021b0840 0x034C0359
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DATA 4 0x021b483c 0x434B0350
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DATA 4 0x021b4840 0x03650348
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DATA 4 0x021b0848 0x4436383B
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DATA 4 0x021b4848 0x39393341
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DATA 4 0x021b0850 0x35373933
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DATA 4 0x021b4850 0x48254A36
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DATA 4 0x021b080c 0x001F001F
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DATA 4 0x021b0810 0x001F001F
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DATA 4 0x021b480c 0x00440044
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DATA 4 0x021b4810 0x00440044
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b48b8 0x00000800
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DATA 4 0x021b001c 0x00000000
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DATA 4 0x021b0404 0x00011006
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/* set the default clock gate to save power */
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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DATA 4 0x020c407c 0x0F0000C3
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DATA 4 0x020c4080 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4 0x020e0010 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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/*
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* Setup CCM_CCOSR register as follows:
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*
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* cko1_en = 1 --> CKO1 enabled
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* cko1_div = 111 --> divide by 8
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* cko1_sel = 1011 --> ahb_clk_root
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*
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
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*/
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DATA 4 0x020c4060 0x000000fb
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@ -0,0 +1,251 @@
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/*
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* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2014, Bachmann electronic GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <malloc.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/arch/crm_regs.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <pca953x.h>
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#include <asm/gpio.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
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PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
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PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
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PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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}
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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};
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static void setup_iomux_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_spi();
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return 0;
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}
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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struct fsl_esdhc_cfg usdhc_cfg[] = {
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{USDHC3_BASE_ADDR},
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};
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int board_mmc_init(bd_t *bis)
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{
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 8;
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C3 - IO expander */
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
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.gp = IMX_GPIO_NR(3, 17)
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||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 18)
|
||||
}
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const pwm_pad[] = {
|
||||
MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
|
||||
};
|
||||
|
||||
static void leds_on(void)
|
||||
{
|
||||
/* turn on all possible leds connected via GPIO expander */
|
||||
i2c_set_bus_num(2);
|
||||
pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
|
||||
pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
|
||||
}
|
||||
|
||||
static void backlight_lcd_off(void)
|
||||
{
|
||||
unsigned gpio = IMX_GPIO_NR(2, 0);
|
||||
gpio_direction_output(gpio, 0);
|
||||
|
||||
gpio = IMX_GPIO_NR(2, 3);
|
||||
gpio_direction_output(gpio, 0);
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
uint32_t base = IMX_FEC_BASE;
|
||||
struct mii_dev *bus = NULL;
|
||||
struct phy_device *phydev = NULL;
|
||||
int ret;
|
||||
|
||||
setup_iomux_enet();
|
||||
|
||||
bus = fec_get_miibus(base, -1);
|
||||
if (!bus)
|
||||
return 0;
|
||||
|
||||
/* scan phy 0 and 5 */
|
||||
phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
|
||||
if (!phydev) {
|
||||
free(bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* depending on the phy address we can detect our board version */
|
||||
if (phydev->addr == 0)
|
||||
setenv("boardver", "");
|
||||
else
|
||||
setenv("boardver", "mr");
|
||||
|
||||
printf("using phy at %d\n", phydev->addr);
|
||||
ret = fec_probe(bis, -1, base, bus, phydev);
|
||||
if (ret) {
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
free(phydev);
|
||||
free(bus);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
backlight_lcd_off();
|
||||
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
|
||||
leds_on();
|
||||
|
||||
/* enable ecspi3 clocks */
|
||||
enable_cspi_clock(1, 2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: "CONFIG_SYS_BOARD"\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_OT1200=y
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2014 Bachmann electronic GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
/* FUSE Configs */
|
||||
#define CONFIG_CMD_FUSE
|
||||
#define CONFIG_MXC_OCOTP
|
||||
|
||||
/* UART Configs */
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* SF Configs */
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SPI_FLASH_MACRONIX
|
||||
#define CONFIG_SPI_FLASH_SST
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 2
|
||||
#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8))
|
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
|
||||
/* IO expander */
|
||||
#define CONFIG_PCA953X
|
||||
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
|
||||
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
|
||||
#define CONFIG_CMD_PCA953X
|
||||
#define CONFIG_CMD_PCA953X_INFO
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* OCOTP Configs */
|
||||
#define CONFIG_CMD_IMXOTP
|
||||
#define CONFIG_IMX_OTP
|
||||
#define IMX_OTP_BASE OCOTP_BASE_ADDR
|
||||
#define IMX_OTP_ADDR_MAX 0x7F
|
||||
#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
|
||||
#define IMX_OTPWRITE_ENABLED
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
#ifdef CONFIG_MX6Q
|
||||
#define CONFIG_CMD_SATA
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SATA Configs
|
||||
*/
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_DWC_AHSATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_LIBATA
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE MII100
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x5
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
/* Miscellaneous commands */
|
||||
#define CONFIG_CMD_BMODE
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Command definition */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_BOOTDELAY 2
|
||||
|
||||
#define CONFIG_PREBOOT ""
|
||||
|
||||
#define CONFIG_LOADADDR 0x12000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
|
||||
#define CONFIG_ENV_OFFSET (1024 * 1024)
|
||||
/* M25P16 has an erase size of 64 KiB */
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_SUPPORT_RAW_INITRD
|
||||
|
||||
/* FS Configs */
|
||||
#define CONFIG_CMD_EXT3
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
|
||||
#define CONFIG_BOOTP_SERVERIP
|
||||
#define CONFIG_BOOTP_BOOTFILE
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue