powerpc/85xx: Fix P2020DS booting
The following commit removed the code that set odt_rd_cfg and
odt_wr_cfg. With out this code P2020DS board will not boot:
commit 712cf7ab0b
Author: York Sun <yorksun@freescale.com>
Date: Mon Oct 3 09:19:53 2011 -0700
powerpc/mpc8xxx: Merge entries in DDR speed table
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
f81f19fafa
commit
3b001ad26d
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@ -57,6 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
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{
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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ulong ddr_freq;
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int i;
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if (ctrl_num) {
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if (ctrl_num) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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printf("Wrong parameter for controller number %d", ctrl_num);
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@ -65,6 +66,17 @@ void fsl_ddr_board_options(memctl_options_t *popts,
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if (!pdimm->n_ranks)
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if (!pdimm->n_ranks)
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return;
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return;
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/*
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* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
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* there are two dimms in the controller, set odt_rd_cfg to 3 and
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
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*/
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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}
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pbsp = dimm0;
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pbsp = dimm0;
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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