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ppc/p4080: Handle timebase enabling and frequency reporting 

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-09-17 01:52:37 -05:00
parent 7e4259bba4
commit 3c2a67eec8
3 changed files with 22 additions and 1 deletions
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4
cpu/mpc85xx/cpu.c
View File

@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
*/
unsigned long get_tbclk (void)
{
#ifdef CONFIG_FSL_CORENET
return (gd->bus_clk + 8) / 16;
#else
return (gd->bus_clk + 4UL)/8UL;
#endif
}

17
cpu/mpc85xx/cpu_init.c
View File

@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
* initialize a bunch of registers
*/
#ifdef CONFIG_FSL_CORENET
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */
out_be32(&rcpm->ctbenrl, (1 << whoami));
}
#endif
void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@ -229,6 +243,9 @@ void cpu_init_f (void)
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
#ifdef CONFIG_FSL_CORENET
corenet_tb_init();
#endif
}

2
cpu/mpc85xx/fdt.c
View File

@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 8, 1);
"timebase-frequency", get_tbclk(), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);