Initial mpc8610hpcd board files.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Jon Loeliger
parent
eff786a9b8
commit
3dd2db53ce
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# Copyright 2007 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o \
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../common/sys_eeprom.o \
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../common/pixis.o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS) $(SOBJS)
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.PHONY: distclean
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,25 @@
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# Copyright 2007 Freescale Semiconductor.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xfff00000
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PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2
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/*
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* Copyright 2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc86xx.h>
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#define LAWAR_TRGT_PCI1 0x00000000
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#define LAWAR_TRGT_PCIE1 0x00200000
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#define LAWAR_TRGT_PCIE2 0x00100000
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#define LAWAR_TRGT_LBC 0x00400000
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#define LAWAR_TRGT_DDR 0x00f00000
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#else
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#define LAWBAR1 0
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#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
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#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
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#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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addi r4,r7,0
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addi r5,r7,0
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/* Skip LAWAR0, start at LAWAR1 */
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lis r6,LAWBAR1@h
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ori r6,r6,LAWBAR1@l
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stwu r6, 0xc28(r4)
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lis r6,LAWAR1@h
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ori r6,r6,LAWAR1@l
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stwu r6, 0xc30(r5)
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/* LAWBAR2, LAWAR2 */
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lis r6,LAWBAR2@h
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ori r6,r6,LAWBAR2@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR2@h
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ori r6,r6,LAWAR2@l
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stwu r6, 0x20(r5)
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/* LAWBAR3, LAWAR3 */
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lis r6,LAWBAR3@h
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ori r6,r6,LAWBAR3@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR3@h
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ori r6,r6,LAWAR3@l
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stwu r6, 0x20(r5)
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/* LAWBAR4, LAWAR4 */
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lis r6,LAWBAR4@h
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ori r6,r6,LAWBAR4@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR4@h
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ori r6,r6,LAWAR4@l
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stwu r6, 0x20(r5)
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/* LAWBAR5, LAWAR5 */
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lis r6,LAWBAR5@h
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ori r6,r6,LAWBAR5@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR5@h
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ori r6,r6,LAWAR5@l
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stwu r6, 0x20(r5)
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/* LAWBAR6, LAWAR6 */
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lis r6,LAWBAR6@h
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ori r6,r6,LAWBAR6@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR6@h
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ori r6,r6,LAWAR6@l
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stwu r6, 0x20(r5)
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/* LAWBAR7, LAWAR7 */
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lis r6,LAWBAR7@h
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ori r6,r6,LAWBAR7@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR7@h
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ori r6,r6,LAWAR7@l
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stwu r6, 0x20(r5)
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/* LAWBAR8, LAWAR8 */
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lis r6,LAWBAR8@h
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ori r6,r6,LAWBAR8@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR8@h
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ori r6,r6,LAWAR8@l
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stwu r6, 0x20(r5)
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/* LAWBAR9, LAWAR9 */
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lis r6,LAWBAR9@h
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ori r6,r6,LAWBAR9@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR9@h
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ori r6,r6,LAWAR9@l
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stwu r6, 0x20(r5)
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blr
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@ -0,0 +1,507 @@
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/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define DEBUG
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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#endif
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#include "../common/pixis.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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#include "spd_sdram.h"
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#endif
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void sdram_init(void);
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long int fixed_sdram(void);
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/* called before any console output */
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int board_early_init_f(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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gur->gpiocr |= 0x888a5500; /* DIU16, IR1, UART0, UART2 */
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return 0;
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}
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int checkboard(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *memctl = &immap->im_lbc;
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volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
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puts("Board: MPC8610HPCD\n");
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mcm->abcr |= 0x00010000; /* 0 */
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mcm->hpmr3 = 0x80000008; /* 4c */
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mcm->hpmr0 = 0;
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mcm->hpmr1 = 0;
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mcm->hpmr2 = 0;
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mcm->hpmr4 = 0;
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mcm->hpmr5 = 0;
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return 0;
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}
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long int
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initdram(int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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#if defined(CFG_RAMBOOT)
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puts(" DDR: ");
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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puts("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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puts("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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puts("SDRAM test passed.\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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long int fixed_sdram(void)
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{
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#if !defined(CFG_RAMBOOT)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
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uint d_init;
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ddr->cs0_bnds = 0x0000001f;
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ddr->cs0_config = 0x80010202;
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ddr->ext_refrec = 0x00000000;
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ddr->timing_cfg_0 = 0x00260802;
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ddr->timing_cfg_1 = 0x3935d322;
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ddr->timing_cfg_2 = 0x14904cc8;
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ddr->sdram_mode_1 = 0x00480432;
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ddr->sdram_mode_2 = 0x00000000;
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ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
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ddr->sdram_data_init = 0xDEADBEEF;
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ddr->sdram_clk_cntl = 0x03800000;
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ddr->sdram_cfg_2 = 0x04400010;
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#if defined(CONFIG_DDR_ECC)
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ddr->err_int_en = 0x0000000d;
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ddr->err_disable = 0x00000000;
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ddr->err_sbe = 0x00010000;
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#endif
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
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udelay(1000);
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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return 512 * 1024 * 1024;
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#endif
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return CFG_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_fsl86xxads_config_table[] = {
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
|
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{}
|
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};
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#endif
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static struct pci_controller pci1_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc86xxcts_config_table
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#endif
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};
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#endif /* CONFIG_PCI */
|
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#ifdef CONFIG_PCIE1
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||||
static struct pci_controller pcie1_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
static struct pci_controller pcie2_hose;
|
||||
#endif
|
||||
|
||||
int first_free_busno = 0;
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
uint devdisr = gur->devdisr;
|
||||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||
|
||||
printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
|
||||
devdisr, io_sel, host_agent);
|
||||
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_configured = (io_sel == 1) || (io_sel == 4);
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
|
||||
(host_agent == 5);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
|
||||
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
if (pci->pme_msg_det)
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE1_MEM_BASE,
|
||||
CFG_PCIE1_MEM_PHYS,
|
||||
CFG_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE1_IO_BASE,
|
||||
CFG_PCIE1_IO_PHYS,
|
||||
CFG_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
||||
(int)&pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno = hose->last_busno + 1;
|
||||
printf(" PCI-Express 1 on bus %02x - %02x\n",
|
||||
hose->first_busno, hose->last_busno);
|
||||
|
||||
} else
|
||||
puts(" PCI-Express 1: Disabled\n");
|
||||
}
|
||||
#else
|
||||
puts("PCI-Express 1: Disabled\n");
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie2_hose;
|
||||
|
||||
int pcie_configured = (io_sel == 0) || (io_sel == 4);
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
|
||||
(host_agent == 4);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
|
||||
printf(" PCI-Express 2 connected to slot as %s" \
|
||||
" (base address %x)\n",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
if (pci->pme_msg_det)
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE2_MEM_BASE,
|
||||
CFG_PCIE2_MEM_PHYS,
|
||||
CFG_PCIE2_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE2_IO_BASE,
|
||||
CFG_PCIE2_IO_PHYS,
|
||||
CFG_PCIE2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
||||
(int)&pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno = hose->last_busno + 1;
|
||||
printf(" PCI-Express 2 on bus %02x - %02x\n",
|
||||
hose->first_busno, hose->last_busno);
|
||||
} else
|
||||
puts(" PCI-Express 2: Disabled\n");
|
||||
}
|
||||
#else
|
||||
puts("PCI-Express 2: Disabled\n");
|
||||
#endif /* CONFIG_PCIE2 */
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
|
||||
|
||||
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
|
||||
printf(" PCI connected to PCI slots as %s" \
|
||||
" (base address %x)\n",
|
||||
pci_agent ? "Agent" : "Host",
|
||||
(uint)pci);
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI1_MEM_BASE,
|
||||
CFG_PCI1_MEM_PHYS,
|
||||
CFG_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCI1_IO_BASE,
|
||||
CFG_PCI1_IO_PHYS,
|
||||
CFG_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr,
|
||||
(int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno = hose->last_busno + 1;
|
||||
printf(" PCI on bus %02x - %02x\n",
|
||||
hose->first_busno, hose->last_busno);
|
||||
|
||||
|
||||
} else
|
||||
puts(" PCI: Disabled\n");
|
||||
}
|
||||
#endif /* CONFIG_PCI1 */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
||||
debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* get_board_sys_clk
|
||||
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
|
||||
*/
|
||||
|
||||
unsigned long
|
||||
get_board_sys_clk(ulong dummy)
|
||||
{
|
||||
u8 i, go_bit, rd_clks;
|
||||
ulong val = 0;
|
||||
ulong a;
|
||||
|
||||
a = PIXIS_BASE + PIXIS_SPD;
|
||||
i = in8(a);
|
||||
i &= 0x07;
|
||||
|
||||
switch (i) {
|
||||
case 0:
|
||||
val = 33333000;
|
||||
break;
|
||||
case 1:
|
||||
val = 39999600;
|
||||
break;
|
||||
case 2:
|
||||
val = 49999500;
|
||||
break;
|
||||
case 3:
|
||||
val = 66666000;
|
||||
break;
|
||||
case 4:
|
||||
val = 83332500;
|
||||
break;
|
||||
case 5:
|
||||
val = 99999000;
|
||||
break;
|
||||
case 6:
|
||||
val = 133332000;
|
||||
break;
|
||||
case 7:
|
||||
val = 166665000;
|
||||
break;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc86xx/start.o (.text)
|
||||
board/freescale/mpc8610hpcd/init.o (.bootpg)
|
||||
cpu/mpc86xx/traps.o (.text)
|
||||
cpu/mpc86xx/interrupts.o (.text)
|
||||
cpu/mpc86xx/cpu_init.o (.text)
|
||||
cpu/mpc86xx/cpu.o (.text)
|
||||
cpu/mpc86xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
Loading…
Reference in New Issue