powerpc/85xx: clear out TLB on boot
Instead of just shooting down the entry that covers CCSR, clear out every TLB entry that isn't the one that we're executing out of. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Scott Wood
Andy Fleming
parent
7ac3cc20e0
commit
3ea21536d7
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@ -435,12 +435,11 @@ l2_disabled:
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* Search for the TLB that covers the code we're executing, and shrink it
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* so that it covers only this 4K page. That will ensure that any other
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* TLB we create won't interfere with it. We assume that the TLB exists,
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* which is why we don't check the Valid bit of MAS1.
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* which is why we don't check the Valid bit of MAS1. We also assume
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* it is in TLB1.
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*
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* This is necessary, for example, when booting from the on-chip ROM,
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* which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
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* If we don't shrink this TLB now, then we'll accidentally delete it
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* in "purge_old_ccsr_tlb" below.
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*/
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bl nexti /* Find our address */
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nexti: mflr r1 /* R1 = our PC */
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@ -450,11 +449,15 @@ nexti: mflr r1 /* R1 = our PC */
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msync
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tlbsx 0, r1 /* This must succeed */
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mfspr r14, MAS0 /* Save ESEL for later */
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rlwinm r14, r14, 16, 0xfff
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/* Set the size of the TLB to 4KB */
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mfspr r3, MAS1
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li r2, 0xF00
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andc r3, r3, r2 /* Clear the TSIZE bits */
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ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
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oris r3, r3, MAS1_IPROT@h
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mtspr MAS1, r3
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/*
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@ -488,6 +491,39 @@ nexti: mflr r1 /* R1 = our PC */
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msync
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tlbwe
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/*
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* Clear out any other TLB entries that may exist, to avoid conflicts.
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* Our TLB entry is in r14.
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*/
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li r0, TLBIVAX_ALL | TLBIVAX_TLB0
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tlbivax 0, r0
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tlbsync
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mfspr r4, SPRN_TLB1CFG
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rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
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li r3, 0
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mtspr MAS1, r3
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1: cmpw r3, r14
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
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cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
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cror cr0*4+eq, cr0*4+eq, cr1*4+eq
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#endif
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rlwinm r5, r3, 16, MAS0_ESEL_MSK
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addi r3, r3, 1
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beq 2f /* skip the entry we're executing from */
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oris r5, r5, MAS0_TLBSEL(1)@h
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mtspr MAS0, r5
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isync
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tlbwe
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isync
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msync
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2: cmpw r3, r4
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blt 1b
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/*
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* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
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* location is not where we want it. This typically happens on a 36-bit
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@ -506,41 +542,15 @@ nexti: mflr r1 /* R1 = our PC */
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#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
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#endif
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purge_old_ccsr_tlb:
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lis r8, CONFIG_SYS_CCSRBAR@h
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ori r8, r8, CONFIG_SYS_CCSRBAR@l
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lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
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ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
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/*
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* In a multi-stage boot (e.g. NAND boot), a previous stage may have
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* created a TLB for CCSR, which will interfere with our relocation
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* code. Since we're going to create a new TLB for CCSR anyway,
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* it should be safe to delete this old TLB here. We have to search
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* for it, though.
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*/
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li r1, 0
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mtspr MAS6, r1 /* Search the current address space and PID */
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isync
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msync
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tlbsx 0, r8
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mfspr r1, MAS1
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andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
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beq 1f /* Skip if no TLB found */
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rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
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mtspr MAS1, r1
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isync
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msync
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tlbwe
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1:
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create_ccsr_new_tlb:
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/*
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* Create a TLB for the new location of CCSR. Register R8 is reserved
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* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
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*/
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lis r8, CONFIG_SYS_CCSRBAR@h
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ori r8, r8, CONFIG_SYS_CCSRBAR@l
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lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
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ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
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lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
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ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
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lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
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@ -475,6 +475,10 @@ extern void print_bats(void);
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#define BOOKE_PAGESZ_256GB 14
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#define BOOKE_PAGESZ_1TB 15
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#define TLBIVAX_ALL 4
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#define TLBIVAX_TLB0 0
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#define TLBIVAX_TLB1 8
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#ifdef CONFIG_E500
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#ifndef __ASSEMBLY__
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extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
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@ -515,6 +515,7 @@
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#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
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#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
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#define TLBnCFG_NENTRY_MASK 0x00000fff
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#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
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#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
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#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
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