MIPS: remove broken "tb0229" board

The "tb0229" board has long been unmaintained, and is broken.
Remove it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2011-12-11 21:58:19 +00:00
parent 6bef783310
commit 3f3110d78b
9 changed files with 4 additions and 1726 deletions

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@ -1,47 +0,0 @@
#
# (C) Masami Komiya <mkomiya@sonare.it> 2004
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o flash.o vr4131-pci.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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@ -1,30 +0,0 @@
#
# (C) Masami Komiya <mkomiya@sonare.it> 2004
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# ROM version
CONFIG_SYS_TEXT_BASE = 0xBFC00000
# RAM version
#CONFIG_SYS_TEXT_BASE = 0x80400000

File diff suppressed because it is too large Load Diff

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@ -1,70 +0,0 @@
/*
* Memory sub-system initialization code for TANBAC Evaluation board TB0229.
*
* Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include <config.h>
#include <asm/regdef.h>
.globl lowlevel_init
lowlevel_init:
/* BCUCNTREG1 = 0x0040 */
la t0, 0xaf000000
li t1, 0x0040
sh t1, 0(t0)
/* ROMSIZEREG = 0x3333 */
la t0, 0xaf000004
li t1, 0x3333
sh t1, 0(t0)
/* ROMSPEEDREG = 0x3003 */
la t0, 0xaf000006
li t1, 0x3003
sh t1, 0(t0)
/* BCUCNTREG3 = 0 */
la t0, 0xaf000016
li t1, 0x0000
sh t1, 0(t0)
/* CMUCLKMSK */
la t0, 0xaf000060
li t1, 0x39a2
sh t1, 0(t0)
/* PMUCNTREG */
la t0, 0xaf0000c2
li t1, 0x0006
sh t1, 0(t0)
/* SDRAMMODEREG = 0x8029 */
la t0, 0xaf000400
li t1, 0x8029
sh t1, 0(t0)
/* SDRAMCNTREG = 0x2322 */
la t0, 0xaf000402
li t1, 0x2322
sh t1, 0(t0)
/* BCURFCNTREG = 0x0106 */
la t0, 0xaf000404
li t1, 0x0106
sh t1, 0(t0)
/* RAMSZEREG = 0x5555 (64MB Bank) */
la t0, 0xaf000408
li t1, 0x5555
sh t1, 0(t0)
j ra
nop

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@ -1,54 +0,0 @@
/*
* Board initialize code for TANBAC Evaluation board TB0229.
*
* (C) Masami Komiya <mkomiya@sonare.it> 2004
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <pci.h>
void _machine_restart(void)
{
void (*f)(void) = (void *) 0xbfc00000;
f();
}
#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board (void)
{
init_vr4131_pci(&hose);
}
#endif
phys_size_t initdram(int board_type)
{
return get_ram_size (CONFIG_SYS_SDRAM_BASE, 0x8000000);
}
int checkboard (void)
{
printf("Board: TANBAC TB0229 ");
printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
set_io_port_base(0);
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}

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@ -1,70 +0,0 @@
/*
* (C) Masami Komiya <mkomiya@sonare.it> 2004
*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data*) }
. = .;
_gp = ALIGN(16) + 0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
.sdata : { *(.sdata*) }
.u_boot_cmd : {
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .;
}

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@ -1,254 +0,0 @@
/*
* VR4131 PCIU support code for TANBAC Evaluation board TB0229.
*
* (C) Masami Komiya <mkomiya@sonare.it> 2004
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
#include <common.h>
#include <pci.h>
#include <asm/addrspace.h>
#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00)
#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04)
#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08)
#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10)
#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14)
#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18)
#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24)
#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28)
#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30)
#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34)
#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38)
#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60)
#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10)
#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14)
#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18)
/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */
/*#define VR4122_PCI_HOST_BASE 0xa0000000 */
volatile unsigned int *pciconfigaddr;
volatile unsigned int *pciconfigdata;
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
/*
* Access PCI Configuration Register for VR4131
*/
static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
u32 * data)
{
u32 bus;
u32 device;
bus = ((dev & 0xff0000) >> 16);
device = ((dev & 0xf800) >> 11);
if (bus == 0) {
/* Type 0 Configuration */
*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
} else {
/* Type 1 Configuration */
*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
}
if (access_type == PCI_ACCESS_WRITE) {
*VR4131_PCICONFDREG = *data;
} else {
*data = *VR4131_PCICONFDREG;
}
return (0);
}
static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
{
u32 data;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = (data >> ((reg & 3) << 3)) & 0xff;
return 0;
}
static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
{
u32 data;
if (reg & 1)
return -1;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = (data >> ((reg & 3) << 3)) & 0xffff;
return 0;
}
static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
u32 * val)
{
u32 data = 0;
if (reg & 3)
return -1;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = data;
return (0);
}
static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
{
u32 data = 0;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
((reg & 3) << 3));
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return 0;
}
static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
{
u32 data = 0;
if (reg & 1)
return -1;
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
return -1;
data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
((reg & 3) << 3));
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return 0;
}
static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
{
u32 data;
if (reg & 3) {
return -1;
}
data = val;
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return (0);
}
/*
* Initialize VR4131 PCIU
*/
static void vr4131_pciu_init(void)
{
/* PCI clock */
*VR4131_PCICLKSELREG = 0x00000002;
/* PCI memory and I/O space */
*VR4131_PCIMMAW1REG = 0x100F9010;
*VR4131_PCIMMAW2REG = 0x140FD014;
*VR4131_PCIMIOAWREG = 0x160FD000;
/* Target memory window */
*VR4131_PCITAW1REG = 0x00081000; /* 64MB */
*VR4131_PCITAW2REG = 0x00000000;
*VR4131_MAILBAREG = 0UL;
*VR4131_PCIMBA1REG = 0UL;
*VR4131_PCITRDYREG = 0x00008004;
*VR4131_PCIENREG = 0x00000004; /* PCI enable */
*VR4131_COMMANDREG = 0x02000007;
}
/*
* Initialize Module
*/
void init_vr4131_pci (struct pci_controller *hose)
{
hose->first_busno = 0;
hose->last_busno = 0xff;
vr4131_pciu_init (); /* Initialize VR4131 PCIU */
/* PCI memory space #1 */
pci_set_region (hose->regions + 0,
0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
/* PCI memory space #2 */
pci_set_region (hose->regions + 1,
0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (hose->regions + 2,
0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
/* System memory space */
pci_set_region (hose->regions + 3,
0x00000000,
0x80000000,
0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
hose->read_byte = vr4131_pci_read_config_byte;
hose->read_word = vr4131_pci_read_config_word;
hose->read_dword = vr4131_pci_read_config_dword;
hose->write_byte = vr4131_pci_write_config_byte;
hose->write_word = vr4131_pci_write_config_word;
hose->write_dword = vr4131_pci_write_config_dword;
pci_register_hose (hose);
hose->last_busno = pci_hose_scan (hose);
return;
}

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@ -331,7 +331,6 @@ M5485GFE m68k mcf547x_8x m548xevb freescale -
M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mips mips mips32 qemu-mips - - qemu-mips
tb0229 mips mips32
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND

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@ -11,9 +11,10 @@ easily if here is something they might want to dig for...
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
rmu powerpc MPC850 - 2011-12-07 Wolfgang Denk <wd@denx.de>
OXC powerpc MPC8240 - 2011-12-07
BAB7xx powerpc MPC740/MPC750 - 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
tb0229 mips mips32 - 2011-12-12
rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de>
OXC powerpc MPC8240 309a292 2011-12-07
BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
xm250 arm pxa c746cdd 2011-25-11
pleb2 arm pxa b185a1c 2011-25-11
cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris <kharris@nexus-tech.net>