x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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@ -28,6 +28,8 @@
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#include <asm/cpu.h>
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#include <asm/cpu.h>
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#include <asm/lapic.h>
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#include <asm/lapic.h>
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#include <asm/mp.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/processor-flags.h>
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@ -352,6 +354,26 @@ int x86_cpu_init_f(void)
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gd->arch.has_mtrr = has_mtrr();
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gd->arch.has_mtrr = has_mtrr();
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}
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}
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/* Configure fixed range MTRRs for some legacy regions */
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if (gd->arch.has_mtrr) {
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u64 mtrr_cap;
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mtrr_cap = native_read_msr(MTRR_CAP_MSR);
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if (mtrr_cap & MTRR_CAP_FIX) {
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/* Mark the VGA RAM area as uncacheable */
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native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
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/* Mark the PCI ROM area as uncacheable */
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native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
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native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
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native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
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native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
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/* Enable the fixed range MTRRs */
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msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
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}
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}
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return 0;
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return 0;
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}
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}
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@ -21,6 +21,11 @@
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#define MTRR_CAP_MSR 0x0fe
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#define MTRR_CAP_MSR 0x0fe
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#define MTRR_DEF_TYPE_MSR 0x2ff
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#define MTRR_DEF_TYPE_MSR 0x2ff
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#define MTRR_CAP_SMRR (1 << 11)
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#define MTRR_CAP_WC (1 << 10)
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#define MTRR_CAP_FIX (1 << 8)
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#define MTRR_CAP_VCNT_MASK 0xff
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#define MTRR_DEF_TYPE_EN (1 << 11)
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#define MTRR_DEF_TYPE_EN (1 << 11)
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#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
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#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
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