net: phy: bugfixes: mv88E61xx multichip addressing support
With these fixes, this driver works properly for multi chip addressging mode Bugfixes: 1. Build error fixed for function mv88e61xx_busychk_multic-fixed 2. PHY dev address error detection- fixed 3. wrong busy bit was refered in function mv88e61xx_busychk -fixed 4. invalid data read ptr was refered for RD_PHY in case of multichip addressing mode -fixed The Multichip Address mode is tested with RD6281A board having MV88E6165 switch on it Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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@ -36,7 +36,7 @@
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* By default single chip mode is configured
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* By default single chip mode is configured
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* multichip mode operation can be configured in board header
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* multichip mode operation can be configured in board header
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*/
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*/
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static int mv88e61xx_busychk_multic(u32 devaddr)
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static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
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{
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{
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u32 reg = 0;
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u32 reg = 0;
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u32 timeout = MV88E61XX_PHY_TIMEOUT;
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u32 timeout = MV88E61XX_PHY_TIMEOUT;
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@ -58,11 +58,11 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
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u32 mii_dev_addr;
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u32 mii_dev_addr;
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/* command to read PHY dev address */
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/* command to read PHY dev address */
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if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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printf("Error..could not read PHY dev address\n");
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printf("Error..could not read PHY dev address\n");
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return;
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return;
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}
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}
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mv88e61xx_busychk_multic(mii_dev_addr);
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Write data to Switch indirect data register */
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/* Write data to Switch indirect data register */
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miiphy_write(name, mii_dev_addr, 0x1, data);
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miiphy_write(name, mii_dev_addr, 0x1, data);
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/* Write command to Switch indirect command register (write) */
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/* Write command to Switch indirect command register (write) */
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@ -77,18 +77,18 @@ static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
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u32 mii_dev_addr;
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u32 mii_dev_addr;
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/* command to read PHY dev address */
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/* command to read PHY dev address */
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if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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printf("Error..could not read PHY dev address\n");
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printf("Error..could not read PHY dev address\n");
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return;
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return;
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}
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}
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mv88e61xx_busychk_multic(mii_dev_addr);
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Write command to Switch indirect command register (read) */
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/* Write command to Switch indirect command register (read) */
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miiphy_write(name, mii_dev_addr, 0x0,
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miiphy_write(name, mii_dev_addr, 0x0,
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reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
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reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
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15));
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15));
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mv88e61xx_busychk_multic(mii_dev_addr);
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Read data from Switch indirect data register */
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/* Read data from Switch indirect data register */
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miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data);
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miiphy_read(name, mii_dev_addr, 0x1, data);
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}
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}
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#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
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#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
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@ -212,7 +212,7 @@ static int mv88e61xx_busychk(char *name)
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printf("SMI busy timeout\n");
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printf("SMI busy timeout\n");
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return -1;
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return -1;
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}
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}
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} while (reg & 1 << 28); /* busy mask */
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} while (reg & 1 << 15); /* busy mask */
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return 0;
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return 0;
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}
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}
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@ -49,7 +49,7 @@
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#define MV88E61XX_ADDR_OFST 5
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#define MV88E61XX_ADDR_OFST 5
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#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
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#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
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static int mv88e61xx_busychk_multic(u32 devaddr);
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static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
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static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
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static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
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static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
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static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
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#define WR_PHY mv88e61xx_wr_phy
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#define WR_PHY mv88e61xx_wr_phy
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