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arm: socfpga: clock: Clean up bit definitions 

Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Marek Vasut 2014-09-16 17:21:00 +02:00
parent 5d8ad0cd3a
commit 44428ab6ab
3 changed files with 294 additions and 274 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

118
arch/arm/cpu/armv7/socfpga/clock_manager.c
View File

@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base = static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
#define CLKMGR_BYPASS_ENABLE 1
#define CLKMGR_BYPASS_DISABLE 0
#define CLKMGR_STAT_IDLE 0
#define CLKMGR_STAT_BUSY 1
#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
#define CLEAR_BGP_EN_PWRDN \
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
#define VCO_EN_BASE \
(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
static void cm_wait_for_lock(uint32_t mask) static void cm_wait_for_lock(uint32_t mask)
{ {
register uint32_t inter_val; register uint32_t inter_val;
@ -130,14 +111,8 @@ void cm_basic_init(const cm_config_t *cfg)
writel(0, &clock_manager_base->per_pll.en); writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */ /* Put all plls in bypass */
cm_write_bypass( cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
CLKMGR_BYPASS_PERPLLSRC_SET( CLKMGR_BYPASS_MAINPLL);
CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_SDRPLLSRC_SET(
CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
/* /*
* Put all plls VCO registers back to reset value. * Put all plls VCO registers back to reset value.
@ -172,19 +147,14 @@ void cm_basic_init(const cm_config_t *cfg)
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator. * with numerator and denominator.
*/ */
writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->main_pll.vco);
&clock_manager_base->main_pll.vco);
writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->per_pll.vco);
&clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | &clock_manager_base->sdr_pll.vco);
cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll.vco);
/* /*
* Time starts here * Time starts here
@ -234,18 +204,16 @@ void cm_basic_init(const cm_config_t *cfg)
/* Enable vco */ /* Enable vco */
/* main pll vco */ /* main pll vco */
writel(cfg->main_vco_base | VCO_EN_BASE, writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->main_pll.vco); &clock_manager_base->main_pll.vco);
/* periferal pll */ /* periferal pll */
writel(cfg->peri_vco_base | VCO_EN_BASE, writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
&clock_manager_base->per_pll.vco); &clock_manager_base->per_pll.vco);
/* sdram pll vco */ /* sdram pll vco */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | &clock_manager_base->sdr_pll.vco);
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */ /* L3 MP and L3 SP */
writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
@ -296,8 +264,8 @@ void cm_basic_init(const cm_config_t *cfg)
&clock_manager_base->per_pll.vco); &clock_manager_base->per_pll.vco);
/* assert sdram outresetall */ /* assert sdram outresetall */
writel(cfg->sdram_vco_base | VCO_EN_BASE| writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
&clock_manager_base->sdr_pll.vco); &clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */ /* deassert main outresetall */
@ -309,9 +277,8 @@ void cm_basic_init(const cm_config_t *cfg)
&clock_manager_base->per_pll.vco); &clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */ /* deassert sdram outresetall */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
cfg->sdram_vco_base | VCO_EN_BASE, &clock_manager_base->sdr_pll.vco);
&clock_manager_base->sdr_pll.vco);
/* /*
* now that we've toggled outreset all, all the clocks * now that we've toggled outreset all, all the clocks
@ -335,18 +302,10 @@ void cm_basic_init(const cm_config_t *cfg)
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */ /* Take all three PLLs out of bypass when safe mode is cleared. */
cm_write_bypass( cm_write_bypass(0);
CLKMGR_BYPASS_PERPLLSRC_SET(
CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_SDRPLLSRC_SET(
CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
/* clear safe mode */ /* clear safe mode */
cm_write_ctrl(readl(&clock_manager_base->ctrl) | cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
/* /*
* now that safe mode is clear with clocks gated * now that safe mode is clear with clocks gated
@ -367,9 +326,11 @@ static unsigned int cm_get_main_vco_clk_hz(void)
/* get the main VCO clock */ /* get the main VCO clock */
reg = readl(&clock_manager_base->main_pll.vco); reg = readl(&clock_manager_base->main_pll.vco);
clock = CONFIG_HPS_CLK_OSC1_HZ / clock = CONFIG_HPS_CLK_OSC1_HZ;
(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock; return clock;
} }
@ -380,7 +341,8 @@ static unsigned int cm_get_per_vco_clk_hz(void)
/* identify PER PLL clock source */ /* identify PER PLL clock source */
reg = readl(&clock_manager_base->per_pll.vco); reg = readl(&clock_manager_base->per_pll.vco);
reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1) if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ; clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2) else if (reg == CLKMGR_VCO_SSRC_EOSC2)
@ -390,8 +352,10 @@ static unsigned int cm_get_per_vco_clk_hz(void)
/* get the PER VCO clock */ /* get the PER VCO clock */
reg = readl(&clock_manager_base->per_pll.vco); reg = readl(&clock_manager_base->per_pll.vco);
clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
return clock; return clock;
} }
@ -416,7 +380,8 @@ unsigned long cm_get_sdram_clk_hz(void)
/* identify SDRAM PLL clock source */ /* identify SDRAM PLL clock source */
reg = readl(&clock_manager_base->sdr_pll.vco); reg = readl(&clock_manager_base->sdr_pll.vco);
reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg); reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1) if (reg == CLKMGR_VCO_SSRC_EOSC1)
clock = CONFIG_HPS_CLK_OSC1_HZ; clock = CONFIG_HPS_CLK_OSC1_HZ;
else if (reg == CLKMGR_VCO_SSRC_EOSC2) else if (reg == CLKMGR_VCO_SSRC_EOSC2)
@ -426,12 +391,15 @@ unsigned long cm_get_sdram_clk_hz(void)
/* get the SDRAM VCO clock */ /* get the SDRAM VCO clock */
reg = readl(&clock_manager_base->sdr_pll.vco); reg = readl(&clock_manager_base->sdr_pll.vco);
clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1); clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1); CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
/* get the SDRAM (DDR_DQS) clock */ /* get the SDRAM (DDR_DQS) clock */
reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg); reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
clock /= (reg + 1); clock /= (reg + 1);
return clock; return clock;
@ -443,7 +411,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
/* identify the source of L4 SP clock */ /* identify the source of L4 SP clock */
reg = readl(&clock_manager_base->main_pll.l4src); reg = readl(&clock_manager_base->main_pll.l4src);
reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
clock = cm_get_main_vco_clk_hz(); clock = cm_get_main_vco_clk_hz();
@ -463,7 +432,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
/* get the L4 SP clock which supplied to UART */ /* get the L4 SP clock which supplied to UART */
reg = readl(&clock_manager_base->main_pll.maindiv); reg = readl(&clock_manager_base->main_pll.maindiv);
reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg); reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
clock = clock / (1 << reg); clock = clock / (1 << reg);
return clock; return clock;
@ -475,7 +445,8 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
/* identify the source of MMC clock */ /* identify the source of MMC clock */
reg = readl(&clock_manager_base->per_pll.src); reg = readl(&clock_manager_base->per_pll.src);
reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg); reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
@ -504,7 +475,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
/* identify the source of QSPI clock */ /* identify the source of QSPI clock */
reg = readl(&clock_manager_base->per_pll.src); reg = readl(&clock_manager_base->per_pll.src);
reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg); reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;

174
arch/arm/cpu/armv7/socfpga/spl.c
View File

@ -19,6 +19,31 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define MAIN_VCO_BASE ( \
(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
)
#define PERI_VCO_BASE ( \
(CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
(CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
)
#define SDR_VCO_BASE ( \
(CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
(CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
(CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
)
u32 spl_boot_device(void) u32 spl_boot_device(void)
{ {
return BOOT_DEVICE_RAM; return BOOT_DEVICE_RAM;
@ -33,86 +58,87 @@ void spl_board_init(void)
cm_config_t cm_default_cfg = { cm_config_t cm_default_cfg = {
/* main group */ /* main group */
MAIN_VCO_BASE, MAIN_VCO_BASE,
CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET( (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT), CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET( (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT), CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET( (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT), CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET( (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT), CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT), CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET( (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT), CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET( (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) | CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET( (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) | CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET( (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) | CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET( (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK), CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET( (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) | CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET( (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK), CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET( (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK), CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET( (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) | CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET( (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP), CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */ /* peripheral group */
PERI_VCO_BASE, PERI_VCO_BASE,
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET( (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT), CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET( (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT), CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET( (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT), CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT), CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET( (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT), CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET( (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT), CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
CLKMGR_PERPLLGRP_DIV_USBCLK_SET( (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
CONFIG_HPS_PERPLLGRP_DIV_USBCLK) | CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET( (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) | CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET( (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) | CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET( (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK), CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET( (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK), CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
CLKMGR_PERPLLGRP_SRC_QSPI_SET( (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
CONFIG_HPS_PERPLLGRP_SRC_QSPI) | CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
CLKMGR_PERPLLGRP_SRC_NAND_SET( (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
CONFIG_HPS_PERPLLGRP_SRC_NAND) | CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
CLKMGR_PERPLLGRP_SRC_SDMMC_SET( (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
CONFIG_HPS_PERPLLGRP_SRC_SDMMC), CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */ /* sdram pll group */
SDR_VCO_BASE, SDR_VCO_BASE,
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET( (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) | CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET( (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT), CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET( (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) | CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET( (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT), CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET( (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) | CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET( (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT), CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET( (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) | CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET( (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT), CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
}; };
debug("Freezing all I/O banks\n"); debug("Freezing all I/O banks\n");

276
arch/arm/include/asm/arch-socfpga/clock_manager.h
View File

@ -118,165 +118,187 @@ struct socfpga_clock_manager {
u32 _pad_0xe8_0x200[70]; u32 _pad_0xe8_0x200[70];
}; };
#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 #define CLKMGR_CTRL_SAFEMODE (1 << 0)
#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) #define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) #define CLKMGR_BYPASS_PERPLL (1 << 3)
#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) #define CLKMGR_BYPASS_PERPLL_OFFSET 3
#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) #define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
#define CLKMGR_BYPASS_SDRPLL (1 << 1)
#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
#define CLKMGR_BYPASS_MAINPLL (1 << 0)
#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
#define CLKMGR_STAT_BUSY (1 << 0)
/* Main PLL */ /* Main PLL */
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d #define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7) #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) #define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1) #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) #define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
/* Per PLL */ /* Per PLL */
#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_VCO_SSRC_EOSC1 0x0 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
#define CLKMGR_VCO_SSRC_EOSC2 0x1 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
#define CLKMGR_VCO_SSRC_F2S 0x2
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_VCO_SSRC_EOSC1 0x0
#define CLKMGR_VCO_SSRC_EOSC2 0x1
#define CLKMGR_VCO_SSRC_F2S 0x2
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4) #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0) #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
#define CLKMGR_QSPI_CLK_SRC_PER 0x2 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
#define CLKMGR_QSPI_CLK_SRC_PER 0x2
/* SDR PLL */ /* SDR PLL */
#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0) #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
#define MAIN_VCO_BASE \
(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
#define PERI_VCO_BASE \
(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
#define SDR_VCO_BASE \
(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
#endif /* _CLOCK_MANAGER_H_ */ #endif /* _CLOCK_MANAGER_H_ */