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use correct at91rm9200 register name 

This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2.  This
makes code use the register name from chip datasheets.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2008-01-18 12:55:00 -08:00 committed by Jean-Christophe PLAGNIOL-VILLARD
parent a3543d6dc5
commit 480ed1dea1
5 changed files with 7 additions and 7 deletions
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6
cpu/arm920t/at91rm9200/lowlevel_init.S
View File

@ -46,7 +46,7 @@
#define MC_ASR 0xFFFFFF04
#define MC_AASR 0xFFFFFF08
#define EBI_CFGR 0xFFFFFF64
#define SMC2_CSR 0xFFFFFF70
#define SMC_CSR0 0xFFFFFF70
/* clocks */
#define PLLAR 0xFFFFFC28
@ -146,8 +146,8 @@ SMRDATA:
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
.word SMC2_CSR
.word SMC2_CSR_VAL
.word SMC_CSR0
.word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR

2
include/configs/at91rm9200dk.h
View File

@ -51,7 +51,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */

2
include/configs/cmc_pu2.h
View File

@ -50,7 +50,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */

2
include/configs/csb637.h
View File

@ -51,7 +51,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */

2
include/configs/mp2usb.h
View File

@ -55,7 +55,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */