Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
48b3ed217f
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@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
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obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
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obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
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obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
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obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
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obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
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obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
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@ -53,6 +53,7 @@ static const struct {
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{ 0x40, "R8A7740" },
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{ 0x45, "R8A7790" },
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{ 0x47, "R8A7791" },
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{ 0x4C, "R8A7794" },
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{ 0x0, "CPU" },
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};
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File diff suppressed because it is too large
Load Diff
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@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
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#elif defined(CONFIG_R8A7791)
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#include "r8a7791-gpio.h"
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void r8a7791_pinmux_init(void);
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#elif defined(CONFIG_R8A7794)
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#include "r8a7794-gpio.h"
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void r8a7794_pinmux_init(void);
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#endif
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#endif /* __ASM_ARCH_GPIO_H */
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@ -0,0 +1,176 @@
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#ifndef __ASM_R8A7794_H__
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#define __ASM_R8A7794_H__
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/* Pin Function Controller:
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* GPIO_FN_xx - GPIO used to select pin function
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* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
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*/
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enum {
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GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
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GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
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GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
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GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
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GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
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GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
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GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
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GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
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GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
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GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
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GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
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GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
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GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
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GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
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GPIO_GP_1_24, GPIO_GP_1_25,
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GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
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GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
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GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
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GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
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GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
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GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
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GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
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GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
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GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
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GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
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GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
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GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
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GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
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GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
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GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
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GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
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GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
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GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
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GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
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GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
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GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
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GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
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GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
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GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
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GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
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GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
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GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
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GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
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GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
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GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
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GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
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GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
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GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
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GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
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GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
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GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
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GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
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GPIO_GP_6_24, GPIO_GP_6_25,
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GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0,
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GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
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GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD,
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GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2,
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GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP,
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GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
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GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
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/*
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* From IPSR0 to IPSR5 have been removed because they does not use.
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*/
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/* IPSR6 */
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GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28,
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GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
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GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA,
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GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB,
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GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK,
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GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1,
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GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1,
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GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4,
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GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4,
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GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7,
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GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL,
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GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7,
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GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C,
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GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N,
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GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C,
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GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B,
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GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN,
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GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B,
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GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI,
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/* IPSR7 */
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GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B,
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GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO,
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GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B,
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GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK,
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GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B,
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GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N,
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GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B,
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GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1,
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GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B,
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GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2,
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GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C,
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GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7,
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GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6,
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GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0,
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GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7,
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GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1,
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GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B,
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GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B,
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GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B,
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GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD,
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/* IPSR8 */
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GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B,
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GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B,
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GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C,
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GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B,
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GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C,
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GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B,
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GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D,
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GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B,
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GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D,
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GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B,
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GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS,
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GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C,
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GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D,
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GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0,
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GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL,
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GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B,
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GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA,
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GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B,
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GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD,
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GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
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GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
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/*
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* From IPSR9 to IPSR10 have been removed because they does not use.
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*/
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/* IPSR11 */
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GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
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GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
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||||
GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1,
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GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B,
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||||
GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6,
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GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
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GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B,
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GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
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GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B,
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||||
GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78,
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||||
GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE,
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||||
GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8,
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||||
GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N,
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||||
GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D,
|
||||
GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129,
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||||
GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B,
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||||
GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
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||||
GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
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||||
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||||
/*
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||||
* From IPSR12 to IPSR13 have been removed because they does not use.
|
||||
*/
|
||||
};
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||||
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||||
#endif /* __ASM_R8A7794_H__ */
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||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
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||||
* arch/arm/include/asm/arch-rmobile/r8a7794.h
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_R8A7794_H
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||||
#define __ASM_ARCH_R8A7794_H
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||||
#include "rcar-base.h"
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||||
|
||||
#endif /* __ASM_ARCH_R8A7794_H */
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||||
|
|
@ -10,7 +10,7 @@
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|||
#define __ASM_ARCH_RCAR_BASE_H
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||||
|
||||
/*
|
||||
* R-Car (R8A7790/R8A7791) I/O Addresses
|
||||
* R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
|
||||
*/
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||||
#define RWDT_BASE 0xE6020000
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||||
#define SWDT_BASE 0xE6030000
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||||
|
|
@ -116,7 +116,7 @@
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|||
#define SYS_AXI_SAT1_BASE 0xFF8009C0
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||||
#define SYS_AXI_SDM0_BASE 0xFF800A00
|
||||
#define SYS_AXI_SDM1_BASE 0xFF800A40
|
||||
#define SYS_AXI_TRAB_BASE 0xFF800B00
|
||||
#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
|
||||
#define SYS_AXI_UDM0_BASE 0xFF800B80
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||||
#define SYS_AXI_UDM1_BASE 0xFF800BC0
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
#include <asm/arch/r8a7790.h>
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||||
#elif defined(CONFIG_R8A7791)
|
||||
#include <asm/arch/r8a7791.h>
|
||||
#elif defined(CONFIG_R8A7794)
|
||||
#include <asm/arch/r8a7794.h>
|
||||
#else
|
||||
#error "SOC Name not defined"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# board/renesas/alt/Makefile
|
||||
#
|
||||
# Copyright (C) 2014 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
obj-y := alt.o qos.o
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* board/renesas/alt/alt.c
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <netdev.h>
|
||||
#include <miiphy.h>
|
||||
#include <i2c.h>
|
||||
#include <div64.h>
|
||||
#include "qos.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define CLK2MHZ(clk) (clk / 1000 / 1000)
|
||||
void s_init(void)
|
||||
{
|
||||
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
|
||||
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
|
||||
|
||||
/* Watchdog init */
|
||||
writel(0xA5A5A500, &rwdt->rwtcsra);
|
||||
writel(0xA5A5A500, &swdt->swtcsra);
|
||||
|
||||
/* QoS */
|
||||
qos_init();
|
||||
}
|
||||
|
||||
#define MSTPSR1 0xE6150038
|
||||
#define SMSTPCR1 0xE6150134
|
||||
#define TMU0_MSTP125 (1 << 25)
|
||||
|
||||
#define MSTPSR7 0xE61501C4
|
||||
#define SMSTPCR7 0xE615014C
|
||||
#define SCIF0_MSTP719 (1 << 19)
|
||||
|
||||
#define MSTPSR8 0xE61509A0
|
||||
#define SMSTPCR8 0xE6150990
|
||||
#define ETHER_MSTP813 (1 << 13)
|
||||
|
||||
#define mstp_setbits(type, addr, saddr, set) \
|
||||
out_##type((saddr), in_##type(addr) | (set))
|
||||
#define mstp_clrbits(type, addr, saddr, clear) \
|
||||
out_##type((saddr), in_##type(addr) & ~(clear))
|
||||
#define mstp_setbits_le32(addr, saddr, set) \
|
||||
mstp_setbits(le32, addr, saddr, set)
|
||||
#define mstp_clrbits_le32(addr, saddr, clear) \
|
||||
mstp_clrbits(le32, addr, saddr, clear)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* TMU */
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
|
||||
/* SCIF0 */
|
||||
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
|
||||
|
||||
/* ETHER */
|
||||
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_preboot_os(void)
|
||||
{
|
||||
/* Disable TMU0 */
|
||||
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
|
||||
|
||||
/* Init PFC controller */
|
||||
r8a7794_pinmux_init();
|
||||
|
||||
/* Ether Enable */
|
||||
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RXD0, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RXD1, NULL);
|
||||
gpio_request(GPIO_FN_ETH_LINK, NULL);
|
||||
gpio_request(GPIO_FN_ETH_REFCLK, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MDIO, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TXD1, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TXD0, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MDC, NULL);
|
||||
gpio_request(GPIO_FN_IRQ8, NULL);
|
||||
|
||||
/* PHY reset */
|
||||
gpio_request(GPIO_GP_1_24, NULL);
|
||||
gpio_direction_output(GPIO_GP_1_24, 0);
|
||||
mdelay(20);
|
||||
gpio_set_value(GPIO_GP_1_24, 1);
|
||||
udelay(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CXR24 0xEE7003C0 /* MAC address high register */
|
||||
#define CXR25 0xEE7003C8 /* MAC address low register */
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_SH_ETHER
|
||||
int ret = -ENODEV;
|
||||
u32 val;
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
ret = sh_eth_initialize(bis);
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
|
||||
return ret;
|
||||
|
||||
/* Set Mac address */
|
||||
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
|
||||
enetaddr[2] << 8 | enetaddr[3];
|
||||
writel(val, CXR24);
|
||||
|
||||
val = enetaddr[4] << 8 | enetaddr[5];
|
||||
writel(val, CXR25);
|
||||
|
||||
return ret;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct rmobile_sysinfo sysinfo = {
|
||||
CONFIG_RMOBILE_BOARD_STRING
|
||||
};
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
|
||||
gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
u8 val;
|
||||
|
||||
i2c_set_bus_num(1); /* PowerIC connected to ch3 */
|
||||
i2c_init(400000, 0);
|
||||
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
|
||||
val |= 0x02;
|
||||
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
|
||||
}
|
||||
|
|
@ -0,0 +1,944 @@
|
|||
/*
|
||||
* board/renesas/alt/qos.c
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
/* QoS version 0.10 */
|
||||
|
||||
enum {
|
||||
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
||||
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
|
||||
DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
|
||||
DBSC3_15,
|
||||
DBSC3_NR,
|
||||
};
|
||||
|
||||
static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
|
||||
[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
|
||||
[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
|
||||
[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
|
||||
[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
|
||||
[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
|
||||
[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
|
||||
[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
|
||||
[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
|
||||
[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
|
||||
[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
|
||||
[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
|
||||
[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
|
||||
[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
|
||||
[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
|
||||
[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
|
||||
[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
|
||||
};
|
||||
|
||||
static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
|
||||
[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
|
||||
[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
|
||||
[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
|
||||
[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
|
||||
[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
|
||||
[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
|
||||
[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
|
||||
[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
|
||||
[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
|
||||
[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
|
||||
[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
|
||||
[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
|
||||
[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
|
||||
[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
|
||||
[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
|
||||
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
|
||||
};
|
||||
|
||||
void qos_init(void)
|
||||
{
|
||||
int i;
|
||||
struct rcar_s3c *s3c;
|
||||
struct rcar_s3c_qos *s3c_qos;
|
||||
struct rcar_dbsc3_qos *qos_addr;
|
||||
struct rcar_mxi *mxi;
|
||||
struct rcar_mxi_qos *mxi_qos;
|
||||
struct rcar_axi_qos *axi_qos;
|
||||
|
||||
/* DBSC DBADJ2 */
|
||||
writel(0x20042004, DBSC3_0_DBADJ2);
|
||||
|
||||
/* S3C -QoS */
|
||||
s3c = (struct rcar_s3c *)S3C_BASE;
|
||||
writel(0x1F0D0B0A, &s3c->s3crorr);
|
||||
writel(0x1F0D0B09, &s3c->s3cworr);
|
||||
|
||||
/* QoS Control Registers */
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
||||
writel(0x80928092, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20DC, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960020, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA20DC, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960020, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
/* DBSC -QoS */
|
||||
/* DBSC0 - Read */
|
||||
for (i = DBSC3_00; i < DBSC3_NR; i++) {
|
||||
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
|
||||
writel(0x00000002, &qos_addr->dblgcnt);
|
||||
writel(0x0000207D, &qos_addr->dbtmval0);
|
||||
writel(0x00002053, &qos_addr->dbtmval1);
|
||||
writel(0x0000202A, &qos_addr->dbtmval2);
|
||||
writel(0x00001FBD, &qos_addr->dbtmval3);
|
||||
writel(0x00000001, &qos_addr->dbrqctr);
|
||||
writel(0x00002064, &qos_addr->dbthres0);
|
||||
writel(0x0000203E, &qos_addr->dbthres1);
|
||||
writel(0x00002019, &qos_addr->dbthres2);
|
||||
writel(0x00000001, &qos_addr->dblgqon);
|
||||
}
|
||||
|
||||
/* DBSC0 - Write */
|
||||
for (i = DBSC3_00; i < DBSC3_NR; i++) {
|
||||
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
|
||||
writel(0x00000002, &qos_addr->dblgcnt);
|
||||
writel(0x0000207D, &qos_addr->dbtmval0);
|
||||
writel(0x00002053, &qos_addr->dbtmval1);
|
||||
writel(0x00002043, &qos_addr->dbtmval2);
|
||||
writel(0x00002030, &qos_addr->dbtmval3);
|
||||
writel(0x00000001, &qos_addr->dbrqctr);
|
||||
writel(0x00002064, &qos_addr->dbthres0);
|
||||
writel(0x0000203E, &qos_addr->dbthres1);
|
||||
writel(0x00002031, &qos_addr->dbthres2);
|
||||
writel(0x00000001, &qos_addr->dblgqon);
|
||||
}
|
||||
|
||||
/* CCI-400 -QoS */
|
||||
writel(0x20001000, CCI_400_MAXOT_1);
|
||||
writel(0x20001000, CCI_400_MAXOT_2);
|
||||
writel(0x0000000C, CCI_400_QOSCNTL_1);
|
||||
writel(0x0000000C, CCI_400_QOSCNTL_2);
|
||||
|
||||
/* MXI -QoS */
|
||||
/* Transaction Control (MXI) */
|
||||
mxi = (struct rcar_mxi *)MXI_BASE;
|
||||
writel(0x00000013, &mxi->mxrtcr);
|
||||
writel(0x00000013, &mxi->mxwtcr);
|
||||
writel(0x00780080, &mxi->mxsaar0);
|
||||
writel(0x02000800, &mxi->mxsaar1);
|
||||
|
||||
/* QoS Control (MXI) */
|
||||
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
|
||||
writel(0x0000000C, &mxi_qos->vspdu0);
|
||||
writel(0x0000000E, &mxi_qos->du0);
|
||||
|
||||
/* AXI -QoS */
|
||||
/* Transaction Control (MXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002029, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (RT-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (MP-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002037, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002014, &axi_qos->qosctset0);
|
||||
writel(0x00000040, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002014, &axi_qos->qosctset0);
|
||||
writel(0x00000040, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00001FF0, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00002001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000206E, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (SYS-AXI256) */
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (CCI-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (Media-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020DC, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x000020AA, &axi_qos->qosthres0);
|
||||
writel(0x00002032, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020DC, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x000020AA, &axi_qos->qosthres0);
|
||||
writel(0x00002032, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00001FF0, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00002001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x00002063, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x00002063, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __QOS_H__
|
||||
#define __QOS_H__
|
||||
|
||||
void qos_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -372,6 +372,7 @@ Active arm armv7 omap5 ti dra7xx
|
|||
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - Lokesh Vutla <lokeshvutla@ti.com>
|
||||
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
|
||||
Active arm armv7 rmobile renesas alt alt - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga <r.baldyga@samsung.com>
|
||||
|
|
|
|||
|
|
@ -413,7 +413,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
|
|||
|
||||
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
|
||||
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7794)
|
||||
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
|
||||
#endif
|
||||
/* Configure phy */
|
||||
|
|
@ -439,7 +440,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
|
|||
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
|
||||
sh_eth_write(eth, 1, RTRATE);
|
||||
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
|
||||
defined(CONFIG_R8A7791)
|
||||
defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
|
||||
val = ECMR_RTM;
|
||||
#endif
|
||||
} else if (phy->speed == 10) {
|
||||
|
|
|
|||
|
|
@ -358,7 +358,8 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
|
|||
#elif defined(CONFIG_R8A7740)
|
||||
#define SH_ETH_TYPE_GETHER
|
||||
#define BASE_IO_ADDR 0xE9A00000
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7794)
|
||||
#define SH_ETH_TYPE_ETHER
|
||||
#define BASE_IO_ADDR 0xEE700200
|
||||
#elif defined(CONFIG_R7S72100)
|
||||
|
|
@ -569,7 +570,8 @@ enum FELIC_MODE_BIT {
|
|||
ECMR_PRM = 0x00000001,
|
||||
#ifdef CONFIG_CPU_SH7724
|
||||
ECMR_RTM = 0x00000010,
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7794)
|
||||
ECMR_RTM = 0x00000004,
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -226,7 +226,8 @@ struct uart_port {
|
|||
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
|
||||
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
||||
defined(CONFIG_R8A7794)
|
||||
# define SCIF_ORER 0x0001
|
||||
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* include/configs/alt.h
|
||||
* This file is alt board configuration.
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ALT_H
|
||||
#define __ALT_H
|
||||
|
||||
#undef DEBUG
|
||||
#define CONFIG_ARMV7
|
||||
#define CONFIG_R8A7794
|
||||
#define CONFIG_RMOBILE
|
||||
#define CONFIG_RMOBILE_BOARD_STRING "Alt"
|
||||
#define CONFIG_SH_GPIO_PFC
|
||||
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
#define CONFIG_CMD_EDITENV
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_DFL
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_RUN
|
||||
#define CONFIG_CMD_LOADS
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xE6304000
|
||||
#define CONFIG_SYS_THUMB_BUILD
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS ""
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_TMU_TIMER
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
|
||||
#define STACK_AREA_SIZE 0xC000
|
||||
#define LOW_LEVEL_MERAM_STACK \
|
||||
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
||||
|
||||
/* MEMORY */
|
||||
#define ALT_SDRAM_BASE 0x40000000
|
||||
#define ALT_SDRAM_SIZE (1024u * 1024 * 1024)
|
||||
#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE 512
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE
|
||||
#define CONFIG_CONS_SCIF2
|
||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
504 * 1024 * 1024)
|
||||
#undef CONFIG_SYS_ALT_MEMTEST
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SH_QSPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_SPI_FLASH_QUAD
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_ADDR 0xC0000
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_low=0x40e00000\0" \
|
||||
"bootm_size=0x100000\0" \
|
||||
|
||||
/* SH Ether */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_SH_ETHER
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Board Clock */
|
||||
#define RMOBILE_XTAL_CLK 20000000u
|
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
|
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
|
||||
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
|
||||
#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ
|
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
/* i2c */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
|
||||
#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED0 400000
|
||||
#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED1 400000
|
||||
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED2 400000
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 10000000
|
||||
|
||||
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
|
||||
|
||||
#endif /* __ALT_H */
|
||||
Loading…
Reference in New Issue