* Patches by David Mller, 12 Jun 2003:
- rewrite of the S3C24X0 register definitions stuff - "driver" for the built-in S3C24X0 RTC * Patches by Yuli Barcohen, 12 Jun 2003: - Add MII support and Ethernet PHY initialization for MPC8260ADS board - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset configuration word supplied by FPGA on some MPC8260ADS boards * Patch by Pantelis Antoniou, 10 Jun 2003: Unify status LED interface
This commit is contained in:
parent
15ef8a5d17
commit
48b42616e9
12
CHANGELOG
12
CHANGELOG
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@ -2,6 +2,18 @@
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Changes since U-Boot 0.3.1:
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Changes since U-Boot 0.3.1:
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======================================================================
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======================================================================
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* Patches by David Müller, 12 Jun 2003:
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- rewrite of the S3C24X0 register definitions stuff
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- "driver" for the built-in S3C24X0 RTC
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* Patches by Yuli Barcohen, 12 Jun 2003:
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- Add MII support and Ethernet PHY initialization for MPC8260ADS board
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- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
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configuration word supplied by FPGA on some MPC8260ADS boards
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* Patch by Pantelis Antoniou, 10 Jun 2003:
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Unify status LED interface
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* Add support for DS12887 RTC; add RTC support for ATC board
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* Add support for DS12887 RTC; add RTC support for ATC board
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* Patch by Nicolas Lacressonniere, 11 Jun 2003:
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* Patch by Nicolas Lacressonniere, 11 Jun 2003:
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@ -9,6 +9,10 @@
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
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* Added support for the 16M dram simm on the 8260ads boards
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* Added support for the 16M dram simm on the 8260ads boards
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*
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*
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* (C) Copyright 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
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*
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* See file CREDITS for list of people who contributed to this
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* See file CREDITS for list of people who contributed to this
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* project.
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* project.
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*
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*
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@ -45,7 +45,11 @@ extern int gunzip (void *, int, unsigned char *, int *);
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extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);
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extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);
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#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
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#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
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#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
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#define IMAGE_SIZE 0x80000
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#define IMAGE_SIZE 0x80000
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#elif defined(CONFIG_VCMA9)
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#define IMAGE_SIZE 0x40000 /* ugly, but it works for now */
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#endif
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extern flash_info_t flash_info[]; /* info for FLASH chips */
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extern flash_info_t flash_info[]; /* info for FLASH chips */
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@ -15,10 +15,10 @@
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# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
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# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
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# optionally with a ramdisk at 3080'0000
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# optionally with a ramdisk at 3080'0000
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#
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#
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# we load ourself to 33F0'0000
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# we load ourself to 33F8'0000
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#
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#
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# download area is 3300'0000
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# download area is 3300'0000
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#
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#
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TEXT_BASE = 0x33F00000
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TEXT_BASE = 0x33F80000
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@ -54,8 +54,10 @@
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/* BANK0CON */
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/* BANK0CON */
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#define B0_Tacs 0x0 /* 0clk */
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#define B0_Tacs 0x0 /* 0clk */
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#define B0_Tcos 0x0 /* 0clk */
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#define B0_Tcos 0x1 /* 1clk */
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#define B0_Tacc 0x5 /* 8clk */
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/*#define B0_Tcos 0x0 0clk */
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#define B0_Tacc 0x7 /* 14clk */
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/*#define B0_Tacc 0x5 8clk */
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#define B0_Tcoh 0x0 /* 0clk */
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#define B0_Tcoh 0x0 /* 0clk */
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#define B0_Tah 0x0 /* 0clk */
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#define B0_Tah 0x0 /* 0clk */
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#define B0_Tacp 0x0 /* page mode is not used */
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#define B0_Tacp 0x0 /* page mode is not used */
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@ -63,8 +65,10 @@
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/* BANK1CON */
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/* BANK1CON */
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#define B1_Tacs 0x0 /* 0clk */
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#define B1_Tacs 0x0 /* 0clk */
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#define B1_Tcos 0x0 /* 0clk */
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#define B1_Tcos 0x1 /* 1clk */
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#define B1_Tacc 0x5 /* 8clk */
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/*#define B1_Tcos 0x0 0clk */
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#define B1_Tacc 0x7 /* 14clk */
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/*#define B1_Tacc 0x5 8clk */
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#define B1_Tcoh 0x0 /* 0clk */
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#define B1_Tcoh 0x0 /* 0clk */
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#define B1_Tah 0x0 /* 0clk */
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#define B1_Tah 0x0 /* 0clk */
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#define B1_Tacp 0x0 /* page mode is not used */
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#define B1_Tacp 0x0 /* page mode is not used */
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@ -72,41 +72,46 @@ static inline void delay(unsigned long loops)
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int board_init(void)
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int board_init(void)
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{
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{
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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rLOCKTIME = 0xFFFFFF;
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clk_power->LOCKTIME = 0xFFFFFF;
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/* configure MPLL */
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/* configure MPLL */
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rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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/* some delay between MPLL and UPLL */
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/* some delay between MPLL and UPLL */
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delay (4000);
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delay (4000);
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/* configure UPLL */
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/* configure UPLL */
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rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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/* some delay between MPLL and UPLL */
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/* some delay between MPLL and UPLL */
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delay (8000);
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delay (8000);
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/* set up the I/O ports */
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/* set up the I/O ports */
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rGPACON = 0x007FFFFF;
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gpio->GPACON = 0x007FFFFF;
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rGPBCON = 0x002AAAAA;
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gpio->GPBCON = 0x002AAAAA;
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rGPBUP = 0x000002BF;
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gpio->GPBUP = 0x000002BF;
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rGPCCON = 0xAAAAAAAA;
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gpio->GPCCON = 0xAAAAAAAA;
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rGPCUP = 0x0000FFFF;
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gpio->GPCUP = 0x0000FFFF;
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rGPDCON = 0xAAAAAAAA;
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gpio->GPDCON = 0xAAAAAAAA;
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rGPDUP = 0x0000FFFF;
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gpio->GPDUP = 0x0000FFFF;
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rGPECON = 0xAAAAAAAA;
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gpio->GPECON = 0xAAAAAAAA;
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rGPEUP = 0x000037F7;
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gpio->GPEUP = 0x000037F7;
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rGPFCON = 0x00000000;
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gpio->GPFCON = 0x00000000;
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rGPFUP = 0x00000000;
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gpio->GPFUP = 0x00000000;
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rGPGCON = 0xFFEAFF5A;
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gpio->GPGCON = 0xFFEAFF5A;
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rGPGUP = 0x0000F0DC;
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gpio->GPGUP = 0x0000F0DC;
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rGPHCON = 0x0028AAAA;
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gpio->GPHCON = 0x0028AAAA;
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rGPHUP = 0x00000656;
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gpio->GPHUP = 0x00000656;
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/* setup correct IRQ modes for NIC */
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/* setup correct IRQ modes for NIC */
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rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
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gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
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/* select USB port 2 to be host or device (fix to host for now) */
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gpio->MISCCR |= 0x08;
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/* init serial */
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/* init serial */
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gd->baudrate = CONFIG_BAUDRATE;
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gd->baudrate = CONFIG_BAUDRATE;
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@ -135,6 +140,50 @@ int dram_init(void)
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return 0;
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return 0;
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}
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}
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/*
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* NAND flash initialization.
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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extern void
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nand_probe(ulong physadr);
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static inline void NF_Reset(void)
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{
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int i;
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NF_SetCE(NFCE_LOW);
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NF_Cmd(0xFF); /* reset command */
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for(i = 0; i < 10; i++); /* tWB = 100ns. */
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NF_WaitRB(); /* wait 200~500us; */
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NF_SetCE(NFCE_HIGH);
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}
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static inline void NF_Init(void)
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{
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#define TACLS 0
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#define TWRPH0 3
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#define TWRPH1 0
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NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
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//nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
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// 1 1 1 1, 1 xxx, r xxx, r xxx
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// En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1
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NF_Reset();
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}
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void
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nand_init(void)
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{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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NF_Init();
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printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
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nand_probe((ulong)nand);
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}
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#endif
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/*
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/*
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* Get some Board/PLD Info
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* Get some Board/PLD Info
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*/
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*/
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@ -195,12 +244,12 @@ int checkboard(void)
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puts ("### No HW ID - assuming VCMA9");
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puts ("### No HW ID - assuming VCMA9");
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} else {
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} else {
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b->serial_name[5] = 0;
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b->serial_name[5] = 0;
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printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(),
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printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
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Get_Board_PCB(), &b->serial_name[6]);
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Get_Board_PCB(), &b->serial_name[6]);
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}
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}
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} else {
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} else {
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s[5] = 0;
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s[5] = 0;
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printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
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printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
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&s[6]);
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&s[6]);
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}
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}
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printf("\n");
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printf("\n");
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@ -211,7 +260,7 @@ int checkboard(void)
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void print_vcma9_rev(void)
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void print_vcma9_rev(void)
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{
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{
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printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n",
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printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
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Get_Board_Config(), Get_Board_PCB(),
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Get_Board_Config(), Get_Board_PCB(),
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Get_PLD_Version(), Get_PLD_Revision());
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Get_PLD_Version(), Get_PLD_Revision());
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}
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}
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@ -245,5 +294,3 @@ void print_vcma9_info(void)
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{
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{
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print_vcma9_rev();
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print_vcma9_rev();
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}
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}
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@ -25,11 +25,97 @@
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* Global routines used for VCMA9
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* Global routines used for VCMA9
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*****************************************************************************/
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*****************************************************************************/
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#include <s3c2410.h>
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extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
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extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
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void print_vcma9_info(void);
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void print_vcma9_info(void);
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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typedef enum {
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NFCE_LOW,
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NFCE_HIGH
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} NFCE_STATE;
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static inline void NF_Conf(u16 conf)
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{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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nand->NFCONF = conf;
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}
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static inline void NF_Cmd(u8 cmd)
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{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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nand->NFCMD = cmd;
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}
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static inline void NF_CmdW(u8 cmd)
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{
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NF_Cmd(cmd);
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udelay(1);
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}
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static inline void NF_Addr(u8 addr)
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{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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|
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nand->NFADDR = addr;
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}
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|
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static inline void NF_SetCE(NFCE_STATE s)
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|
{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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|
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switch (s) {
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case NFCE_LOW:
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nand->NFCONF &= ~(1<<11);
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break;
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|
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case NFCE_HIGH:
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|
nand->NFCONF |= (1<<11);
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|
break;
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|
}
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}
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|
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static inline void NF_WaitRB(void)
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{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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|
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|
while (!(nand->NFSTAT & (1<<0)));
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}
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|
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static inline void NF_Write(u8 data)
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|
{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
|
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|
|
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nand->NFDATA = data;
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|
}
|
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|
|
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static inline u8 NF_Read(void)
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|
{
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S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
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|
|
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return(nand->NFDATA);
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|
}
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|
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static inline void NF_Init_ECC(void)
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|
{
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|
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
|
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|
|
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|
nand->NFCONF |= (1<<12);
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|
}
|
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|
|
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static inline u32 NF_Read_ECC(void)
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|
{
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|
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
|
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|
|
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|
return(nand->NFECC);
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|
}
|
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|
|
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|
#endif
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|
|
||||||
|
|
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#define PLD_BASE_ADDRESS 0x2C000100
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#define PLD_BASE_ADDRESS 0x2C000100
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#define PLD_ID_REG (PLD_BASE_ADDRESS + 0)
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#define PLD_ID_REG (PLD_BASE_ADDRESS + 0)
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|
@ -39,5 +125,3 @@ void print_vcma9_info(void);
|
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#define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4)
|
#define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4)
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#define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5)
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#define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5)
|
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|
|
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|
|
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|
|
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|
|
|
@ -46,33 +46,35 @@ extern int do_mdm_init; /* defined in common/main.c */
|
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int board_init (void)
|
int board_init (void)
|
||||||
{
|
{
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
/* memory and cpu-speed are setup before relocation */
|
/* memory and cpu-speed are setup before relocation */
|
||||||
/* change the clock to be 50 MHz 1:1:1 */
|
/* change the clock to be 50 MHz 1:1:1 */
|
||||||
rMPLLCON = 0x5c042;
|
clk_power->MPLLCON = 0x5c042;
|
||||||
rCLKDIVN = 0;
|
clk_power->CLKDIVN = 0;
|
||||||
/* set up the I/O ports */
|
/* set up the I/O ports */
|
||||||
rPACON = 0x3ffff;
|
gpio->PACON = 0x3ffff;
|
||||||
rPBCON = 0xaaaaaaaa;
|
gpio->PBCON = 0xaaaaaaaa;
|
||||||
rPBUP = 0xffff;
|
gpio->PBUP = 0xffff;
|
||||||
rPECON = 0x0;
|
gpio->PECON = 0x0;
|
||||||
rPEUP = 0x0;
|
gpio->PEUP = 0x0;
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
|
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
|
||||||
/* 10, 10, 00, 00, 10, 00, 10 */
|
/* 10, 10, 00, 00, 10, 00, 10 */
|
||||||
rPFCON=0xa22;
|
gpio->PFCON=0xa22;
|
||||||
/* Disable pull-up on Rx, Tx, CTS and RTS pins */
|
/* Disable pull-up on Rx, Tx, CTS and RTS pins */
|
||||||
rPFUP=0x35;
|
gpio->PFUP=0x35;
|
||||||
#else
|
#else
|
||||||
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
|
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
|
||||||
/* 00, 00, 00, 00, 10, 00, 10 */
|
/* 00, 00, 00, 00, 10, 00, 10 */
|
||||||
rPFCON = 0x22;
|
gpio->PFCON = 0x22;
|
||||||
/* Disable pull-up on Rx and Tx pins */
|
/* Disable pull-up on Rx and Tx pins */
|
||||||
rPFUP = 0x5;
|
gpio->PFUP = 0x5;
|
||||||
#endif /* CONFIG_HWFLOW */
|
#endif /* CONFIG_HWFLOW */
|
||||||
rPGCON = 0x0;
|
gpio->PGCON = 0x0;
|
||||||
rPGUP = 0x0;
|
gpio->PGUP = 0x0;
|
||||||
rOPENCR = 0x0;
|
gpio->OPENCR = 0x0;
|
||||||
|
|
||||||
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
|
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
|
||||||
gd->bd->bi_arch_number = 145;
|
gd->bd->bi_arch_number = 145;
|
||||||
|
|
|
@ -16,10 +16,10 @@
|
||||||
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
|
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
|
||||||
# optionally with a ramdisk at 3080'0000
|
# optionally with a ramdisk at 3080'0000
|
||||||
#
|
#
|
||||||
# we load ourself to 33F0'0000
|
# we load ourself to 33F8'0000
|
||||||
#
|
#
|
||||||
# download area is 3300'0000
|
# download area is 3300'0000
|
||||||
#
|
#
|
||||||
|
|
||||||
|
|
||||||
TEXT_BASE = 0x33F00000
|
TEXT_BASE = 0x33F80000
|
||||||
|
|
|
@ -68,38 +68,40 @@ static inline void delay (unsigned long loops)
|
||||||
int board_init (void)
|
int board_init (void)
|
||||||
{
|
{
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
/* to reduce PLL lock time, adjust the LOCKTIME register */
|
/* to reduce PLL lock time, adjust the LOCKTIME register */
|
||||||
rLOCKTIME = 0xFFFFFF;
|
clk_power->LOCKTIME = 0xFFFFFF;
|
||||||
|
|
||||||
/* configure MPLL */
|
/* configure MPLL */
|
||||||
rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
|
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
|
||||||
|
|
||||||
/* some delay between MPLL and UPLL */
|
/* some delay between MPLL and UPLL */
|
||||||
delay (4000);
|
delay (4000);
|
||||||
|
|
||||||
/* configure UPLL */
|
/* configure UPLL */
|
||||||
rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
|
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
|
||||||
|
|
||||||
/* some delay between MPLL and UPLL */
|
/* some delay between MPLL and UPLL */
|
||||||
delay (8000);
|
delay (8000);
|
||||||
|
|
||||||
/* set up the I/O ports */
|
/* set up the I/O ports */
|
||||||
rGPACON = 0x007FFFFF;
|
gpio->GPACON = 0x007FFFFF;
|
||||||
rGPBCON = 0x00044555;
|
gpio->GPBCON = 0x00044555;
|
||||||
rGPBUP = 0x000007FF;
|
gpio->GPBUP = 0x000007FF;
|
||||||
rGPCCON = 0xAAAAAAAA;
|
gpio->GPCCON = 0xAAAAAAAA;
|
||||||
rGPCUP = 0x0000FFFF;
|
gpio->GPCUP = 0x0000FFFF;
|
||||||
rGPDCON = 0xAAAAAAAA;
|
gpio->GPDCON = 0xAAAAAAAA;
|
||||||
rGPDUP = 0x0000FFFF;
|
gpio->GPDUP = 0x0000FFFF;
|
||||||
rGPECON = 0xAAAAAAAA;
|
gpio->GPECON = 0xAAAAAAAA;
|
||||||
rGPEUP = 0x0000FFFF;
|
gpio->GPEUP = 0x0000FFFF;
|
||||||
rGPFCON = 0x000055AA;
|
gpio->GPFCON = 0x000055AA;
|
||||||
rGPFUP = 0x000000FF;
|
gpio->GPFUP = 0x000000FF;
|
||||||
rGPGCON = 0xFF95FFBA;
|
gpio->GPGCON = 0xFF95FFBA;
|
||||||
rGPGUP = 0x0000FFFF;
|
gpio->GPGUP = 0x0000FFFF;
|
||||||
rGPHCON = 0x002AFAAA;
|
gpio->GPHCON = 0x002AFAAA;
|
||||||
rGPHUP = 0x000007FF;
|
gpio->GPHUP = 0x000007FF;
|
||||||
|
|
||||||
/* arch number of SMDK2410-Board */
|
/* arch number of SMDK2410-Board */
|
||||||
gd->bd->bi_arch_number = 193;
|
gd->bd->bi_arch_number = 193;
|
||||||
|
|
|
@ -71,37 +71,39 @@ int board_init ()
|
||||||
extern int vfd_init_clocks(void);
|
extern int vfd_init_clocks(void);
|
||||||
#endif
|
#endif
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
/* memory and cpu-speed are setup before relocation */
|
/* memory and cpu-speed are setup before relocation */
|
||||||
#ifdef CONFIG_TRAB_50MHZ
|
#ifdef CONFIG_TRAB_50MHZ
|
||||||
/* change the clock to be 50 MHz 1:1:1 */
|
/* change the clock to be 50 MHz 1:1:1 */
|
||||||
/* MDIV:0x5c PDIV:4 SDIV:2 */
|
/* MDIV:0x5c PDIV:4 SDIV:2 */
|
||||||
rMPLLCON = 0x5c042;
|
clk_power->MPLLCON = 0x5c042;
|
||||||
rCLKDIVN = 0;
|
clk_power->CLKDIVN = 0;
|
||||||
#else
|
#else
|
||||||
/* change the clock to be 133 MHz 1:2:4 */
|
/* change the clock to be 133 MHz 1:2:4 */
|
||||||
/* MDIV:0x7d PDIV:4 SDIV:1 */
|
/* MDIV:0x7d PDIV:4 SDIV:1 */
|
||||||
rMPLLCON = 0x7d041;
|
clk_power->MPLLCON = 0x7d041;
|
||||||
rCLKDIVN = 3;
|
clk_power->CLKDIVN = 3;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* set up the I/O ports */
|
/* set up the I/O ports */
|
||||||
rPACON = 0x3ffff;
|
gpio->PACON = 0x3ffff;
|
||||||
rPBCON = 0xaaaaaaaa;
|
gpio->PBCON = 0xaaaaaaaa;
|
||||||
rPBUP = 0xffff;
|
gpio->PBUP = 0xffff;
|
||||||
/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
|
/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
|
||||||
/* 00, 10, 10, 10, 10, 10, 10 */
|
/* 00, 10, 10, 10, 10, 10, 10 */
|
||||||
rPFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
|
gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
|
/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
|
||||||
rPFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
|
gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
|
||||||
#else
|
#else
|
||||||
/* do not pull up RXD0, RXD1, TXD0, TXD1 */
|
/* do not pull up RXD0, RXD1, TXD0, TXD1 */
|
||||||
rPFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
|
gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3);
|
||||||
#endif
|
#endif
|
||||||
rPGCON = 0x0;
|
gpio->PGCON = 0x0;
|
||||||
rPGUP = 0x0;
|
gpio->PGUP = 0x0;
|
||||||
rOPENCR= 0x0;
|
gpio->OPENCR= 0x0;
|
||||||
|
|
||||||
/* arch number of SAMSUNG-Board */
|
/* arch number of SAMSUNG-Board */
|
||||||
/* MACH_TYPE_SMDK2400 */
|
/* MACH_TYPE_SMDK2400 */
|
||||||
|
@ -112,8 +114,8 @@ int board_init ()
|
||||||
gd->bd->bi_boot_params = 0x0c000100;
|
gd->bd->bi_boot_params = 0x0c000100;
|
||||||
|
|
||||||
/* Make sure both buzzers are turned off */
|
/* Make sure both buzzers are turned off */
|
||||||
rPDCON |= 0x5400;
|
gpio->PDCON |= 0x5400;
|
||||||
rPDDAT &= ~0xE0;
|
gpio->PDDAT &= ~0xE0;
|
||||||
|
|
||||||
#ifdef CONFIG_VFD
|
#ifdef CONFIG_VFD
|
||||||
vfd_init_clocks();
|
vfd_init_clocks();
|
||||||
|
@ -305,57 +307,73 @@ static int key_pressed(void)
|
||||||
|
|
||||||
#ifdef CFG_BRIGHTNESS
|
#ifdef CFG_BRIGHTNESS
|
||||||
|
|
||||||
#define SET_CS_TOUCH (rPDDAT &= 0x5FF)
|
static inline void SET_CS_TOUCH(void)
|
||||||
#define CLR_CS_TOUCH (rPDDAT |= 0x200)
|
{
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
|
gpio->PDDAT &= 0x5FF;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void CLR_CS_TOUCH(void)
|
||||||
|
{
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
|
gpio->PDDAT |= 0x200;
|
||||||
|
}
|
||||||
|
|
||||||
static void spi_init(void)
|
static void spi_init(void)
|
||||||
{
|
{
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
/* Configure I/O ports. */
|
/* Configure I/O ports. */
|
||||||
rPDCON = (rPDCON & 0xF3FFFF) | 0x040000;
|
gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
|
||||||
rPGCON = (rPGCON & 0x0F3FFF) | 0x008000;
|
gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
|
||||||
rPGCON = (rPGCON & 0x0CFFFF) | 0x020000;
|
gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
|
||||||
rPGCON = (rPGCON & 0x03FFFF) | 0x080000;
|
gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
|
||||||
|
|
||||||
CLR_CS_TOUCH;
|
CLR_CS_TOUCH();
|
||||||
|
|
||||||
rSPPRE = 0x1F; /* Baudrate ca. 514kHz */
|
spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
|
||||||
rSPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
|
spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
|
||||||
rSPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
|
spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
|
||||||
|
|
||||||
/* Dummy byte ensures clock to be low. */
|
/* Dummy byte ensures clock to be low. */
|
||||||
for (i = 0; i < 10; i++) {
|
for (i = 0; i < 10; i++) {
|
||||||
rSPTDAT = 0xFF;
|
spi->ch[0].SPTDAT = 0xFF;
|
||||||
}
|
}
|
||||||
wait_transmit_done();
|
wait_transmit_done();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void wait_transmit_done(void)
|
static void wait_transmit_done(void)
|
||||||
{
|
{
|
||||||
while (!(rSPSTA & 0x01)); /* wait until transfer is done */
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
|
||||||
|
|
||||||
|
while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tsc2000_write(unsigned int page, unsigned int reg,
|
static void tsc2000_write(unsigned int page, unsigned int reg,
|
||||||
unsigned int data)
|
unsigned int data)
|
||||||
{
|
{
|
||||||
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
|
||||||
unsigned int command;
|
unsigned int command;
|
||||||
|
|
||||||
SET_CS_TOUCH;
|
SET_CS_TOUCH();
|
||||||
command = 0x0000;
|
command = 0x0000;
|
||||||
command |= (page << 11);
|
command |= (page << 11);
|
||||||
command |= (reg << 5);
|
command |= (reg << 5);
|
||||||
|
|
||||||
rSPTDAT = (command & 0xFF00) >> 8;
|
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
|
||||||
wait_transmit_done();
|
wait_transmit_done();
|
||||||
rSPTDAT = (command & 0x00FF);
|
spi->ch[0].SPTDAT = (command & 0x00FF);
|
||||||
wait_transmit_done();
|
wait_transmit_done();
|
||||||
rSPTDAT = (data & 0xFF00) >> 8;
|
spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
|
||||||
wait_transmit_done();
|
wait_transmit_done();
|
||||||
rSPTDAT = (data & 0x00FF);
|
spi->ch[0].SPTDAT = (data & 0x00FF);
|
||||||
wait_transmit_done();
|
wait_transmit_done();
|
||||||
|
|
||||||
CLR_CS_TOUCH;
|
CLR_CS_TOUCH();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tsc2000_set_brightness(void)
|
static void tsc2000_set_brightness(void)
|
||||||
|
|
|
@ -359,14 +359,17 @@ void transfer_pic(int display, unsigned char *adr, int height, int width)
|
||||||
*/
|
*/
|
||||||
int vfd_init_clocks (void)
|
int vfd_init_clocks (void)
|
||||||
{
|
{
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||||
|
S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
|
||||||
|
|
||||||
/* try to determine display type from the value
|
/* try to determine display type from the value
|
||||||
* defined by pull-ups
|
* defined by pull-ups
|
||||||
*/
|
*/
|
||||||
rPCUP = (rPCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
|
gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
|
||||||
rPCCON = (rPCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
|
gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
|
||||||
udelay (10); /* allow signals to settle */
|
udelay (10); /* allow signals to settle */
|
||||||
vfd_board_id = (~rPCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
|
vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
|
||||||
|
|
||||||
VFD_DISABLE; /* activate blank for the vfd */
|
VFD_DISABLE; /* activate blank for the vfd */
|
||||||
|
|
||||||
|
@ -377,39 +380,39 @@ int vfd_init_clocks (void)
|
||||||
/* If new board revision, then use PWM 3 as cpld-clock */
|
/* If new board revision, then use PWM 3 as cpld-clock */
|
||||||
/* Enable 500 Hz timer for fill level sensor to operate properly */
|
/* Enable 500 Hz timer for fill level sensor to operate properly */
|
||||||
/* Configure TOUT3 as functional pin, disable pull-up */
|
/* Configure TOUT3 as functional pin, disable pull-up */
|
||||||
rPDCON &= ~0x30000;
|
gpio->PDCON &= ~0x30000;
|
||||||
rPDCON |= 0x20000;
|
gpio->PDCON |= 0x20000;
|
||||||
rPDUP |= (1 << 8);
|
gpio->PDUP |= (1 << 8);
|
||||||
|
|
||||||
/* Configure the prescaler */
|
/* Configure the prescaler */
|
||||||
rTCFG0 &= ~0xff00;
|
timers->TCFG0 &= ~0xff00;
|
||||||
rTCFG0 |= 0x0f00;
|
timers->TCFG0 |= 0x0f00;
|
||||||
|
|
||||||
/* Select MUX input (divider) for timer3 (1/16) */
|
/* Select MUX input (divider) for timer3 (1/16) */
|
||||||
rTCFG1 &= ~0xf000;
|
timers->TCFG1 &= ~0xf000;
|
||||||
rTCFG1 |= 0x3000;
|
timers->TCFG1 |= 0x3000;
|
||||||
|
|
||||||
/* Enable autoreload and set the counter and compare
|
/* Enable autoreload and set the counter and compare
|
||||||
* registers to values for the 500 Hz clock
|
* registers to values for the 500 Hz clock
|
||||||
* (for a given prescaler (15) and divider (16)):
|
* (for a given prescaler (15) and divider (16)):
|
||||||
* counter = (66000000 / 500) >> 9;
|
* counter = (66000000 / 500) >> 9;
|
||||||
*/
|
*/
|
||||||
rTCNTB3 = 0x101;
|
timers->ch[3].TCNTB = 0x101;
|
||||||
rTCMPB3 = 0x101 / 2;
|
timers->ch[3].TCMPB = 0x101 / 2;
|
||||||
|
|
||||||
/* Start timer */
|
/* Start timer */
|
||||||
rTCON = (rTCON | UPDATE3 | RELOAD3) & ~INVERT3;
|
timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
|
||||||
rTCON = (rTCON | START3) & ~UPDATE3;
|
timers->TCON = (timers->TCON | START3) & ~UPDATE3;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
/* If old board revision, then use vm-signal as cpld-clock */
|
/* If old board revision, then use vm-signal as cpld-clock */
|
||||||
rLCDCON2 = 0x00FFC000;
|
lcd->LCDCON2 = 0x00FFC000;
|
||||||
rLCDCON3 = 0x0007FF00;
|
lcd->LCDCON3 = 0x0007FF00;
|
||||||
rLCDCON4 = 0x00000000;
|
lcd->LCDCON4 = 0x00000000;
|
||||||
rLCDCON5 = 0x00000400;
|
lcd->LCDCON5 = 0x00000400;
|
||||||
rLCDCON1 = 0x00000B75;
|
lcd->LCDCON1 = 0x00000B75;
|
||||||
/* VM (GPD1) is used as clock for the CPLD */
|
/* VM (GPD1) is used as clock for the CPLD */
|
||||||
rPDCON = (rPDCON & 0xFFFFFFF3) | 0x00000008;
|
gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -425,6 +428,8 @@ int vfd_init_clocks (void)
|
||||||
*/
|
*/
|
||||||
int drv_vfd_init(void)
|
int drv_vfd_init(void)
|
||||||
{
|
{
|
||||||
|
S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
char *tmp;
|
char *tmp;
|
||||||
ulong palette;
|
ulong palette;
|
||||||
static int vfd_init_done = 0;
|
static int vfd_init_done = 0;
|
||||||
|
@ -481,40 +486,40 @@ int drv_vfd_init(void)
|
||||||
* see manual S3C2400
|
* see manual S3C2400
|
||||||
*/
|
*/
|
||||||
/* Stopp LCD-Controller */
|
/* Stopp LCD-Controller */
|
||||||
rLCDCON1 = 0x00000000;
|
lcd->LCDCON1 = 0x00000000;
|
||||||
/* frame buffer startadr */
|
/* frame buffer startadr */
|
||||||
rLCDSADDR1 = gd->fb_base >> 1;
|
lcd->LCDSADDR1 = gd->fb_base >> 1;
|
||||||
/* frame buffer endadr */
|
/* frame buffer endadr */
|
||||||
rLCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
|
lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
|
||||||
rLCDSADDR3 = ((256/4));
|
lcd->LCDSADDR3 = ((256/4));
|
||||||
rLCDCON2 = 0x000DC000;
|
lcd->LCDCON2 = 0x000DC000;
|
||||||
if(gd->vfd_type == VFD_TYPE_MN11236)
|
if(gd->vfd_type == VFD_TYPE_MN11236)
|
||||||
rLCDCON2 = 37 << 14; /* MN11236: 38 lines */
|
lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */
|
||||||
else
|
else
|
||||||
rLCDCON2 = 55 << 14; /* T119C: 56 lines */
|
lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */
|
||||||
rLCDCON3 = 0x0051000A;
|
lcd->LCDCON3 = 0x0051000A;
|
||||||
rLCDCON4 = 0x00000001;
|
lcd->LCDCON4 = 0x00000001;
|
||||||
if (gd->vfd_type && vfd_inv_data)
|
if (gd->vfd_type && vfd_inv_data)
|
||||||
rLCDCON5 = 0x000004C0;
|
lcd->LCDCON5 = 0x000004C0;
|
||||||
else
|
else
|
||||||
rLCDCON5 = 0x00000440;
|
lcd->LCDCON5 = 0x00000440;
|
||||||
|
|
||||||
/* Port pins as LCD output */
|
/* Port pins as LCD output */
|
||||||
rPCCON = (rPCCON & 0xFFFFFF00)| 0x000000AA;
|
gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
|
||||||
rPDCON = (rPDCON & 0xFFFFFF03)| 0x000000A8;
|
gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
|
||||||
|
|
||||||
/* Synchronize VFD enable with LCD controller to avoid flicker */
|
/* Synchronize VFD enable with LCD controller to avoid flicker */
|
||||||
rLCDCON1 = 0x00000B75; /* Start LCD-Controller */
|
lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */
|
||||||
while((rLCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */
|
while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */
|
||||||
while((rLCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */
|
while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */
|
||||||
while((rLCDCON5 & 0x060000)==0x040000);
|
while((lcd->LCDCON5 & 0x060000)==0x040000);
|
||||||
while((rLCDCON5 & 0x060000)!=0x000000);
|
while((lcd->LCDCON5 & 0x060000)!=0x000000);
|
||||||
if(gd->vfd_type)
|
if(gd->vfd_type)
|
||||||
VFD_ENABLE;
|
VFD_ENABLE;
|
||||||
|
|
||||||
debug ("LCDSADDR1: %lX\n", rLCDSADDR1);
|
debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
|
||||||
debug ("LCDSADDR2: %lX\n", rLCDSADDR2);
|
debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
|
||||||
debug ("LCDSADDR3: %lX\n", rLCDSADDR3);
|
debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -525,9 +530,11 @@ rLCDCON2 = 0x000DC000;
|
||||||
*/
|
*/
|
||||||
void disable_vfd (void)
|
void disable_vfd (void)
|
||||||
{
|
{
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
VFD_DISABLE;
|
VFD_DISABLE;
|
||||||
rPDCON &= ~0xC;
|
gpio->PDCON &= ~0xC;
|
||||||
rPDUP &= ~0x2;
|
gpio->PDUP &= ~0x2;
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************/
|
/************************************************************************/
|
||||||
|
|
|
@ -43,7 +43,12 @@ extern void reset_cpu(ulong addr);
|
||||||
int timer_load_val = 0;
|
int timer_load_val = 0;
|
||||||
|
|
||||||
/* macro to read the 16 bit timer */
|
/* macro to read the 16 bit timer */
|
||||||
#define READ_TIMER (rTCNTO4 & 0xffff)
|
static inline ulong READ_TIMER(void)
|
||||||
|
{
|
||||||
|
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||||
|
|
||||||
|
return (timers->TCNTO4 & 0xffff);
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_USE_IRQ
|
#ifdef CONFIG_USE_IRQ
|
||||||
/* enable IRQ interrupts */
|
/* enable IRQ interrupts */
|
||||||
|
@ -184,9 +189,11 @@ static ulong lastdec;
|
||||||
|
|
||||||
int interrupt_init (void)
|
int interrupt_init (void)
|
||||||
{
|
{
|
||||||
|
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
|
||||||
|
|
||||||
/* use PWM Timer 4 because it has no output */
|
/* use PWM Timer 4 because it has no output */
|
||||||
/* prescaler for Timer 4 is 16 */
|
/* prescaler for Timer 4 is 16 */
|
||||||
rTCFG0 = 0x0f00;
|
timers->TCFG0 = 0x0f00;
|
||||||
if (timer_load_val == 0)
|
if (timer_load_val == 0)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
|
@ -197,11 +204,11 @@ int interrupt_init (void)
|
||||||
timer_load_val = get_PCLK()/(2 * 16 * 100);
|
timer_load_val = get_PCLK()/(2 * 16 * 100);
|
||||||
}
|
}
|
||||||
/* load value for 10 ms timeout */
|
/* load value for 10 ms timeout */
|
||||||
lastdec = rTCNTB4 = timer_load_val;
|
lastdec = timers->TCNTB4 = timer_load_val;
|
||||||
/* auto load, manual update of Timer 4 */
|
/* auto load, manual update of Timer 4 */
|
||||||
rTCON = (rTCON & ~0x0700000) | 0x600000;
|
timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
|
||||||
/* auto load, start Timer 4 */
|
/* auto load, start Timer 4 */
|
||||||
rTCON = (rTCON & ~0x0700000) | 0x500000;
|
timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
|
||||||
timestamp = 0;
|
timestamp = 0;
|
||||||
|
|
||||||
return (0);
|
return (0);
|
||||||
|
@ -243,13 +250,13 @@ void udelay (unsigned long usec)
|
||||||
void reset_timer_masked (void)
|
void reset_timer_masked (void)
|
||||||
{
|
{
|
||||||
/* reset time */
|
/* reset time */
|
||||||
lastdec = READ_TIMER;
|
lastdec = READ_TIMER();
|
||||||
timestamp = 0;
|
timestamp = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
ulong get_timer_masked (void)
|
ulong get_timer_masked (void)
|
||||||
{
|
{
|
||||||
ulong now = READ_TIMER;
|
ulong now = READ_TIMER();
|
||||||
|
|
||||||
if (lastdec >= now) {
|
if (lastdec >= now) {
|
||||||
/* normal mode */
|
/* normal mode */
|
||||||
|
|
|
@ -25,57 +25,51 @@
|
||||||
#include <s3c2410.h>
|
#include <s3c2410.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL1
|
||||||
|
#define UART_NR S3C24X0_UART0
|
||||||
|
|
||||||
|
#elif CONFIG_SERIAL2
|
||||||
|
# if defined(CONFIG_TRAB)
|
||||||
|
# #error "TRAB supports only CONFIG_SERIAL1"
|
||||||
|
# endif
|
||||||
|
#define UART_NR S3C24X0_UART1
|
||||||
|
|
||||||
|
#elif CONFIG_SERIAL3
|
||||||
|
# if defined(CONFIG_TRAB)
|
||||||
|
# #error "TRAB supports only CONFIG_SERIAL1"
|
||||||
|
# endif
|
||||||
|
#define UART_NR S3C24X0_UART2
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error "Bad: you didn't configure serial ..."
|
||||||
|
#endif
|
||||||
|
|
||||||
void serial_setbrg (void)
|
void serial_setbrg (void)
|
||||||
{
|
{
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
|
||||||
int i;
|
int i;
|
||||||
unsigned int reg = 0;
|
unsigned int reg = 0;
|
||||||
|
|
||||||
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
|
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
|
||||||
reg = get_PCLK() / (16 * gd->baudrate) - 1;
|
reg = get_PCLK() / (16 * gd->baudrate) - 1;
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL1
|
|
||||||
/* FIFO enable, Tx/Rx FIFO clear */
|
/* FIFO enable, Tx/Rx FIFO clear */
|
||||||
rUFCON0 = 0x07;
|
uart->UFCON = 0x07;
|
||||||
rUMCON0 = 0x0;
|
uart->UMCON = 0x0;
|
||||||
/* Normal,No parity,1 stop,8 bit */
|
/* Normal,No parity,1 stop,8 bit */
|
||||||
rULCON0 = 0x3;
|
uart->ULCON = 0x3;
|
||||||
/*
|
/*
|
||||||
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
|
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
|
||||||
* normal,interrupt or polling
|
* normal,interrupt or polling
|
||||||
*/
|
*/
|
||||||
rUCON0 = 0x245;
|
uart->UCON = 0x245;
|
||||||
rUBRDIV0 = reg;
|
uart->UBRDIV = reg;
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
rUMCON0 = 0x1; /* RTS up */
|
uart->UMCON = 0x1; /* RTS up */
|
||||||
#endif
|
#endif
|
||||||
for (i = 0; i < 100; i++);
|
for (i = 0; i < 100; i++);
|
||||||
#elif CONFIG_SERIAL2
|
|
||||||
# if defined(CONFIG_TRAB)
|
|
||||||
# #error "TRAB supports only CONFIG_SERIAL1"
|
|
||||||
# endif
|
|
||||||
/* FIFO enable, Tx/Rx FIFO clear */
|
|
||||||
rUFCON1 = 0x06;
|
|
||||||
rUMCON1 = 0x0;
|
|
||||||
/* Normal,No parity,1 stop,8 bit */
|
|
||||||
rULCON1 = 0x3;
|
|
||||||
/*
|
|
||||||
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
|
|
||||||
* normal,interrupt or polling
|
|
||||||
*/
|
|
||||||
rUCON1 = 0x245;
|
|
||||||
rUBRDIV1 = reg;
|
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
|
||||||
rUMCON1 = 0x1; /* RTS up */
|
|
||||||
#endif
|
|
||||||
for (i = 0; i < 100; i++);
|
|
||||||
#else
|
|
||||||
#error "Bad: you didn't configure serial ..."
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -97,15 +91,12 @@ int serial_init (void)
|
||||||
*/
|
*/
|
||||||
int serial_getc (void)
|
int serial_getc (void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_SERIAL1
|
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
|
||||||
while (!(rUTRSTAT0 & 0x1));
|
|
||||||
|
/* wait for character to arrive */
|
||||||
|
while (!(uart->UTRSTAT & 0x1));
|
||||||
|
|
||||||
return rURXH0 & 0xff;
|
return uart->URXH & 0xff;
|
||||||
#elif CONFIG_SERIAL2
|
|
||||||
while (!(rUTRSTAT1 & 0x1));
|
|
||||||
|
|
||||||
return rURXH1 & 0xff;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
|
@ -146,33 +137,22 @@ void enable_putc(void)
|
||||||
*/
|
*/
|
||||||
void serial_putc (const char c)
|
void serial_putc (const char c)
|
||||||
{
|
{
|
||||||
|
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
|
||||||
#ifdef CONFIG_MODEM_SUPPORT
|
#ifdef CONFIG_MODEM_SUPPORT
|
||||||
if (be_quiet)
|
if (be_quiet)
|
||||||
return;
|
return;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL1
|
/* wait for room in the tx FIFO */
|
||||||
/* wait for room in the tx FIFO on SERIAL1 */
|
while (!(uart->UTRSTAT & 0x2));
|
||||||
while (!(rUTRSTAT0 & 0x2));
|
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
/* Wait for CTS up */
|
/* Wait for CTS up */
|
||||||
while(hwflow && !(rUMSTAT0 & 0x1))
|
while(hwflow && !(uart->UMSTAT & 0x1))
|
||||||
;
|
;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
rUTXH0 = c;
|
uart->UTXH = c;
|
||||||
#elif CONFIG_SERIAL2
|
|
||||||
/* wait for room in the tx FIFO on SERIAL2 */
|
|
||||||
while (!(rUTRSTAT1 & 0x2));
|
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
|
||||||
/* Wait for CTS up */
|
|
||||||
while(hwflow && !(rUMSTAT1 & 0x1))
|
|
||||||
;
|
|
||||||
#endif
|
|
||||||
rUTXH1 = c;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* If \n, also do \r */
|
/* If \n, also do \r */
|
||||||
if (c == '\n')
|
if (c == '\n')
|
||||||
|
@ -184,11 +164,9 @@ void serial_putc (const char c)
|
||||||
*/
|
*/
|
||||||
int serial_tstc (void)
|
int serial_tstc (void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_SERIAL1
|
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
|
||||||
return rUTRSTAT0 & 0x1;
|
|
||||||
#elif CONFIG_SERIAL2
|
return uart->UTRSTAT & 0x1;
|
||||||
return rUTRSTAT1 & 0x1;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
|
@ -51,12 +51,13 @@
|
||||||
|
|
||||||
static ulong get_PLLCLK(int pllreg)
|
static ulong get_PLLCLK(int pllreg)
|
||||||
{
|
{
|
||||||
|
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||||
ulong r, m, p, s;
|
ulong r, m, p, s;
|
||||||
|
|
||||||
if (pllreg == MPLL)
|
if (pllreg == MPLL)
|
||||||
r = rMPLLCON;
|
r = clk_power->MPLLCON;
|
||||||
else if (pllreg == UPLL)
|
else if (pllreg == UPLL)
|
||||||
r = rUPLLCON;
|
r = clk_power->UPLLCON;
|
||||||
else
|
else
|
||||||
hang();
|
hang();
|
||||||
|
|
||||||
|
@ -76,17 +77,17 @@ ulong get_FCLK(void)
|
||||||
/* return HCLK frequency */
|
/* return HCLK frequency */
|
||||||
ulong get_HCLK(void)
|
ulong get_HCLK(void)
|
||||||
{
|
{
|
||||||
ulong clkdiv = rCLKDIVN;
|
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||||
|
|
||||||
return((clkdiv & 0x2) ? get_FCLK()/2 : get_FCLK());
|
return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
|
||||||
}
|
}
|
||||||
|
|
||||||
/* return PCLK frequency */
|
/* return PCLK frequency */
|
||||||
ulong get_PCLK(void)
|
ulong get_PCLK(void)
|
||||||
{
|
{
|
||||||
ulong clkdiv = rCLKDIVN;
|
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
|
||||||
|
|
||||||
return((clkdiv & 0x1) ? get_HCLK()/2 : get_HCLK());
|
return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
|
||||||
}
|
}
|
||||||
|
|
||||||
/* return UCLK frequency */
|
/* return UCLK frequency */
|
||||||
|
|
|
@ -35,7 +35,7 @@ include $(TOPDIR)/config.mk
|
||||||
LIB = lib$(CPU).a
|
LIB = lib$(CPU).a
|
||||||
|
|
||||||
START = start.S
|
START = start.S
|
||||||
OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o status_led.o
|
OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o
|
||||||
|
|
||||||
all: .depend $(START) $(LIB)
|
all: .depend $(START) $(LIB)
|
||||||
|
|
||||||
|
|
|
@ -1,161 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2000-2002 Wolfgang Denk, DENX Software Engineering, wd@denx.de
|
|
||||||
* (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* File: status_led.c
|
|
||||||
*
|
|
||||||
* Discription: Blink a board led to show boot progress. Led's
|
|
||||||
* are connected via the MIOS module.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <mpc5xx.h>
|
|
||||||
#include <status_led.h>
|
|
||||||
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
|
||||||
|
|
||||||
typedef struct {
|
|
||||||
ulong mask;
|
|
||||||
int state;
|
|
||||||
int period;
|
|
||||||
int cnt;
|
|
||||||
} led_dev_t;
|
|
||||||
|
|
||||||
led_dev_t led_dev[] = {
|
|
||||||
{ STATUS_LED_BIT,
|
|
||||||
STATUS_LED_STATE,
|
|
||||||
STATUS_LED_PERIOD,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#if defined(STATUS_LED_BIT1)
|
|
||||||
{ STATUS_LED_BIT1,
|
|
||||||
STATUS_LED_STATE1,
|
|
||||||
STATUS_LED_PERIOD1,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
#if defined(STATUS_LED_BIT2)
|
|
||||||
{ STATUS_LED_BIT2,
|
|
||||||
STATUS_LED_STATE2,
|
|
||||||
STATUS_LED_PERIOD2,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
#if defined(STATUS_LED_BIT3)
|
|
||||||
{ STATUS_LED_BIT3,
|
|
||||||
STATUS_LED_STATE3,
|
|
||||||
STATUS_LED_PERIOD3,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t))
|
|
||||||
|
|
||||||
static int status_led_init_done = 0;
|
|
||||||
|
|
||||||
static void status_led_init (void)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i=0; i<MAX_LED_DEV; ++i) {
|
|
||||||
led_dev_t *ld = &led_dev[i];
|
|
||||||
|
|
||||||
immr->STATUS_LED_DIR = STATUS_LED_BIT;
|
|
||||||
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
if (ld->state == STATUS_LED_ON)
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
else
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#else
|
|
||||||
if (ld->state == STATUS_LED_ON)
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
else
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
status_led_init_done = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
void status_led_tick (ulong timestamp)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (!status_led_init_done)
|
|
||||||
status_led_init();
|
|
||||||
|
|
||||||
for (i=0; i<MAX_LED_DEV; ++i) {
|
|
||||||
led_dev_t *ld = &led_dev[i];
|
|
||||||
|
|
||||||
if (ld->state != STATUS_LED_BLINKING)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
if (++(ld->cnt) >= ld->period) {
|
|
||||||
immr->STATUS_LED_DAT ^= ld->mask;
|
|
||||||
ld->cnt -= ld->period;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void status_led_set (int led, int state)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
|
||||||
led_dev_t *ld;
|
|
||||||
|
|
||||||
if (led < 0 || led >= MAX_LED_DEV)
|
|
||||||
return;
|
|
||||||
|
|
||||||
if (!status_led_init_done)
|
|
||||||
status_led_init();
|
|
||||||
|
|
||||||
ld = &led_dev[led];
|
|
||||||
|
|
||||||
switch (state) {
|
|
||||||
default:
|
|
||||||
return;
|
|
||||||
case STATUS_LED_BLINKING:
|
|
||||||
ld->cnt = 0; /* always start with full period */
|
|
||||||
/* fall through */ /* always start with LED _ON_ */
|
|
||||||
case STATUS_LED_ON:
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#else
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
case STATUS_LED_OFF:
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#else
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
ld->state = state;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_STATUS_LED */
|
|
|
@ -28,7 +28,7 @@ LIB = lib$(CPU).a
|
||||||
START = start.o kgdb.o
|
START = start.o kgdb.o
|
||||||
OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
|
OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
|
||||||
interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
|
interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
|
||||||
bedbug_603e.o status_led.o pci.o spi.o
|
bedbug_603e.o pci.o spi.o
|
||||||
|
|
||||||
all: .depend $(START) $(LIB)
|
all: .depend $(START) $(LIB)
|
||||||
|
|
||||||
|
|
|
@ -333,7 +333,7 @@ int eth_init(bd_t *bis)
|
||||||
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
|
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
|
||||||
SCC_GSMRL_ENT);
|
SCC_GSMRL_ENT);
|
||||||
|
|
||||||
return 1;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -161,6 +161,7 @@ _hrcw_table:
|
||||||
.globl _start
|
.globl _start
|
||||||
_start:
|
_start:
|
||||||
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
|
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
|
||||||
|
nop
|
||||||
b boot_cold
|
b boot_cold
|
||||||
|
|
||||||
. = EXC_OFF_SYS_RESET + 0x10
|
. = EXC_OFF_SYS_RESET + 0x10
|
||||||
|
@ -171,6 +172,18 @@ _start_warm:
|
||||||
b boot_warm
|
b boot_warm
|
||||||
|
|
||||||
boot_cold:
|
boot_cold:
|
||||||
|
#if defined(CONFIG_MPC8260ADS)
|
||||||
|
lis r3, CFG_DEFAULT_IMMR@h
|
||||||
|
nop
|
||||||
|
lwz r4, 0(r3)
|
||||||
|
nop
|
||||||
|
rlwinm r4, r4, 0, 8, 5
|
||||||
|
nop
|
||||||
|
oris r4, r4, 0x0200
|
||||||
|
nop
|
||||||
|
stw r4, 0(r3)
|
||||||
|
nop
|
||||||
|
#endif /* CONFIG_MPC8260ADS */
|
||||||
boot_warm:
|
boot_warm:
|
||||||
mfmsr r5 /* save msr contents */
|
mfmsr r5 /* save msr contents */
|
||||||
|
|
||||||
|
|
|
@ -1,160 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <status_led.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The purpose of this code is to signal the operational status of a
|
|
||||||
* target which usually boots over the network; while running in
|
|
||||||
* PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
|
|
||||||
* message has been received, the LED is turned off. The Linux
|
|
||||||
* kernel, once it is running, will start blinking the LED again,
|
|
||||||
* with another frequency.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
|
||||||
|
|
||||||
typedef struct {
|
|
||||||
ulong mask;
|
|
||||||
int state;
|
|
||||||
int period;
|
|
||||||
int cnt;
|
|
||||||
} led_dev_t;
|
|
||||||
|
|
||||||
led_dev_t led_dev[] = {
|
|
||||||
{ STATUS_LED_BIT,
|
|
||||||
STATUS_LED_STATE,
|
|
||||||
STATUS_LED_PERIOD,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#if defined(STATUS_LED_BIT1)
|
|
||||||
{ STATUS_LED_BIT1,
|
|
||||||
STATUS_LED_STATE1,
|
|
||||||
STATUS_LED_PERIOD1,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
#if defined(STATUS_LED_BIT2)
|
|
||||||
{ STATUS_LED_BIT2,
|
|
||||||
STATUS_LED_STATE2,
|
|
||||||
STATUS_LED_PERIOD2,
|
|
||||||
0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t))
|
|
||||||
|
|
||||||
static int status_led_init_done = 0;
|
|
||||||
|
|
||||||
static void status_led_init (void)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i=0; i<MAX_LED_DEV; ++i) {
|
|
||||||
led_dev_t *ld = &led_dev[i];
|
|
||||||
|
|
||||||
immr->STATUS_LED_PAR &= ~(ld->mask);
|
|
||||||
#ifdef STATUS_LED_ODR
|
|
||||||
immr->STATUS_LED_ODR &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
if (ld->state == STATUS_LED_ON)
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
else
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#else
|
|
||||||
if (ld->state == STATUS_LED_ON)
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
else
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
immr->STATUS_LED_DIR |= ld->mask ;
|
|
||||||
}
|
|
||||||
|
|
||||||
status_led_init_done = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
void status_led_tick (ulong timestamp)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (!status_led_init_done)
|
|
||||||
status_led_init();
|
|
||||||
|
|
||||||
for (i=0; i<MAX_LED_DEV; ++i) {
|
|
||||||
led_dev_t *ld = &led_dev[i];
|
|
||||||
|
|
||||||
if (ld->state != STATUS_LED_BLINKING)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
if (++(ld->cnt) >= ld->period) {
|
|
||||||
immr->STATUS_LED_DAT ^= ld->mask;
|
|
||||||
ld->cnt -= ld->period;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void status_led_set (int led, int state)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
|
||||||
led_dev_t *ld;
|
|
||||||
|
|
||||||
if (led < 0 || led >= MAX_LED_DEV)
|
|
||||||
return;
|
|
||||||
|
|
||||||
if (!status_led_init_done)
|
|
||||||
status_led_init();
|
|
||||||
|
|
||||||
ld = &led_dev[led];
|
|
||||||
|
|
||||||
switch (state) {
|
|
||||||
default:
|
|
||||||
return;
|
|
||||||
case STATUS_LED_BLINKING:
|
|
||||||
ld->cnt = 0; /* always start with full period */
|
|
||||||
/* fall through */ /* always start with LED _ON_ */
|
|
||||||
case STATUS_LED_ON:
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#else
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
case STATUS_LED_OFF:
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#else
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
ld->state = state;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_STATUS_LED */
|
|
|
@ -30,7 +30,7 @@ LIB = lib$(CPU).a
|
||||||
START = start.o kgdb.o
|
START = start.o kgdb.o
|
||||||
OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
|
OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
|
||||||
fec.o i2c.o interrupts.o lcd.o scc.o \
|
fec.o i2c.o interrupts.o lcd.o scc.o \
|
||||||
serial.o speed.o spi.o status_led.o\
|
serial.o speed.o spi.o \
|
||||||
traps.o upatch.o video.o
|
traps.o upatch.o video.o
|
||||||
|
|
||||||
all: .depend $(START) $(LIB)
|
all: .depend $(START) $(LIB)
|
||||||
|
|
|
@ -38,7 +38,8 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
|
||||||
pcnet.o plb2800_eth.o \
|
pcnet.o plb2800_eth.o \
|
||||||
s3c24x0_i2c.o sed13806.o serial.o \
|
s3c24x0_i2c.o sed13806.o serial.o \
|
||||||
smc91111.o smiLynxEM.o sym53c8xx.o \
|
smc91111.o smiLynxEM.o sym53c8xx.o \
|
||||||
ti_pci1410a.o tigon3.o w83c553f.o
|
ti_pci1410a.o tigon3.o w83c553f.o \
|
||||||
|
status_led.o
|
||||||
|
|
||||||
## Disabled for now:
|
## Disabled for now:
|
||||||
## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \
|
## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \
|
||||||
|
|
|
@ -39,103 +39,114 @@
|
||||||
|
|
||||||
#ifdef CONFIG_HARD_I2C
|
#ifdef CONFIG_HARD_I2C
|
||||||
|
|
||||||
#define IIC_WRITE 0
|
#define I2C_WRITE 0
|
||||||
#define IIC_READ 1
|
#define I2C_READ 1
|
||||||
|
|
||||||
#define IIC_OK 0
|
#define I2C_OK 0
|
||||||
#define IIC_NOK 1
|
#define I2C_NOK 1
|
||||||
#define IIC_NACK 2
|
#define I2C_NACK 2
|
||||||
#define IIC_NOK_LA 3 /* Lost arbitration */
|
#define I2C_NOK_LA 3 /* Lost arbitration */
|
||||||
#define IIC_NOK_TOUT 4 /* time out */
|
#define I2C_NOK_TOUT 4 /* time out */
|
||||||
|
|
||||||
#define IICSTAT_BSY 0x20 /* Busy bit */
|
#define I2CSTAT_BSY 0x20 /* Busy bit */
|
||||||
#define IICSTAT_NACK 0x01 /* Nack bit */
|
#define I2CSTAT_NACK 0x01 /* Nack bit */
|
||||||
#define IICCON_IRPND 0x10 /* Interrupt pending bit */
|
#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
|
||||||
#define IIC_MODE_MT 0xC0 /* Master Transmit Mode */
|
#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
|
||||||
#define IIC_MODE_MR 0x80 /* Master Receive Mode */
|
#define I2C_MODE_MR 0x80 /* Master Receive Mode */
|
||||||
#define IIC_START_STOP 0x20 /* START / STOP */
|
#define I2C_START_STOP 0x20 /* START / STOP */
|
||||||
#define IIC_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
|
#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
|
||||||
|
|
||||||
#define IIC_TIMEOUT 1 /* 1 seconde */
|
#define I2C_TIMEOUT 1 /* 1 seconde */
|
||||||
|
|
||||||
|
|
||||||
static int GetIICSDA(void)
|
static int GetI2CSDA(void)
|
||||||
{
|
{
|
||||||
return (rGPEDAT & 0x8000) >> 15;
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
|
return (gpio->GPEDAT & 0x8000) >> 15;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
static void SetIICSDA(int x)
|
static void SetI2CSDA(int x)
|
||||||
{
|
{
|
||||||
rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
|
rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static void SetIICSCL(int x)
|
static void SetI2CSCL(int x)
|
||||||
{
|
{
|
||||||
rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14;
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
|
|
||||||
|
gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static int WaitForXfer(void)
|
static int WaitForXfer(void)
|
||||||
{
|
{
|
||||||
|
S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
|
||||||
int i, status;
|
int i, status;
|
||||||
|
|
||||||
i = IIC_TIMEOUT * 1000;
|
i = I2C_TIMEOUT * 1000;
|
||||||
status = rIICCON;
|
status = i2c->IICCON;
|
||||||
while ((i > 0) && !(status & IICCON_IRPND)) {
|
while ((i > 0) && !(status & I2CCON_IRPND)) {
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
status = rIICCON;
|
status = i2c->IICCON;
|
||||||
i--;
|
i--;
|
||||||
}
|
}
|
||||||
|
|
||||||
return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT;
|
return(status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int IsACK(void)
|
static int IsACK(void)
|
||||||
{
|
{
|
||||||
return(!(rIICSTAT & IICSTAT_NACK));
|
S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
|
||||||
|
|
||||||
|
return(!(i2c->IICSTAT & I2CSTAT_NACK));
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ReadWriteByte(void)
|
static void ReadWriteByte(void)
|
||||||
{
|
{
|
||||||
rIICCON &= ~IICCON_IRPND;
|
S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
|
||||||
|
|
||||||
|
i2c->IICCON &= ~I2CCON_IRPND;
|
||||||
}
|
}
|
||||||
|
|
||||||
void i2c_init (int speed, int slaveadd)
|
void i2c_init (int speed, int slaveadd)
|
||||||
{
|
{
|
||||||
|
S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
|
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
|
||||||
ulong freq, pres = 16, div;
|
ulong freq, pres = 16, div;
|
||||||
int i, status;
|
int i, status;
|
||||||
|
|
||||||
/* wait for some time to give previous transfer a chance to finish */
|
/* wait for some time to give previous transfer a chance to finish */
|
||||||
|
|
||||||
i = IIC_TIMEOUT * 1000;
|
i = I2C_TIMEOUT * 1000;
|
||||||
status = rIICSTAT;
|
status = i2c->IICSTAT;
|
||||||
while ((i > 0) && (status & IICSTAT_BSY)) {
|
while ((i > 0) && (status & I2CSTAT_BSY)) {
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
status = rIICSTAT;
|
status = i2c->IICSTAT;
|
||||||
i--;
|
i--;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((status & IICSTAT_BSY) || GetIICSDA() == 0) {
|
if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) {
|
||||||
ulong old_gpecon = rGPECON;
|
ulong old_gpecon = gpio->GPECON;
|
||||||
/* bus still busy probably by (most) previously interrupted transfer */
|
/* bus still busy probably by (most) previously interrupted transfer */
|
||||||
|
|
||||||
/* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */
|
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
|
||||||
rGPECON = (rGPECON & ~0xF0000000) | 0x10000000;
|
gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
|
||||||
|
|
||||||
/* toggle IICSCL until bus idle */
|
/* toggle I2CSCL until bus idle */
|
||||||
SetIICSCL(0); udelay(1000);
|
SetI2CSCL(0); udelay(1000);
|
||||||
i = 10;
|
i = 10;
|
||||||
while ((i > 0) && (GetIICSDA() != 1)) {
|
while ((i > 0) && (GetI2CSDA() != 1)) {
|
||||||
SetIICSCL(1); udelay(1000);
|
SetI2CSCL(1); udelay(1000);
|
||||||
SetIICSCL(0); udelay(1000);
|
SetI2CSCL(0); udelay(1000);
|
||||||
i--;
|
i--;
|
||||||
}
|
}
|
||||||
SetIICSCL(1); udelay(1000);
|
SetI2CSCL(1); udelay(1000);
|
||||||
|
|
||||||
/* restore pin functions */
|
/* restore pin functions */
|
||||||
rGPECON = old_gpecon;
|
gpio->GPECON = old_gpecon;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* calculate prescaler and divisor values */
|
/* calculate prescaler and divisor values */
|
||||||
|
@ -150,13 +161,13 @@ void i2c_init (int speed, int slaveadd)
|
||||||
|
|
||||||
/* set prescaler, divisor according to freq, also set
|
/* set prescaler, divisor according to freq, also set
|
||||||
ACKGEN, IRQ */
|
ACKGEN, IRQ */
|
||||||
rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
|
i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
|
||||||
|
|
||||||
/* init to SLAVE REVEIVE and set slaveaddr */
|
/* init to SLAVE REVEIVE and set slaveaddr */
|
||||||
rIICSTAT = 0;
|
i2c->IICSTAT = 0;
|
||||||
rIICADD = slaveadd;
|
i2c->IICADD = slaveadd;
|
||||||
/* program Master Transmit (and implicit STOP) */
|
/* program Master Transmit (and implicit STOP) */
|
||||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
|
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -176,142 +187,143 @@ int i2c_transfer(unsigned char cmd_type,
|
||||||
unsigned char data[],
|
unsigned char data[],
|
||||||
unsigned short data_len)
|
unsigned short data_len)
|
||||||
{
|
{
|
||||||
|
S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
|
||||||
int i, status, result;
|
int i, status, result;
|
||||||
|
|
||||||
if (data == 0 || data_len == 0) {
|
if (data == 0 || data_len == 0) {
|
||||||
/*Don't support data transfer of no length or to address 0*/
|
/*Don't support data transfer of no length or to address 0*/
|
||||||
printf( "i2c_transfer: bad call\n" );
|
printf( "i2c_transfer: bad call\n" );
|
||||||
return IIC_NOK;
|
return I2C_NOK;
|
||||||
}
|
}
|
||||||
|
|
||||||
//CheckDelay();
|
//CheckDelay();
|
||||||
|
|
||||||
/* Check I2C bus idle */
|
/* Check I2C bus idle */
|
||||||
i = IIC_TIMEOUT * 1000;
|
i = I2C_TIMEOUT * 1000;
|
||||||
status = rIICSTAT;
|
status = i2c->IICSTAT;
|
||||||
while ((i > 0) && (status & IICSTAT_BSY)) {
|
while ((i > 0) && (status & I2CSTAT_BSY)) {
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
status = rIICSTAT;
|
status = i2c->IICSTAT;
|
||||||
i--;
|
i--;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
if (status & IICSTAT_BSY) {
|
if (status & I2CSTAT_BSY) {
|
||||||
result = IIC_NOK_TOUT;
|
result = I2C_NOK_TOUT;
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
rIICCON |= 0x80;
|
i2c->IICCON |= 0x80;
|
||||||
|
|
||||||
result = IIC_OK;
|
result = I2C_OK;
|
||||||
|
|
||||||
switch (cmd_type) {
|
switch (cmd_type) {
|
||||||
case IIC_WRITE:
|
case I2C_WRITE:
|
||||||
if (addr && addr_len) {
|
if (addr && addr_len) {
|
||||||
rIICDS = chip;
|
i2c->IICDS = chip;
|
||||||
/* send START */
|
/* send START */
|
||||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
|
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
|
||||||
i = 0;
|
i = 0;
|
||||||
while ((i < addr_len) && (result == IIC_OK)) {
|
while ((i < addr_len) && (result == I2C_OK)) {
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
rIICDS = addr[i];
|
i2c->IICDS = addr[i];
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
i = 0;
|
i = 0;
|
||||||
while ((i < data_len) && (result == IIC_OK)) {
|
while ((i < data_len) && (result == I2C_OK)) {
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
rIICDS = data[i];
|
i2c->IICDS = data[i];
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
rIICDS = chip;
|
i2c->IICDS = chip;
|
||||||
/* send START */
|
/* send START */
|
||||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
|
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
|
||||||
i = 0;
|
i = 0;
|
||||||
while ((i < data_len) && (result = IIC_OK)) {
|
while ((i < data_len) && (result = I2C_OK)) {
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
rIICDS = data[i];
|
i2c->IICDS = data[i];
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (result == IIC_OK)
|
if (result == I2C_OK)
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
|
|
||||||
/* send STOP */
|
/* send STOP */
|
||||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
|
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case IIC_READ:
|
case I2C_READ:
|
||||||
if (addr && addr_len) {
|
if (addr && addr_len) {
|
||||||
rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
|
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
|
||||||
rIICDS = chip;
|
i2c->IICDS = chip;
|
||||||
/* send START */
|
/* send START */
|
||||||
rIICSTAT |= IIC_START_STOP;
|
i2c->IICSTAT |= I2C_START_STOP;
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
if (IsACK()) {
|
if (IsACK()) {
|
||||||
i = 0;
|
i = 0;
|
||||||
while ((i < addr_len) && (result == IIC_OK)) {
|
while ((i < addr_len) && (result == I2C_OK)) {
|
||||||
rIICDS = addr[i];
|
i2c->IICDS = addr[i];
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
|
|
||||||
rIICDS = chip;
|
i2c->IICDS = chip;
|
||||||
/* resend START */
|
/* resend START */
|
||||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP;
|
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP;
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
i = 0;
|
i = 0;
|
||||||
while ((i < data_len) && (result == IIC_OK)) {
|
while ((i < data_len) && (result == I2C_OK)) {
|
||||||
/* disable ACK for final READ */
|
/* disable ACK for final READ */
|
||||||
if (i == data_len - 1)
|
if (i == data_len - 1)
|
||||||
rIICCON &= ~0x80;
|
i2c->IICCON &= ~0x80;
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
data[i] = rIICDS;
|
data[i] = i2c->IICDS;
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
result = IIC_NACK;
|
result = I2C_NACK;
|
||||||
}
|
}
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
|
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
|
||||||
rIICDS = chip;
|
i2c->IICDS = chip;
|
||||||
/* send START */
|
/* send START */
|
||||||
rIICSTAT |= IIC_START_STOP;
|
i2c->IICSTAT |= I2C_START_STOP;
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
|
|
||||||
if (IsACK()) {
|
if (IsACK()) {
|
||||||
i = 0;
|
i = 0;
|
||||||
while ((i < data_len) && (result == IIC_OK)) {
|
while ((i < data_len) && (result == I2C_OK)) {
|
||||||
/* disable ACK for final READ */
|
/* disable ACK for final READ */
|
||||||
if (i == data_len - 1)
|
if (i == data_len - 1)
|
||||||
rIICCON &= ~0x80;
|
i2c->IICCON &= ~0x80;
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
result = WaitForXfer();
|
result = WaitForXfer();
|
||||||
data[i] = rIICDS;
|
data[i] = i2c->IICDS;
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
result = IIC_NACK;
|
result = I2C_NACK;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* send STOP */
|
/* send STOP */
|
||||||
rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
|
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
|
||||||
ReadWriteByte();
|
ReadWriteByte();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
printf( "i2c_transfer: bad call\n" );
|
printf( "i2c_transfer: bad call\n" );
|
||||||
result = IIC_NOK;
|
result = I2C_NOK;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -329,7 +341,7 @@ int i2c_probe (uchar chip)
|
||||||
* address was <ACK>ed (i.e. there was a chip at that address which
|
* address was <ACK>ed (i.e. there was a chip at that address which
|
||||||
* drove the data line low).
|
* drove the data line low).
|
||||||
*/
|
*/
|
||||||
return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK);
|
return(i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
|
||||||
}
|
}
|
||||||
|
|
||||||
int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||||
|
@ -365,7 +377,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||||
if( alen > 0 )
|
if( alen > 0 )
|
||||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
||||||
#endif
|
#endif
|
||||||
if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
|
if( (ret = i2c_transfer(I2C_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
|
||||||
printf( "I2c read: failed %d\n", ret);
|
printf( "I2c read: failed %d\n", ret);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
@ -403,7 +415,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||||
if( alen > 0 )
|
if( alen > 0 )
|
||||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
||||||
#endif
|
#endif
|
||||||
return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
|
return (i2c_transfer(I2C_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_HARD_I2C */
|
#endif /* CONFIG_HARD_I2C */
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2000
|
* (C) Copyright 2000-2003
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
@ -22,13 +22,12 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <mpc8xx.h>
|
|
||||||
#include <status_led.h>
|
#include <status_led.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The purpose of this code is to signal the operational status of a
|
* The purpose of this code is to signal the operational status of a
|
||||||
* target which usually boots over the network; while running in
|
* target which usually boots over the network; while running in
|
||||||
* PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
|
* U-Boot, a status LED is blinking. As soon as a valid BOOTP reply
|
||||||
* message has been received, the LED is turned off. The Linux
|
* message has been received, the LED is turned off. The Linux
|
||||||
* kernel, once it is running, will start blinking the LED again,
|
* kernel, once it is running, will start blinking the LED again,
|
||||||
* with another frequency.
|
* with another frequency.
|
||||||
|
@ -39,10 +38,10 @@
|
||||||
#ifdef CONFIG_STATUS_LED
|
#ifdef CONFIG_STATUS_LED
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
ulong mask;
|
led_id_t mask;
|
||||||
int state;
|
int state;
|
||||||
int period;
|
int period;
|
||||||
int cnt;
|
int cnt;
|
||||||
} led_dev_t;
|
} led_dev_t;
|
||||||
|
|
||||||
led_dev_t led_dev[] = {
|
led_dev_t led_dev[] = {
|
||||||
|
@ -80,89 +79,53 @@ static int status_led_init_done = 0;
|
||||||
|
|
||||||
static void status_led_init (void)
|
static void status_led_init (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
led_dev_t *ld;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i=0; i<MAX_LED_DEV; ++i) {
|
for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++)
|
||||||
led_dev_t *ld = &led_dev[i];
|
__led_init (ld->mask, ld->state);
|
||||||
|
status_led_init_done = 1;
|
||||||
immr->STATUS_LED_PAR &= ~(ld->mask);
|
|
||||||
#ifdef STATUS_LED_ODR
|
|
||||||
immr->STATUS_LED_ODR &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
if (ld->state == STATUS_LED_ON)
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
else
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#else
|
|
||||||
if (ld->state == STATUS_LED_ON)
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
else
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
immr->STATUS_LED_DIR |= ld->mask ;
|
|
||||||
}
|
|
||||||
|
|
||||||
status_led_init_done = 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void status_led_tick (ulong timestamp)
|
void status_led_tick (ulong timestamp)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
led_dev_t *ld;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (!status_led_init_done)
|
if (!status_led_init_done)
|
||||||
status_led_init();
|
status_led_init ();
|
||||||
|
|
||||||
for (i=0; i<MAX_LED_DEV; ++i) {
|
for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) {
|
||||||
led_dev_t *ld = &led_dev[i];
|
|
||||||
|
|
||||||
if (ld->state != STATUS_LED_BLINKING)
|
if (ld->state != STATUS_LED_BLINKING)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
|
if (++ld->cnt >= ld->period) {
|
||||||
|
__led_toggle (ld->mask);
|
||||||
|
ld->cnt -= ld->period;
|
||||||
|
}
|
||||||
|
|
||||||
if (++(ld->cnt) >= ld->period) {
|
|
||||||
immr->STATUS_LED_DAT ^= ld->mask;
|
|
||||||
ld->cnt -= ld->period;
|
|
||||||
}
|
}
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void status_led_set (int led, int state)
|
void status_led_set (int led, int state)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
led_dev_t *ld;
|
||||||
led_dev_t *ld;
|
|
||||||
|
|
||||||
if (led < 0 || led >= MAX_LED_DEV)
|
if (led < 0 || led >= MAX_LED_DEV)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (!status_led_init_done)
|
if (!status_led_init_done)
|
||||||
status_led_init();
|
status_led_init ();
|
||||||
|
|
||||||
ld = &led_dev[led];
|
ld = &led_dev[led];
|
||||||
|
|
||||||
switch (state) {
|
ld->state = state;
|
||||||
default:
|
if (state == STATUS_LED_BLINKING) {
|
||||||
return;
|
ld->cnt = 0; /* always start with full period */
|
||||||
case STATUS_LED_BLINKING:
|
state = STATUS_LED_ON; /* always start with LED _ON_ */
|
||||||
ld->cnt = 0; /* always start with full period */
|
}
|
||||||
/* fall through */ /* always start with LED _ON_ */
|
__led_set (ld->mask, state);
|
||||||
case STATUS_LED_ON:
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#else
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
case STATUS_LED_OFF:
|
|
||||||
#if (STATUS_LED_ACTIVE == 0)
|
|
||||||
immr->STATUS_LED_DAT |= ld->mask ;
|
|
||||||
#else
|
|
||||||
immr->STATUS_LED_DAT &= ~(ld->mask);
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
ld->state = state;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_STATUS_LED */
|
#endif /* CONFIG_STATUS_LED */
|
|
@ -0,0 +1,77 @@
|
||||||
|
/*
|
||||||
|
* asm/status_led.h
|
||||||
|
*
|
||||||
|
* MPC8xx/MPC8260/MPC5xx based status led support functions
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_STATUS_LED_H__
|
||||||
|
#define __ASM_STATUS_LED_H__
|
||||||
|
|
||||||
|
/* if not overriden */
|
||||||
|
#ifndef CONFIG_BOARD_SPECIFIC_LED
|
||||||
|
# if defined(CONFIG_8xx)
|
||||||
|
# include <mpc8xx.h>
|
||||||
|
# elif defined(CONFIG_8260)
|
||||||
|
# include <mpc8260.h>
|
||||||
|
# elif defined(CONFIG_5xx)
|
||||||
|
# include <mpc5xx.h>
|
||||||
|
# else
|
||||||
|
# error CPU specific Status LED header file missing.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* led_id_t is unsigned long mask */
|
||||||
|
typedef unsigned long led_id_t;
|
||||||
|
|
||||||
|
static inline void __led_init (led_id_t mask, int state)
|
||||||
|
{
|
||||||
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
|
|
||||||
|
#ifdef STATUS_LED_PAR
|
||||||
|
immr->STATUS_LED_PAR &= ~mask;
|
||||||
|
#endif
|
||||||
|
#ifdef STATUS_LED_ODR
|
||||||
|
immr->STATUS_LED_ODR &= ~mask;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (STATUS_LED_ACTIVE == 0)
|
||||||
|
if (state == STATUS_LED_ON)
|
||||||
|
immr->STATUS_LED_DAT &= ~mask;
|
||||||
|
else
|
||||||
|
immr->STATUS_LED_DAT |= mask;
|
||||||
|
#else
|
||||||
|
if (state == STATUS_LED_ON)
|
||||||
|
immr->STATUS_LED_DAT |= mask;
|
||||||
|
else
|
||||||
|
immr->STATUS_LED_DAT &= ~mask;
|
||||||
|
#endif
|
||||||
|
#ifdef STATUS_LED_DIR
|
||||||
|
immr->STATUS_LED_DIR |= mask;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void __led_toggle (led_id_t mask)
|
||||||
|
{
|
||||||
|
((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void __led_set (led_id_t mask, int state)
|
||||||
|
{
|
||||||
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
|
|
||||||
|
#if (STATUS_LED_ACTIVE == 0)
|
||||||
|
if (state == STATUS_LED_ON)
|
||||||
|
immr->STATUS_LED_DAT &= ~mask;
|
||||||
|
else
|
||||||
|
immr->STATUS_LED_DAT |= mask;
|
||||||
|
#else
|
||||||
|
if (state == STATUS_LED_ON)
|
||||||
|
immr->STATUS_LED_DAT |= mask;
|
||||||
|
else
|
||||||
|
immr->STATUS_LED_DAT &= ~mask;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASM_STATUS_LED_H__ */
|
|
@ -26,10 +26,6 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
|
||||||
* Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
#ifndef __CONFIG_H
|
||||||
#define __CONFIG_H
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
@ -77,23 +73,45 @@
|
||||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
|
||||||
|
#ifdef CONFIG_ETHER_ON_FCC
|
||||||
|
|
||||||
|
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
|
||||||
|
|
||||||
#if (CONFIG_ETHER_INDEX == 2)
|
#if (CONFIG_ETHER_INDEX == 2)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* - Rx-CLK is CLK13
|
* - Rx-CLK is CLK13
|
||||||
* - Tx-CLK is CLK14
|
* - Tx-CLK is CLK14
|
||||||
* - Select bus for bd/buffers (see 28-13)
|
* - Select bus for bd/buffers (see 28-13)
|
||||||
* - Half duplex
|
* - Full duplex
|
||||||
*/
|
*/
|
||||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||||
# define CFG_CPMFCR_RAMTYPE 0
|
# define CFG_CPMFCR_RAMTYPE 0
|
||||||
# define CFG_FCC_PSMR 0
|
# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||||
|
|
||||||
#endif /* CONFIG_ETHER_INDEX */
|
#endif /* CONFIG_ETHER_INDEX */
|
||||||
|
|
||||||
|
#define CONFIG_MII /* MII PHY management */
|
||||||
|
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||||
|
/*
|
||||||
|
* GPIO pins used for bit-banged MII communications
|
||||||
|
*/
|
||||||
|
#define MDIO_PORT 2 /* Port C */
|
||||||
|
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
|
||||||
|
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
|
||||||
|
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
|
||||||
|
|
||||||
|
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
|
||||||
|
else iop->pdat &= ~0x00400000
|
||||||
|
|
||||||
|
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
|
||||||
|
else iop->pdat &= ~0x00200000
|
||||||
|
|
||||||
|
#define MIIDELAY udelay(1)
|
||||||
|
|
||||||
|
#endif /* CONFIG_ETHER_ON_FCC */
|
||||||
|
|
||||||
/* other options */
|
/* other options */
|
||||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||||
|
@ -172,9 +190,6 @@
|
||||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||||
|
|
||||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
|
||||||
/* for versions < 2.4.5-pre5 */
|
|
||||||
|
|
||||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||||
|
|
||||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||||
|
@ -239,8 +254,8 @@
|
||||||
|
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
# define CFG_ENV_IS_IN_FLASH 1
|
# define CFG_ENV_IS_IN_FLASH 1
|
||||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
|
# define CFG_ENV_SECT_SIZE 0x40000
|
||||||
# define CFG_ENV_SECT_SIZE 0x40000
|
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
|
||||||
#else
|
#else
|
||||||
# define CFG_ENV_IS_IN_NVRAM 1
|
# define CFG_ENV_IS_IN_NVRAM 1
|
||||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||||
|
|
|
@ -59,9 +59,13 @@
|
||||||
#define CONFIG_COMMANDS \
|
#define CONFIG_COMMANDS \
|
||||||
(CONFIG_CMD_DFL | \
|
(CONFIG_CMD_DFL | \
|
||||||
CFG_CMD_CACHE | \
|
CFG_CMD_CACHE | \
|
||||||
|
/*CFG_CMD_JFFS2 |*/ \
|
||||||
|
/*CFG_CMD_NAND |*/ \
|
||||||
CFG_CMD_EEPROM | \
|
CFG_CMD_EEPROM | \
|
||||||
CFG_CMD_I2C | \
|
CFG_CMD_I2C | \
|
||||||
|
/*CFG_CMD_USB |*/ \
|
||||||
CFG_CMD_REGINFO | \
|
CFG_CMD_REGINFO | \
|
||||||
|
CFG_CMD_DATE | \
|
||||||
CFG_CMD_ELF | \
|
CFG_CMD_ELF | \
|
||||||
CFG_CMD_BSP)
|
CFG_CMD_BSP)
|
||||||
|
|
||||||
|
@ -111,6 +115,24 @@
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
|
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
|
||||||
|
|
||||||
|
/************************************************************
|
||||||
|
* USB support
|
||||||
|
************************************************************/
|
||||||
|
#if 0
|
||||||
|
#define CONFIG_USB_OHCI
|
||||||
|
#define CONFIG_USB_KEYBOARD
|
||||||
|
#define CONFIG_USB_STORAGE
|
||||||
|
|
||||||
|
/* Enable needed helper functions */
|
||||||
|
#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************
|
||||||
|
* RTC
|
||||||
|
************************************************************/
|
||||||
|
#define CONFIG_RTC_S3C24X0 1
|
||||||
|
|
||||||
|
|
||||||
/* allow to overwrite serial and ethaddr */
|
/* allow to overwrite serial and ethaddr */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
@ -138,7 +160,7 @@
|
||||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
|
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
|
||||||
#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
|
#define CFG_MEMTEST_END 0x33F80000 /* 63.5 MB in DRAM */
|
||||||
#define CFG_ALT_MEMTEST
|
#define CFG_ALT_MEMTEST
|
||||||
#define CFG_LOAD_ADDR 0x33000000 /* default load address */
|
#define CFG_LOAD_ADDR 0x33000000 /* default load address */
|
||||||
|
|
||||||
|
@ -152,6 +174,13 @@
|
||||||
/* valid baudrates */
|
/* valid baudrates */
|
||||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
|
||||||
|
/************************************************************
|
||||||
|
* Ident
|
||||||
|
************************************************************/
|
||||||
|
/*#define VERSION_TAG "released"*/
|
||||||
|
#define VERSION_TAG "unstable"
|
||||||
|
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* Stack sizes
|
* Stack sizes
|
||||||
*
|
*
|
||||||
|
@ -204,6 +233,48 @@
|
||||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define MULTI_PURPOSE_SOCKET_ADDR 0
|
|
||||||
|
#define CFG_JFFS2_FIRST_BANK 0
|
||||||
|
#define CFG_JFFS2_NUM_BANKS 1
|
||||||
|
|
||||||
|
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* NAND flash settings
|
||||||
|
*/
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||||
|
|
||||||
|
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||||
|
#define SECTORSIZE 512
|
||||||
|
|
||||||
|
#define ADDR_COLUMN 1
|
||||||
|
#define ADDR_PAGE 2
|
||||||
|
#define ADDR_COLUMN_PAGE 3
|
||||||
|
|
||||||
|
#define NAND_ChipID_UNKNOWN 0x00
|
||||||
|
#define NAND_MAX_FLOORS 1
|
||||||
|
#define NAND_MAX_CHIPS 1
|
||||||
|
|
||||||
|
#define NAND_WAIT_READY(nand) NF_WaitRB()
|
||||||
|
|
||||||
|
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
|
||||||
|
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
|
||||||
|
|
||||||
|
|
||||||
|
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
|
||||||
|
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
|
||||||
|
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
|
||||||
|
#define WRITE_NAND(d, adr) NF_Write(d)
|
||||||
|
#define READ_NAND(adr) NF_Read()
|
||||||
|
/* the following functions are NOP's because S3C24X0 handles this in hardware */
|
||||||
|
#define NAND_CTL_CLRALE(nandptr)
|
||||||
|
#define NAND_CTL_SETALE(nandptr)
|
||||||
|
#define NAND_CTL_CLRCLE(nandptr)
|
||||||
|
#define NAND_CTL_SETCLE(nandptr)
|
||||||
|
|
||||||
|
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
|
||||||
|
#define CONFIG_MTD_NAND_ECC_JFFS2 1
|
||||||
|
|
||||||
|
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
|
@ -86,10 +86,14 @@
|
||||||
|
|
||||||
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
|
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
|
||||||
|
|
||||||
|
/* Use s3c2400's RTC */
|
||||||
|
#define CONFIG_RTC_S3C24X0 1
|
||||||
|
|
||||||
#ifndef USE_920T_MMU
|
#ifndef USE_920T_MMU
|
||||||
#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
|
#define CONFIG_COMMANDS_tmp ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
|
||||||
|
CFG_CMD_DATE)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL)
|
#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL | CFG_CMD_DATE)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
|
|
|
@ -67,16 +67,29 @@
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
|
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
|
||||||
|
|
||||||
|
/************************************************************
|
||||||
|
* RTC
|
||||||
|
************************************************************/
|
||||||
|
#define CONFIG_RTC_S3C24X0 1
|
||||||
|
|
||||||
/* allow to overwrite serial and ethaddr */
|
/* allow to overwrite serial and ethaddr */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
#ifndef USE_920T_MMU
|
/***********************************************************
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
|
* Command definition
|
||||||
#else
|
***********************************************************/
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
|
#define CONFIG_COMMANDS \
|
||||||
#endif
|
(CONFIG_CMD_DFL | \
|
||||||
|
CFG_CMD_CACHE | \
|
||||||
|
/*CFG_CMD_NAND |*/ \
|
||||||
|
/*CFG_CMD_EEPROM |*/ \
|
||||||
|
/*CFG_CMD_I2C |*/ \
|
||||||
|
/*CFG_CMD_USB |*/ \
|
||||||
|
CFG_CMD_REGINFO | \
|
||||||
|
CFG_CMD_DATE | \
|
||||||
|
CFG_CMD_ELF)
|
||||||
|
|
||||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
#include <cmd_confdefs.h>
|
#include <cmd_confdefs.h>
|
||||||
|
|
|
@ -90,6 +90,9 @@
|
||||||
|
|
||||||
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
|
#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
|
||||||
|
|
||||||
|
/* Use s3c2400's RTC */
|
||||||
|
#define CONFIG_RTC_S3C24X0 1
|
||||||
|
|
||||||
#ifdef CONFIG_HWFLOW
|
#ifdef CONFIG_HWFLOW
|
||||||
#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW
|
#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW
|
||||||
#else
|
#else
|
||||||
|
@ -105,11 +108,13 @@
|
||||||
#ifndef USE_920T_MMU
|
#ifndef USE_920T_MMU
|
||||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
|
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
|
||||||
CFG_CMD_BSP | \
|
CFG_CMD_BSP | \
|
||||||
|
CFG_CMD_DATE | \
|
||||||
CONFIG_COMMANDS_ADD_HWFLOW | \
|
CONFIG_COMMANDS_ADD_HWFLOW | \
|
||||||
CONFIG_COMMANDS_ADD_VFD )
|
CONFIG_COMMANDS_ADD_VFD )
|
||||||
#else
|
#else
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||||
CFG_CMD_BSP | \
|
CFG_CMD_BSP | \
|
||||||
|
CFG_CMD_DATE | \
|
||||||
CONFIG_COMMANDS_ADD_HWFLOW | \
|
CONFIG_COMMANDS_ADD_HWFLOW | \
|
||||||
CONFIG_COMMANDS_ADD_VFD )
|
CONFIG_COMMANDS_ADD_VFD )
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -1,13 +1,138 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
/************************************************
|
/************************************************
|
||||||
* NAME : s3c2400.h
|
* NAME : s3c2400.h
|
||||||
* Version : 3.7.2002
|
* Version : 31.3.2003
|
||||||
*
|
*
|
||||||
* Based on 24x.h for the Samsung Development Board
|
* Based on S3C2400X User's manual Rev 1.1
|
||||||
************************************************/
|
************************************************/
|
||||||
|
|
||||||
#ifndef __S3C2400_H__
|
#ifndef __S3C2400_H__
|
||||||
#define __S3C2400_H__
|
#define __S3C2400_H__
|
||||||
|
|
||||||
|
#define S3C24X0_UART_CHANNELS 2
|
||||||
|
#define S3C24X0_SPI_CHANNELS 1
|
||||||
|
#define PALETTE (0x14A00400) /* SJS */
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
S3C24X0_UART0,
|
||||||
|
S3C24X0_UART1,
|
||||||
|
} S3C24X0_UARTS_NR;
|
||||||
|
|
||||||
|
/* S3C2400 device base addresses */
|
||||||
|
#define S3C24X0_MEMCTL_BASE 0x14000000
|
||||||
|
#define S3C24X0_USB_HOST_BASE 0x14200000
|
||||||
|
#define S3C24X0_INTERRUPT_BASE 0x14400000
|
||||||
|
#define S3C24X0_DMA_BASE 0x14600000
|
||||||
|
#define S3C24X0_CLOCK_POWER_BASE 0x14800000
|
||||||
|
#define S3C24X0_LCD_BASE 0x14A00000
|
||||||
|
#define S3C24X0_UART_BASE 0x15000000
|
||||||
|
#define S3C24X0_TIMER_BASE 0x15100000
|
||||||
|
#define S3C24X0_USB_DEVICE_BASE 0x15200140
|
||||||
|
#define S3C24X0_WATCHDOG_BASE 0x15300000
|
||||||
|
#define S3C24X0_I2C_BASE 0x15400000
|
||||||
|
#define S3C24X0_I2S_BASE 0x15508000
|
||||||
|
#define S3C24X0_GPIO_BASE 0x15600000
|
||||||
|
#define S3C24X0_RTC_BASE 0x15700000
|
||||||
|
#define S3C24X0_ADC_BASE 0x15800000
|
||||||
|
#define S3C24X0_SPI_BASE 0x15900000
|
||||||
|
#define S3C2400_MMC_BASE 0x15A00000
|
||||||
|
|
||||||
|
/* include common stuff */
|
||||||
|
#include <s3c24x0.h>
|
||||||
|
|
||||||
|
|
||||||
|
static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
|
||||||
|
{
|
||||||
|
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
|
||||||
|
}
|
||||||
|
static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C2400_ADC * const S3C2400_GetBase_ADC(void)
|
||||||
|
{
|
||||||
|
return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void)
|
||||||
|
{
|
||||||
|
return (S3C2400_MMC * const)S3C2400_MMC_BASE;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if 0
|
||||||
/* Memory control */
|
/* Memory control */
|
||||||
#define rBWSCON (*(volatile unsigned *)0x14000000)
|
#define rBWSCON (*(volatile unsigned *)0x14000000)
|
||||||
#define rBANKCON0 (*(volatile unsigned *)0x14000004)
|
#define rBANKCON0 (*(volatile unsigned *)0x14000004)
|
||||||
|
@ -426,4 +551,5 @@
|
||||||
rINTPND;\
|
rINTPND;\
|
||||||
}
|
}
|
||||||
/* Wait until rINTPND is changed for the case that the ISR is very short. */
|
/* Wait until rINTPND is changed for the case that the ISR is very short. */
|
||||||
|
#endif
|
||||||
#endif /*__S3C2400_H__*/
|
#endif /*__S3C2400_H__*/
|
||||||
|
|
|
@ -1,494 +1,148 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
/************************************************
|
/************************************************
|
||||||
* NAME : s3c2410.h
|
* NAME : s3c2410.h
|
||||||
* Version : 3.7.2002
|
* Version : 31.3.2003
|
||||||
*
|
*
|
||||||
* Based on S3C2410X User's manual Rev 0.1
|
* Based on S3C2410X User's manual Rev 1.1
|
||||||
************************************************/
|
************************************************/
|
||||||
|
|
||||||
#ifndef __S3C2410_H__
|
#ifndef __S3C2410_H__
|
||||||
#define __S3C2410_H__
|
#define __S3C2410_H__
|
||||||
|
|
||||||
|
#define S3C24X0_UART_CHANNELS 3
|
||||||
|
#define S3C24X0_SPI_CHANNELS 2
|
||||||
|
|
||||||
/* Memory control */
|
/* S3C2410 only supports 512 Byte HW ECC */
|
||||||
#define rBWSCON (*(volatile unsigned *)0x48000000)
|
#define S3C2410_ECCSIZE 512
|
||||||
#define rBANKCON0 (*(volatile unsigned *)0x48000004)
|
#define S3C2410_ECCBYTES 3
|
||||||
#define rBANKCON1 (*(volatile unsigned *)0x48000008)
|
|
||||||
#define rBANKCON2 (*(volatile unsigned *)0x4800000C)
|
typedef enum {
|
||||||
#define rBANKCON3 (*(volatile unsigned *)0x48000010)
|
S3C24X0_UART0,
|
||||||
#define rBANKCON4 (*(volatile unsigned *)0x48000014)
|
S3C24X0_UART1,
|
||||||
#define rBANKCON5 (*(volatile unsigned *)0x48000018)
|
S3C24X0_UART2
|
||||||
#define rBANKCON6 (*(volatile unsigned *)0x4800001C)
|
} S3C24X0_UARTS_NR;
|
||||||
#define rBANKCON7 (*(volatile unsigned *)0x48000020)
|
|
||||||
#define rREFRESH (*(volatile unsigned *)0x48000024)
|
/* S3C2410 device base addresses */
|
||||||
#define rBANKSIZE (*(volatile unsigned *)0x48000028)
|
#define S3C24X0_MEMCTL_BASE 0x48000000
|
||||||
#define rMRSRB6 (*(volatile unsigned *)0x4800002C)
|
#define S3C24X0_USB_HOST_BASE 0x49000000
|
||||||
#define rMRSRB7 (*(volatile unsigned *)0x48000030)
|
#define S3C24X0_INTERRUPT_BASE 0x4A000000
|
||||||
|
#define S3C24X0_DMA_BASE 0x4B000000
|
||||||
|
#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
|
||||||
|
#define S3C24X0_LCD_BASE 0x4D000000
|
||||||
|
#define S3C2410_NAND_BASE 0x4E000000
|
||||||
|
#define S3C24X0_UART_BASE 0x50000000
|
||||||
|
#define S3C24X0_TIMER_BASE 0x51000000
|
||||||
|
#define S3C24X0_USB_DEVICE_BASE 0x52000140
|
||||||
|
#define S3C24X0_WATCHDOG_BASE 0x53000000
|
||||||
|
#define S3C24X0_I2C_BASE 0x54000000
|
||||||
|
#define S3C24X0_I2S_BASE 0x55000000
|
||||||
|
#define S3C24X0_GPIO_BASE 0x56000000
|
||||||
|
#define S3C24X0_RTC_BASE 0x57000000
|
||||||
|
#define S3C2410_ADC_BASE 0x58000000
|
||||||
|
#define S3C24X0_SPI_BASE 0x59000000
|
||||||
|
#define S3C2410_SDI_BASE 0x5A000000
|
||||||
|
|
||||||
|
|
||||||
/* USB HOST */
|
/* include common stuff */
|
||||||
#define rHcRevision (*(volatile unsigned *)0x49000000)
|
#include <s3c24x0.h>
|
||||||
#define rHcControl (*(volatile unsigned *)0x49000004)
|
|
||||||
#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
|
|
||||||
#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
|
|
||||||
#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
|
|
||||||
#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
|
|
||||||
#define rHcHCCA (*(volatile unsigned *)0x49000018)
|
|
||||||
#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
|
|
||||||
#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
|
|
||||||
#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
|
|
||||||
#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
|
|
||||||
#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
|
|
||||||
#define rHcDoneHead (*(volatile unsigned *)0x49000030)
|
|
||||||
#define rHcRmInterval (*(volatile unsigned *)0x49000034)
|
|
||||||
#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
|
|
||||||
#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
|
|
||||||
#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
|
|
||||||
#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
|
|
||||||
#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
|
|
||||||
#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
|
|
||||||
#define rHcRhStatus (*(volatile unsigned *)0x49000050)
|
|
||||||
#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
|
|
||||||
#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
|
|
||||||
|
|
||||||
|
|
||||||
/* INTERRUPT */
|
static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
|
||||||
#define rSRCPND (*(volatile unsigned *)0x4A000000)
|
{
|
||||||
#define rINTMOD (*(volatile unsigned *)0x4A000004)
|
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
|
||||||
#define rINTMSK (*(volatile unsigned *)0x4A000008)
|
}
|
||||||
#define rPRIORITY (*(volatile unsigned *)0x4A00000C)
|
static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
|
||||||
#define rINTPND (*(volatile unsigned *)0x4A000010)
|
{
|
||||||
#define rINTOFFSET (*(volatile unsigned *)0x4A000014)
|
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
|
||||||
#define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
|
}
|
||||||
#define rINTSUBMSK (*(volatile unsigned *)0x4A00001C)
|
static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
|
||||||
|
{
|
||||||
|
return (S3C2410_NAND * const)S3C2410_NAND_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
|
||||||
|
{
|
||||||
|
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
|
||||||
|
}
|
||||||
|
static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
|
||||||
|
{
|
||||||
|
return (S3C2410_ADC * const)S3C2410_ADC_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
|
||||||
|
{
|
||||||
|
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
|
||||||
|
}
|
||||||
|
static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
|
||||||
|
{
|
||||||
|
return (S3C2410_SDI * const)S3C2410_SDI_BASE;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/* DMA */
|
|
||||||
#define rDISRC0 (*(volatile unsigned *)0x4B000000)
|
|
||||||
#define rDISRCC0 (*(volatile unsigned *)0x4B000004)
|
|
||||||
#define rDIDST0 (*(volatile unsigned *)0x4B000008)
|
|
||||||
#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
|
|
||||||
#define rDCON0 (*(volatile unsigned *)0x4B000010)
|
|
||||||
#define rDSTAT0 (*(volatile unsigned *)0x4B000014)
|
|
||||||
#define rDCSRC0 (*(volatile unsigned *)0x4B000018)
|
|
||||||
#define rDCDST0 (*(volatile unsigned *)0x4B00001C)
|
|
||||||
#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
|
|
||||||
#define rDISRC1 (*(volatile unsigned *)0x4B000040)
|
|
||||||
#define rDISRCC1 (*(volatile unsigned *)0x4B000044)
|
|
||||||
#define rDIDST1 (*(volatile unsigned *)0x4B000048)
|
|
||||||
#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
|
|
||||||
#define rDCON1 (*(volatile unsigned *)0x4B000050)
|
|
||||||
#define rDSTAT1 (*(volatile unsigned *)0x4B000054)
|
|
||||||
#define rDCSRC1 (*(volatile unsigned *)0x4B000058)
|
|
||||||
#define rDCDST1 (*(volatile unsigned *)0x4B00005C)
|
|
||||||
#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
|
|
||||||
#define rDISRC2 (*(volatile unsigned *)0x4B000080)
|
|
||||||
#define rDISRCC2 (*(volatile unsigned *)0x4B000084)
|
|
||||||
#define rDIDST2 (*(volatile unsigned *)0x4B000088)
|
|
||||||
#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
|
|
||||||
#define rDCON2 (*(volatile unsigned *)0x4B000090)
|
|
||||||
#define rDSTAT2 (*(volatile unsigned *)0x4B000094)
|
|
||||||
#define rDCSRC2 (*(volatile unsigned *)0x4B000098)
|
|
||||||
#define rDCDST2 (*(volatile unsigned *)0x4B00009C)
|
|
||||||
#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
|
|
||||||
#define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
|
|
||||||
#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
|
|
||||||
#define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
|
|
||||||
#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
|
|
||||||
#define rDCON3 (*(volatile unsigned *)0x4B0000D0)
|
|
||||||
#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
|
|
||||||
#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
|
|
||||||
#define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
|
|
||||||
#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
|
|
||||||
|
|
||||||
|
|
||||||
/* CLOCK & POWER MANAGEMENT */
|
|
||||||
#define rLOCKTIME (*(volatile unsigned *)0x4C000000)
|
|
||||||
#define rMPLLCON (*(volatile unsigned *)0x4C000004)
|
|
||||||
#define rUPLLCON (*(volatile unsigned *)0x4C000008)
|
|
||||||
#define rCLKCON (*(volatile unsigned *)0x4C00000C)
|
|
||||||
#define rCLKSLOW (*(volatile unsigned *)0x4C000010)
|
|
||||||
#define rCLKDIVN (*(volatile unsigned *)0x4C000014)
|
|
||||||
|
|
||||||
|
|
||||||
/* LCD CONTROLLER */
|
|
||||||
#define rLCDCON1 (*(volatile unsigned *)0x4D000000)
|
|
||||||
#define rLCDCON2 (*(volatile unsigned *)0x4D000004)
|
|
||||||
#define rLCDCON3 (*(volatile unsigned *)0x4D000008)
|
|
||||||
#define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
|
|
||||||
#define rLCDCON5 (*(volatile unsigned *)0x4D000010)
|
|
||||||
#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
|
|
||||||
#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
|
|
||||||
#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
|
|
||||||
#define rREDLUT (*(volatile unsigned *)0x4D000020)
|
|
||||||
#define rGREENLUT (*(volatile unsigned *)0x4D000024)
|
|
||||||
#define rBLUELUT (*(volatile unsigned *)0x4D000028)
|
|
||||||
#define rDITHMODE (*(volatile unsigned *)0x4D00004C)
|
|
||||||
#define rTPAL (*(volatile unsigned *)0x4D000050)
|
|
||||||
#define rLCDINTPND (*(volatile unsigned *)0x4D000054)
|
|
||||||
#define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
|
|
||||||
#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
|
|
||||||
|
|
||||||
|
|
||||||
/* NAND FLASH */
|
|
||||||
#define rNFCONF (*(volatile unsigned *)0x4E000000)
|
|
||||||
#define rNFCMD (*(volatile unsigned *)0x4E000004)
|
|
||||||
#define rNFADDR (*(volatile unsigned *)0x4E000008)
|
|
||||||
#define rNFDATA (*(volatile unsigned *)0x4E00000C)
|
|
||||||
#define rNFSTAT (*(volatile unsigned *)0x4E000010)
|
|
||||||
#define rNFECC (*(volatile unsigned *)0x4E000014)
|
|
||||||
|
|
||||||
|
|
||||||
/* UART */
|
|
||||||
#define rULCON0 (*(volatile unsigned *)0x50000000)
|
|
||||||
#define rUCON0 (*(volatile unsigned *)0x50000004)
|
|
||||||
#define rUFCON0 (*(volatile unsigned *)0x50000008)
|
|
||||||
#define rUMCON0 (*(volatile unsigned *)0x5000000C)
|
|
||||||
#define rUTRSTAT0 (*(volatile unsigned *)0x50000010)
|
|
||||||
#define rUERSTAT0 (*(volatile unsigned *)0x50000014)
|
|
||||||
#define rUFSTAT0 (*(volatile unsigned *)0x50000018)
|
|
||||||
#define rUMSTAT0 (*(volatile unsigned *)0x5000001C)
|
|
||||||
#define rUBRDIV0 (*(volatile unsigned *)0x50000028)
|
|
||||||
|
|
||||||
#define rULCON1 (*(volatile unsigned *)0x50004000)
|
|
||||||
#define rUCON1 (*(volatile unsigned *)0x50004004)
|
|
||||||
#define rUFCON1 (*(volatile unsigned *)0x50004008)
|
|
||||||
#define rUMCON1 (*(volatile unsigned *)0x5000400C)
|
|
||||||
#define rUTRSTAT1 (*(volatile unsigned *)0x50004010)
|
|
||||||
#define rUERSTAT1 (*(volatile unsigned *)0x50004014)
|
|
||||||
#define rUFSTAT1 (*(volatile unsigned *)0x50004018)
|
|
||||||
#define rUMSTAT1 (*(volatile unsigned *)0x5000401C)
|
|
||||||
#define rUBRDIV1 (*(volatile unsigned *)0x50004028)
|
|
||||||
|
|
||||||
#define rULCON2 (*(volatile unsigned *)0x50008000)
|
|
||||||
#define rUCON2 (*(volatile unsigned *)0x50008004)
|
|
||||||
#define rUFCON2 (*(volatile unsigned *)0x50008008)
|
|
||||||
#define rUTRSTAT2 (*(volatile unsigned *)0x50008010)
|
|
||||||
#define rUERSTAT2 (*(volatile unsigned *)0x50008014)
|
|
||||||
#define rUFSTAT2 (*(volatile unsigned *)0x50008018)
|
|
||||||
#define rUBRDIV2 (*(volatile unsigned *)0x50008028)
|
|
||||||
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
#define rUTXH0 (*(volatile unsigned char *)0x50000023)
|
|
||||||
#define rURXH0 (*(volatile unsigned char *)0x50000027)
|
|
||||||
#define rUTXH1 (*(volatile unsigned char *)0x50004023)
|
|
||||||
#define rURXH1 (*(volatile unsigned char *)0x50004027)
|
|
||||||
#define rUTXH2 (*(volatile unsigned char *)0x50008023)
|
|
||||||
#define rURXH2 (*(volatile unsigned char *)0x50008027)
|
|
||||||
|
|
||||||
#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
|
|
||||||
#define RdURXH0() (*(volatile unsigned char *)0x50000027)
|
|
||||||
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
|
|
||||||
#define RdURXH1() (*(volatile unsigned char *)0x50004027)
|
|
||||||
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
|
|
||||||
#define RdURXH2() (*(volatile unsigned char *)0x50008027)
|
|
||||||
|
|
||||||
#define UTXH0 (0x50000020+3) /* byte_access address by DMA */
|
|
||||||
#define URXH0 (0x50000024+3)
|
|
||||||
#define UTXH1 (0x50004020+3)
|
|
||||||
#define URXH1 (0x50004024+3)
|
|
||||||
#define UTXH2 (0x50008020+3)
|
|
||||||
#define URXH2 (0x50008024+3)
|
|
||||||
|
|
||||||
#else /* Little Endian */
|
|
||||||
#define rUTXH0 (*(volatile unsigned char *)0x50000020)
|
|
||||||
#define rURXH0 (*(volatile unsigned char *)0x50000024)
|
|
||||||
#define rUTXH1 (*(volatile unsigned char *)0x50004020)
|
|
||||||
#define rURXH1 (*(volatile unsigned char *)0x50004024)
|
|
||||||
#define rUTXH2 (*(volatile unsigned char *)0x50008020)
|
|
||||||
#define rURXH2 (*(volatile unsigned char *)0x50008024)
|
|
||||||
|
|
||||||
#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
|
|
||||||
#define RdURXH0() (*(volatile unsigned char *)0x50000024)
|
|
||||||
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
|
|
||||||
#define RdURXH1() (*(volatile unsigned char *)0x50004024)
|
|
||||||
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
|
|
||||||
#define RdURXH2() (*(volatile unsigned char *)0x50008024)
|
|
||||||
|
|
||||||
#define UTXH0 (0x50000020) /* byte_access address by DMA */
|
|
||||||
#define URXH0 (0x50000024)
|
|
||||||
#define UTXH1 (0x50004020)
|
|
||||||
#define URXH1 (0x50004024)
|
|
||||||
#define UTXH2 (0x50008020)
|
|
||||||
#define URXH2 (0x50008024)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* PWM TIMER */
|
|
||||||
#define rTCFG0 (*(volatile unsigned *)0x51000000)
|
|
||||||
#define rTCFG1 (*(volatile unsigned *)0x51000004)
|
|
||||||
#define rTCON (*(volatile unsigned *)0x51000008)
|
|
||||||
#define rTCNTB0 (*(volatile unsigned *)0x5100000C)
|
|
||||||
#define rTCMPB0 (*(volatile unsigned *)0x51000010)
|
|
||||||
#define rTCNTO0 (*(volatile unsigned *)0x51000014)
|
|
||||||
#define rTCNTB1 (*(volatile unsigned *)0x51000018)
|
|
||||||
#define rTCMPB1 (*(volatile unsigned *)0x5100001C)
|
|
||||||
#define rTCNTO1 (*(volatile unsigned *)0x51000020)
|
|
||||||
#define rTCNTB2 (*(volatile unsigned *)0x51000024)
|
|
||||||
#define rTCMPB2 (*(volatile unsigned *)0x51000028)
|
|
||||||
#define rTCNTO2 (*(volatile unsigned *)0x5100002C)
|
|
||||||
#define rTCNTB3 (*(volatile unsigned *)0x51000030)
|
|
||||||
#define rTCMPB3 (*(volatile unsigned *)0x51000034)
|
|
||||||
#define rTCNTO3 (*(volatile unsigned *)0x51000038)
|
|
||||||
#define rTCNTB4 (*(volatile unsigned *)0x5100003C)
|
|
||||||
#define rTCNTO4 (*(volatile unsigned *)0x51000040)
|
|
||||||
|
|
||||||
|
|
||||||
/* USB DEVICE */
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143)
|
|
||||||
#define rPWR_REG (*(volatile unsigned char *)0x52000147)
|
|
||||||
#define rEP_INT_REG (*(volatile unsigned char *)0x5200014B)
|
|
||||||
#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B)
|
|
||||||
#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F)
|
|
||||||
#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F)
|
|
||||||
#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173)
|
|
||||||
#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177)
|
|
||||||
#define rINDEX_REG (*(volatile unsigned char *)0x5200017B)
|
|
||||||
#define rMAXP_REG (*(volatile unsigned char *)0x52000183)
|
|
||||||
#define rEP0_CSR (*(volatile unsigned char *)0x52000187)
|
|
||||||
#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187)
|
|
||||||
#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B)
|
|
||||||
#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193)
|
|
||||||
#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
|
|
||||||
#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B)
|
|
||||||
#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F)
|
|
||||||
#define rEP0_FIFO (*(volatile unsigned char *)0x520001C3)
|
|
||||||
#define rEP1_FIFO (*(volatile unsigned char *)0x520001C7)
|
|
||||||
#define rEP2_FIFO (*(volatile unsigned char *)0x520001CB)
|
|
||||||
#define rEP3_FIFO (*(volatile unsigned char *)0x520001CF)
|
|
||||||
#define rEP4_FIFO (*(volatile unsigned char *)0x520001D3)
|
|
||||||
#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203)
|
|
||||||
#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207)
|
|
||||||
#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B)
|
|
||||||
#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F)
|
|
||||||
#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213)
|
|
||||||
#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217)
|
|
||||||
#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B)
|
|
||||||
#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F)
|
|
||||||
#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223)
|
|
||||||
#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227)
|
|
||||||
#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B)
|
|
||||||
#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F)
|
|
||||||
#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243)
|
|
||||||
#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247)
|
|
||||||
#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B)
|
|
||||||
#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F)
|
|
||||||
#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253)
|
|
||||||
#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257)
|
|
||||||
#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B)
|
|
||||||
#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F)
|
|
||||||
#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263)
|
|
||||||
#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267)
|
|
||||||
#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B)
|
|
||||||
#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F)
|
|
||||||
#else /* little endian */
|
|
||||||
#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140)
|
|
||||||
#define rPWR_REG (*(volatile unsigned char *)0x52000144)
|
|
||||||
#define rEP_INT_REG (*(volatile unsigned char *)0x52000148)
|
|
||||||
#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158)
|
|
||||||
#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C)
|
|
||||||
#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C)
|
|
||||||
#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170)
|
|
||||||
#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174)
|
|
||||||
#define rINDEX_REG (*(volatile unsigned char *)0x52000178)
|
|
||||||
#define rMAXP_REG (*(volatile unsigned char *)0x52000180)
|
|
||||||
#define rEP0_CSR (*(volatile unsigned char *)0x52000184)
|
|
||||||
#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184)
|
|
||||||
#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
|
|
||||||
#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190)
|
|
||||||
#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
|
|
||||||
#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198)
|
|
||||||
#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C)
|
|
||||||
#define rEP0_FIFO (*(volatile unsigned char *)0x520001C0)
|
|
||||||
#define rEP1_FIFO (*(volatile unsigned char *)0x520001C4)
|
|
||||||
#define rEP2_FIFO (*(volatile unsigned char *)0x520001C8)
|
|
||||||
#define rEP3_FIFO (*(volatile unsigned char *)0x520001CC)
|
|
||||||
#define rEP4_FIFO (*(volatile unsigned char *)0x520001D0)
|
|
||||||
#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200)
|
|
||||||
#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204)
|
|
||||||
#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208)
|
|
||||||
#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C)
|
|
||||||
#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210)
|
|
||||||
#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214)
|
|
||||||
#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218)
|
|
||||||
#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C)
|
|
||||||
#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220)
|
|
||||||
#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224)
|
|
||||||
#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228)
|
|
||||||
#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C)
|
|
||||||
#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240)
|
|
||||||
#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244)
|
|
||||||
#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248)
|
|
||||||
#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C)
|
|
||||||
#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250)
|
|
||||||
#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254)
|
|
||||||
#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258)
|
|
||||||
#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C)
|
|
||||||
#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260)
|
|
||||||
#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264)
|
|
||||||
#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268)
|
|
||||||
#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C)
|
|
||||||
#endif /* __BIG_ENDIAN */
|
|
||||||
|
|
||||||
/* WATCH DOG TIMER */
|
|
||||||
#define rWTCON (*(volatile unsigned *)0x53000000)
|
|
||||||
#define rWTDAT (*(volatile unsigned *)0x53000004)
|
|
||||||
#define rWTCNT (*(volatile unsigned *)0x53000008)
|
|
||||||
|
|
||||||
|
|
||||||
/* IIC */
|
|
||||||
#define rIICCON (*(volatile unsigned *)0x54000000)
|
|
||||||
#define rIICSTAT (*(volatile unsigned *)0x54000004)
|
|
||||||
#define rIICADD (*(volatile unsigned *)0x54000008)
|
|
||||||
#define rIICDS (*(volatile unsigned *)0x5400000C)
|
|
||||||
|
|
||||||
|
|
||||||
/* IIS */
|
|
||||||
#define rIISCON (*(volatile unsigned *)0x55000000)
|
|
||||||
#define rIISMOD (*(volatile unsigned *)0x55000004)
|
|
||||||
#define rIISPSR (*(volatile unsigned *)0x55000008)
|
|
||||||
#define rIISFCON (*(volatile unsigned *)0x5500000C)
|
|
||||||
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
#define IISFIF ((volatile unsigned short *)0x55000012)
|
|
||||||
#else /* little endian */
|
|
||||||
#define IISFIF ((volatile unsigned short *)0x55000010)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* I/O PORT */
|
|
||||||
#define rGPACON (*(volatile unsigned *)0x56000000)
|
|
||||||
#define rGPADAT (*(volatile unsigned *)0x56000004)
|
|
||||||
|
|
||||||
#define rGPBCON (*(volatile unsigned *)0x56000010)
|
|
||||||
#define rGPBDAT (*(volatile unsigned *)0x56000014)
|
|
||||||
#define rGPBUP (*(volatile unsigned *)0x56000018)
|
|
||||||
|
|
||||||
#define rGPCCON (*(volatile unsigned *)0x56000020)
|
|
||||||
#define rGPCDAT (*(volatile unsigned *)0x56000024)
|
|
||||||
#define rGPCUP (*(volatile unsigned *)0x56000028)
|
|
||||||
|
|
||||||
#define rGPDCON (*(volatile unsigned *)0x56000030)
|
|
||||||
#define rGPDDAT (*(volatile unsigned *)0x56000034)
|
|
||||||
#define rGPDUP (*(volatile unsigned *)0x56000038)
|
|
||||||
|
|
||||||
#define rGPECON (*(volatile unsigned *)0x56000040)
|
|
||||||
#define rGPEDAT (*(volatile unsigned *)0x56000044)
|
|
||||||
#define rGPEUP (*(volatile unsigned *)0x56000048)
|
|
||||||
|
|
||||||
#define rGPFCON (*(volatile unsigned *)0x56000050)
|
|
||||||
#define rGPFDAT (*(volatile unsigned *)0x56000054)
|
|
||||||
#define rGPFUP (*(volatile unsigned *)0x56000058)
|
|
||||||
|
|
||||||
#define rGPGCON (*(volatile unsigned *)0x56000060)
|
|
||||||
#define rGPGDAT (*(volatile unsigned *)0x56000064)
|
|
||||||
#define rGPGUP (*(volatile unsigned *)0x56000068)
|
|
||||||
|
|
||||||
#define rGPHCON (*(volatile unsigned *)0x56000070)
|
|
||||||
#define rGPHDAT (*(volatile unsigned *)0x56000074)
|
|
||||||
#define rGPHUP (*(volatile unsigned *)0x56000078)
|
|
||||||
|
|
||||||
#define rMISCCR (*(volatile unsigned *)0x56000080)
|
|
||||||
#define rDCLKCON (*(volatile unsigned *)0x56000084)
|
|
||||||
#define rEXTINT0 (*(volatile unsigned *)0x56000088)
|
|
||||||
#define rEXTINT1 (*(volatile unsigned *)0x5600008C)
|
|
||||||
#define rEXTINT2 (*(volatile unsigned *)0x56000090)
|
|
||||||
#define rEINTFLT0 (*(volatile unsigned *)0x56000094)
|
|
||||||
#define rEINTFLT1 (*(volatile unsigned *)0x56000098)
|
|
||||||
#define rEINTFLT2 (*(volatile unsigned *)0x5600009C)
|
|
||||||
#define rEINTFLT3 (*(volatile unsigned *)0x560000A0)
|
|
||||||
#define rEINTMASK (*(volatile unsigned *)0x560000A4)
|
|
||||||
#define rEINTPEND (*(volatile unsigned *)0x560000A8)
|
|
||||||
#define rGSTATUS0 (*(volatile unsigned *)0x560000AC)
|
|
||||||
#define rGSTATUS1 (*(volatile unsigned *)0x560000B0)
|
|
||||||
|
|
||||||
|
|
||||||
/* RTC */
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
#define rRTCCON (*(volatile unsigned char *)0x57000043)
|
|
||||||
#define rTICNT (*(volatile unsigned char *)0x57000047)
|
|
||||||
#define rRTCALM (*(volatile unsigned char *)0x57000053)
|
|
||||||
#define rALMSEC (*(volatile unsigned char *)0x57000057)
|
|
||||||
#define rALMMIN (*(volatile unsigned char *)0x5700005B)
|
|
||||||
#define rALMHOUR (*(volatile unsigned char *)0x5700005F)
|
|
||||||
#define rALMDATE (*(volatile unsigned char *)0x57000063)
|
|
||||||
#define rALMMON (*(volatile unsigned char *)0x57000067)
|
|
||||||
#define rALMYEAR (*(volatile unsigned char *)0x5700006B)
|
|
||||||
#define rRTCRST (*(volatile unsigned char *)0x5700006F)
|
|
||||||
#define rBCDSEC (*(volatile unsigned char *)0x57000073)
|
|
||||||
#define rBCDMIN (*(volatile unsigned char *)0x57000077)
|
|
||||||
#define rBCDHOUR (*(volatile unsigned char *)0x5700007B)
|
|
||||||
#define rBCDDATE (*(volatile unsigned char *)0x5700007F)
|
|
||||||
#define rBCDDAY (*(volatile unsigned char *)0x57000083)
|
|
||||||
#define rBCDMON (*(volatile unsigned char *)0x57000087)
|
|
||||||
#define rBCDYEAR (*(volatile unsigned char *)0x5700008B)
|
|
||||||
#else /* little endian */
|
|
||||||
#define rRTCCON (*(volatile unsigned char *)0x57000040)
|
|
||||||
#define rTICNT (*(volatile unsigned char *)0x57000044)
|
|
||||||
#define rRTCALM (*(volatile unsigned char *)0x57000050)
|
|
||||||
#define rALMSEC (*(volatile unsigned char *)0x57000054)
|
|
||||||
#define rALMMIN (*(volatile unsigned char *)0x57000058)
|
|
||||||
#define rALMHOUR (*(volatile unsigned char *)0x5700005C)
|
|
||||||
#define rALMDATE (*(volatile unsigned char *)0x57000060)
|
|
||||||
#define rALMMON (*(volatile unsigned char *)0x57000064)
|
|
||||||
#define rALMYEAR (*(volatile unsigned char *)0x57000068)
|
|
||||||
#define rRTCRST (*(volatile unsigned char *)0x5700006C)
|
|
||||||
#define rBCDSEC (*(volatile unsigned char *)0x57000070)
|
|
||||||
#define rBCDMIN (*(volatile unsigned char *)0x57000074)
|
|
||||||
#define rBCDHOUR (*(volatile unsigned char *)0x57000078)
|
|
||||||
#define rBCDDATE (*(volatile unsigned char *)0x5700007C)
|
|
||||||
#define rBCDDAY (*(volatile unsigned char *)0x57000080)
|
|
||||||
#define rBCDMON (*(volatile unsigned char *)0x57000084)
|
|
||||||
#define rBCDYEAR (*(volatile unsigned char *)0x57000088)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* ADC */
|
|
||||||
#define rADCCON (*(volatile unsigned *)0x58000000)
|
|
||||||
#define rADCTSC (*(volatile unsigned *)0x58000004)
|
|
||||||
#define rADCDLY (*(volatile unsigned *)0x58000008)
|
|
||||||
#define rADCDAT0 (*(volatile unsigned *)0x5800000C)
|
|
||||||
#define rADCDAT1 (*(volatile unsigned *)0x58000010)
|
|
||||||
|
|
||||||
|
|
||||||
/* SPI */
|
|
||||||
#define rSPCON0 (*(volatile unsigned *)0x59000000)
|
|
||||||
#define rSPSTA0 (*(volatile unsigned *)0x59000004)
|
|
||||||
#define rSPPIN0 (*(volatile unsigned *)0x59000008)
|
|
||||||
#define rSPPRE0 (*(volatile unsigned *)0x5900000C)
|
|
||||||
#define rSPTDAT0 (*(volatile unsigned *)0x59000010)
|
|
||||||
#define rSPRDAT0 (*(volatile unsigned *)0x59000014)
|
|
||||||
#define rSPCON1 (*(volatile unsigned *)0x59000020)
|
|
||||||
#define rSPSTA1 (*(volatile unsigned *)0x59000024)
|
|
||||||
#define rSPPIN1 (*(volatile unsigned *)0x59000028)
|
|
||||||
#define rSPPRE1 (*(volatile unsigned *)0x5900002C)
|
|
||||||
#define rSPTDAT1 (*(volatile unsigned *)0x59000030)
|
|
||||||
#define rSPRDAT1 (*(volatile unsigned *)0x59000034)
|
|
||||||
|
|
||||||
|
|
||||||
/* SD INTERFACE */
|
|
||||||
#define rSDICON (*(volatile unsigned *)0x5A000000)
|
|
||||||
#define rSDIPRE (*(volatile unsigned *)0x5A000004)
|
|
||||||
#define rSDICmdArg (*(volatile unsigned *)0x5A000008)
|
|
||||||
#define rSDICmdCon (*(volatile unsigned *)0x5A00000C)
|
|
||||||
#define rSDICmdSta (*(volatile unsigned *)0x5A000010)
|
|
||||||
#define rSDIRSP0 (*(volatile unsigned *)0x5A000014)
|
|
||||||
#define rSDIRSP1 (*(volatile unsigned *)0x5A000018)
|
|
||||||
#define rSDIRSP2 (*(volatile unsigned *)0x5A00001C)
|
|
||||||
#define rSDIRSP3 (*(volatile unsigned *)0x5A000020)
|
|
||||||
#define rSDIDTimer (*(volatile unsigned *)0x5A000024)
|
|
||||||
#define rSDIBSize (*(volatile unsigned *)0x5A000028)
|
|
||||||
#define rSDIDatCon (*(volatile unsigned *)0x5A00002C)
|
|
||||||
#define rSDIDatCnt (*(volatile unsigned *)0x5A000030)
|
|
||||||
#define rSDIDatSta (*(volatile unsigned *)0x5A000034)
|
|
||||||
#define rSDIFSTA (*(volatile unsigned *)0x5A000038)
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
#define rSDIDAT (*(volatile unsigned char *)0x5A00003F)
|
|
||||||
#else
|
|
||||||
#define rSDIDAT (*(volatile unsigned char *)0x5A00003C)
|
|
||||||
#endif
|
|
||||||
#define rSDIIntMsk (*(volatile unsigned *)0x5A000040)
|
|
||||||
|
|
||||||
/* ISR */
|
/* ISR */
|
||||||
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
|
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
|
||||||
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
|
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -321,6 +321,10 @@ void status_led_set (int led, int state);
|
||||||
#endif
|
#endif
|
||||||
/************************************************************************/
|
/************************************************************************/
|
||||||
|
|
||||||
|
#ifndef CONFIG_BOARD_SPECIFIC_LED
|
||||||
|
# include <asm/status_led.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* CONFIG_STATUS_LED */
|
#endif /* CONFIG_STATUS_LED */
|
||||||
|
|
||||||
#endif /* _STATUS_LED_H_ */
|
#endif /* _STATUS_LED_H_ */
|
||||||
|
|
|
@ -42,8 +42,12 @@ extern int AT91F_DataflashInit(void);
|
||||||
extern void dataflash_print_info(void);
|
extern void dataflash_print_info(void);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_IDENT_STRING
|
||||||
|
#define CONFIG_IDENT_STRING ""
|
||||||
|
#endif
|
||||||
|
|
||||||
const char version_string[] =
|
const char version_string[] =
|
||||||
U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
|
U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"CONFIG_IDENT_STRING;
|
||||||
|
|
||||||
#ifdef CONFIG_DRIVER_CS8900
|
#ifdef CONFIG_DRIVER_CS8900
|
||||||
extern void cs8900_get_enetaddr (uchar * addr);
|
extern void cs8900_get_enetaddr (uchar * addr);
|
||||||
|
@ -150,7 +154,6 @@ static void display_flash_config (ulong size)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Breath some life into the board...
|
* Breath some life into the board...
|
||||||
*
|
*
|
||||||
|
|
|
@ -31,7 +31,7 @@ OBJS = date.o \
|
||||||
ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \
|
ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \
|
||||||
ds1556.o ds164x.o ds174x.o \
|
ds1556.o ds164x.o ds174x.o \
|
||||||
m41t11.o m48t35ax.o mc146818.o mk48t59.o \
|
m41t11.o m48t35ax.o mc146818.o mk48t59.o \
|
||||||
mpc8xx.o pcf8563.o
|
mpc8xx.o pcf8563.o s3c24x0_rtc.o
|
||||||
|
|
||||||
all: $(LIB)
|
all: $(LIB)
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,178 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003
|
||||||
|
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Date & Time support for the built-in Samsung S3C24X0 RTC
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <command.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_RTC_S3C24X0) && (CONFIG_COMMANDS & CFG_CMD_DATE)
|
||||||
|
|
||||||
|
#if defined(CONFIG_S3C2400)
|
||||||
|
#include <s3c2400.h>
|
||||||
|
#elif defined(CONFIG_S3C2410)
|
||||||
|
#include <s3c2410.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtc.h>
|
||||||
|
|
||||||
|
/*#define DEBUG*/
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
RTC_ENABLE,
|
||||||
|
RTC_DISABLE
|
||||||
|
} RTC_ACCESS;
|
||||||
|
|
||||||
|
|
||||||
|
static inline void SetRTC_Access(RTC_ACCESS a)
|
||||||
|
{
|
||||||
|
S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
|
||||||
|
switch (a) {
|
||||||
|
case RTC_ENABLE:
|
||||||
|
rtc->RTCCON |= 0x01; break;
|
||||||
|
|
||||||
|
case RTC_DISABLE:
|
||||||
|
rtc->RTCCON &= ~0x01; break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned bcd2bin (uchar n)
|
||||||
|
{
|
||||||
|
return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned char bin2bcd (unsigned int n)
|
||||||
|
{
|
||||||
|
return (((n / 10) << 4) | (n % 10));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
void rtc_get (struct rtc_time *tmp)
|
||||||
|
{
|
||||||
|
S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
|
||||||
|
uchar sec, min, hour, mday, wday, mon, year;
|
||||||
|
uchar a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed;
|
||||||
|
|
||||||
|
/* enable access to RTC registers */
|
||||||
|
SetRTC_Access(RTC_ENABLE);
|
||||||
|
|
||||||
|
/* read RTC registers */
|
||||||
|
sec = rtc->BCDSEC;
|
||||||
|
min = rtc->BCDMIN;
|
||||||
|
hour = rtc->BCDHOUR;
|
||||||
|
mday = rtc->BCDDATE;
|
||||||
|
wday = rtc->BCDDAY;
|
||||||
|
mon = rtc->BCDMON;
|
||||||
|
year = rtc->BCDYEAR;
|
||||||
|
|
||||||
|
/* read ALARM registers */
|
||||||
|
a_sec = rtc->ALMSEC;
|
||||||
|
a_min = rtc->ALMMIN;
|
||||||
|
a_hour = rtc->ALMHOUR;
|
||||||
|
a_date = rtc->ALMDATE;
|
||||||
|
a_mon = rtc->ALMMON;
|
||||||
|
a_year = rtc->ALMYEAR;
|
||||||
|
a_armed = rtc->RTCALM;
|
||||||
|
|
||||||
|
/* disable access to RTC registers */
|
||||||
|
SetRTC_Access(RTC_DISABLE);
|
||||||
|
|
||||||
|
#ifdef RTC_DEBUG
|
||||||
|
printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
|
||||||
|
"hr: %02x min: %02x sec: %02x\n",
|
||||||
|
year, mon, mday, wday,
|
||||||
|
hour, min, sec);
|
||||||
|
printf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n",
|
||||||
|
a_armed,
|
||||||
|
a_year, a_mon, a_date,
|
||||||
|
a_hour, a_min, a_sec);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
tmp->tm_sec = bcd2bin(sec & 0x7F);
|
||||||
|
tmp->tm_min = bcd2bin(min & 0x7F);
|
||||||
|
tmp->tm_hour = bcd2bin(hour & 0x3F);
|
||||||
|
tmp->tm_mday = bcd2bin(mday & 0x3F);
|
||||||
|
tmp->tm_mon = bcd2bin(mon & 0x1F);
|
||||||
|
tmp->tm_year = bcd2bin(year);
|
||||||
|
tmp->tm_wday = bcd2bin(wday & 0x07);
|
||||||
|
if(tmp->tm_year<70)
|
||||||
|
tmp->tm_year+=2000;
|
||||||
|
else
|
||||||
|
tmp->tm_year+=1900;
|
||||||
|
tmp->tm_yday = 0;
|
||||||
|
tmp->tm_isdst= 0;
|
||||||
|
#ifdef RTC_DEBUG
|
||||||
|
printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
|
||||||
|
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
|
||||||
|
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
void rtc_set (struct rtc_time *tmp)
|
||||||
|
{
|
||||||
|
S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
|
||||||
|
uchar sec, min, hour, mday, wday, mon, year;
|
||||||
|
|
||||||
|
#ifdef RTC_DEBUG
|
||||||
|
printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
|
||||||
|
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
|
||||||
|
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
|
||||||
|
#endif
|
||||||
|
year = bin2bcd(tmp->tm_year % 100);
|
||||||
|
mon = bin2bcd(tmp->tm_mon);
|
||||||
|
wday = bin2bcd(tmp->tm_wday);
|
||||||
|
mday = bin2bcd(tmp->tm_mday);
|
||||||
|
hour = bin2bcd(tmp->tm_hour);
|
||||||
|
min = bin2bcd(tmp->tm_min);
|
||||||
|
sec = bin2bcd(tmp->tm_sec);
|
||||||
|
|
||||||
|
/* enable access to RTC registers */
|
||||||
|
SetRTC_Access(RTC_ENABLE);
|
||||||
|
|
||||||
|
/* write RTC registers */
|
||||||
|
rtc->BCDSEC = sec;
|
||||||
|
rtc->BCDMIN = min;
|
||||||
|
rtc->BCDHOUR = hour;
|
||||||
|
rtc->BCDDATE = mday;
|
||||||
|
rtc->BCDDAY = wday;
|
||||||
|
rtc->BCDMON = mon;
|
||||||
|
rtc->BCDYEAR = year;
|
||||||
|
|
||||||
|
/* disable access to RTC registers */
|
||||||
|
SetRTC_Access(RTC_DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void rtc_reset (void)
|
||||||
|
{
|
||||||
|
S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
|
||||||
|
|
||||||
|
rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08;
|
||||||
|
rtc->RTCCON &= ~0x08;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
#endif /* CONFIG_RTC_S3C24X0 && CFG_CMD_DATE */
|
Loading…
Reference in New Issue