omap_gpmc: add support for hw assisted BCH8
The kernel states: ---8<--- The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not provide automatic error location and correction: this step is implemented using the BCH library. --->8--- And we do so in u-boot. This implementation uses the same layout for BCH8 but it is fix. The current provided layout does only work with 64 Byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mansoor Ahamed <mansoor.ahamed@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
This commit is contained in:
Andreas Bießmann
Tom Rini
parent
da634ae356
commit
4a0930069b
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@ -145,6 +145,34 @@ int omap3_dma_wait_for_transfer(uint32_t chan)
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int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
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Read silicon Revision of the DMA module
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NAND
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====
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There are some OMAP3 devices out there with NAND attached. Due to the fact that
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OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page
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(place where SPL lives) we require this setup for u-boot at least when reading
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the second progam within SPL. A lot of newer NAND chips however require more
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than 1-bit ECC for the pages, some can live with 1-bit for the first page. To
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handle this we can switch to another ECC algorithm after reading the payload
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within SPL.
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BCH8
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----
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To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
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OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
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to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted
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syndrom generation to your board config.
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The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
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implementation for OMAP3 works for you so the u-boot version should also.
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When you require the SPL to read with BCH8 there are two more configs to
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change:
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* CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
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GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
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arch/arm/include/asm/arch-omap3/omap_gpmc.h)
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* CONFIG_SYS_NAND_ECCSIZE must be 512
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* CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
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Acknowledgements
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================
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@ -28,6 +28,7 @@
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#include <asm/arch/cpu.h>
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#include <asm/omap_gpmc.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/bch.h>
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#include <linux/compiler.h>
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#include <nand.h>
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#ifdef CONFIG_AM33XX
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@ -37,6 +38,8 @@
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static uint8_t cs;
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static __maybe_unused struct nand_ecclayout hw_nand_oob =
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GPMC_NAND_HW_ECC_LAYOUT;
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static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
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GPMC_NAND_HW_BCH8_ECC_LAYOUT;
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/*
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* omap_nand_hwcontrol - Set the address pointers corretly for the
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@ -239,13 +242,13 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
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}
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/*
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* BCH8 support (needs ELM and thus AM33xx-only)
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* Generic BCH interface
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*/
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#ifdef CONFIG_AM33XX
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struct nand_bch_priv {
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uint8_t mode;
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uint8_t type;
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uint8_t nibbles;
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struct bch_control *control;
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};
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/* bch types */
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@ -253,20 +256,145 @@ struct nand_bch_priv {
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#define ECC_BCH8 1
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#define ECC_BCH16 2
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/* GPMC ecc engine settings */
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#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
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#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
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/* BCH nibbles for diff bch levels */
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#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
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#define ECC_BCH4_NIBBLES 13
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#define ECC_BCH8_NIBBLES 26
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#define ECC_BCH16_NIBBLES 52
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static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
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static struct nand_bch_priv bch_priv = {
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/*
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* This can be a single instance cause all current users have only one NAND
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* with nearly the same setup (BCH8, some with ELM and others with sw BCH
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* library).
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* When some users with other BCH strength will exists this have to change!
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*/
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static __maybe_unused struct nand_bch_priv bch_priv = {
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.mode = NAND_ECC_HW_BCH,
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.type = ECC_BCH8,
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.nibbles = ECC_BCH8_NIBBLES
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.nibbles = ECC_BCH8_NIBBLES,
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.control = NULL
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};
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/*
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* omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
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* GPMC controller
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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__maybe_unused
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static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
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{
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uint32_t val;
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uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
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#ifdef CONFIG_AM33XX
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uint32_t unused_length = 0;
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#endif
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uint32_t wr_mode = BCH_WRAPMODE_6;
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struct nand_bch_priv *bch = chip->priv;
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/* Clear the ecc result registers, select ecc reg as 1 */
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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#ifdef CONFIG_AM33XX
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wr_mode = BCH_WRAPMODE_1;
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switch (bch->nibbles) {
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case ECC_BCH4_NIBBLES:
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unused_length = 3;
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break;
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case ECC_BCH8_NIBBLES:
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unused_length = 2;
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break;
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case ECC_BCH16_NIBBLES:
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unused_length = 0;
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break;
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}
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/*
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* This is ecc_size_config for ELM mode.
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* Here we are using different settings for read and write access and
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* also depending on BCH strength.
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*/
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switch (mode) {
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case NAND_ECC_WRITE:
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/* write access only setup eccsize1 config */
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val = ((unused_length + bch->nibbles) << 22);
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break;
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case NAND_ECC_READ:
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default:
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/*
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* by default eccsize0 selected for ecc1resultsize
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* eccsize0 config.
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*/
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val = (bch->nibbles << 12);
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/* eccsize1 config */
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val |= (unused_length << 22);
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break;
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}
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#else
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/*
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* This ecc_size_config setting is for BCH sw library.
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*
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* Note: we only support BCH8 currently with BCH sw library!
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* Should be really easy to adobt to BCH4, however some omap3 have
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* flaws with BCH4.
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*
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* Here we are using wrapping mode 6 both for reading and writing, with:
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* size0 = 0 (no additional protected byte in spare area)
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* size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
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*/
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val = (32 << 22) | (0 << 12);
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#endif
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/* ecc size configuration */
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writel(val, &gpmc_cfg->ecc_size_config);
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/*
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* Configure the ecc engine in gpmc
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* We assume 512 Byte sector pages for access to NAND.
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*/
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val = (1 << 16); /* enable BCH mode */
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val |= (bch->type << 12); /* setup BCH type */
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val |= (wr_mode << 8); /* setup wrapping mode */
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val |= (dev_width << 7); /* setup device width (16 or 8 bit) */
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val |= (cs << 1); /* setup chip select to work on */
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debug("set ECC_CONFIG=0x%08x\n", val);
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writel(val, &gpmc_cfg->ecc_config);
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}
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/*
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* omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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__maybe_unused
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static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
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{
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struct nand_chip *chip = mtd->priv;
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omap_hwecc_init_bch(chip, mode);
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/* enable ecc */
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writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
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}
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/*
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* omap_ecc_disable - Disable H/W ECC calculation
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*
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* @mtd: MTD device structure
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*/
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static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
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{
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writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
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}
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/*
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* BCH8 support (needs ELM and thus AM33xx-only)
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*/
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#ifdef CONFIG_AM33XX
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/*
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* omap_read_bch8_result - Read BCH result for BCH8 level
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*
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@ -305,18 +433,6 @@ static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
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}
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}
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/*
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* omap_ecc_disable - Disable H/W ECC calculation
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*
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* @mtd: MTD device structure
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*
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*/
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static void omap_ecc_disable(struct mtd_info *mtd)
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{
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writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
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&gpmc_cfg->ecc_config);
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}
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/*
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* omap_rotate_ecc_bch - Rotate the syndrome bytes
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*
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@ -468,76 +584,6 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
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return 0;
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}
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/*
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* omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
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* GPMC controller
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
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{
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uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
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uint32_t unused_length = 0;
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struct nand_bch_priv *bch = chip->priv;
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switch (bch->nibbles) {
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case ECC_BCH4_NIBBLES:
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unused_length = 3;
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break;
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case ECC_BCH8_NIBBLES:
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unused_length = 2;
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break;
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case ECC_BCH16_NIBBLES:
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unused_length = 0;
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break;
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}
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/* Clear the ecc result registers, select ecc reg as 1 */
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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switch (mode) {
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case NAND_ECC_WRITE:
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/* eccsize1 config */
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val = ((unused_length + bch->nibbles) << 22);
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break;
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case NAND_ECC_READ:
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default:
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/* by default eccsize0 selected for ecc1resultsize */
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/* eccsize0 config */
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val = (bch->nibbles << 12);
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/* eccsize1 config */
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val |= (unused_length << 22);
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break;
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}
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/* ecc size configuration */
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writel(val, &gpmc_cfg->ecc_size_config);
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/* by default 512bytes sector page is selected */
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/* set bch mode */
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val = (1 << 16);
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/* bch4 / bch8 / bch16 */
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val |= (bch->type << 12);
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/* set wrap mode to 1 */
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val |= (1 << 8);
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val |= (dev_width << 7);
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val |= (cs << 1);
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writel(val, &gpmc_cfg->ecc_config);
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}
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/*
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* omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*
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*/
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static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
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{
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struct nand_chip *chip = mtd->priv;
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omap_hwecc_init_bch(chip, mode);
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/* enable ecc */
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writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
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}
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/**
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* omap_read_page_bch - hardware ecc based page read function
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@ -602,6 +648,127 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
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}
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#endif /* CONFIG_AM33XX */
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/*
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* OMAP3 BCH8 support (with BCH library)
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*/
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#ifdef CONFIG_NAND_OMAP_BCH8
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/*
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* omap_calculate_ecc_bch - Read BCH ECC result
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*
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* @mtd: MTD device structure
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* @dat: The pointer to data on which ecc is computed (unused here)
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* @ecc: The ECC output buffer
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*/
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static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc)
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{
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int ret = 0;
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size_t i;
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unsigned long nsectors, val1, val2, val3, val4;
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nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
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for (i = 0; i < nsectors; i++) {
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/* Read hw-computed remainder */
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val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
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val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
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val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
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val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
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/*
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* Add constant polynomial to remainder, in order to get an ecc
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* sequence of 0xFFs for a buffer filled with 0xFFs.
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*/
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*ecc++ = 0xef ^ (val4 & 0xFF);
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*ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
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*ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
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*ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
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*ecc++ = 0xed ^ (val3 & 0xFF);
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*ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
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*ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
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*ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
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*ecc++ = 0x97 ^ (val2 & 0xFF);
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*ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
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*ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
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*ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
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*ecc++ = 0xb5 ^ (val1 & 0xFF);
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}
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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omap_ecc_disable(mtd);
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return ret;
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}
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/**
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* omap_correct_data_bch - Decode received data and correct errors
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* @mtd: MTD device structure
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* @data: page data
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* @read_ecc: ecc read from nand flash
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* @calc_ecc: ecc read from HW ECC registers
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*/
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static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
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u_char *read_ecc, u_char *calc_ecc)
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{
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int i, count;
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/* cannot correct more than 8 errors */
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unsigned int errloc[8];
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *chip_priv = chip->priv;
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struct bch_control *bch = chip_priv->control;
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count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
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if (count > 0) {
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/* correct errors */
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for (i = 0; i < count; i++) {
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/* correct data only, not ecc bytes */
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if (errloc[i] < 8*512)
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data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
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printf("corrected bitflip %u\n", errloc[i]);
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#ifdef DEBUG
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puts("read_ecc: ");
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/*
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* BCH8 have 13 bytes of ECC; BCH4 needs adoption
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* here!
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*/
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for (i = 0; i < 13; i++)
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printf("%02x ", read_ecc[i]);
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puts("\n");
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puts("calc_ecc: ");
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for (i = 0; i < 13; i++)
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printf("%02x ", calc_ecc[i]);
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puts("\n");
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#endif
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}
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} else if (count < 0) {
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puts("ecc unrecoverable error\n");
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}
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return count;
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}
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/**
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* omap_free_bch - Release BCH ecc resources
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* @mtd: MTD device structure
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*/
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static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *chip_priv = chip->priv;
|
||||
struct bch_control *bch = NULL;
|
||||
|
||||
if (chip_priv)
|
||||
bch = chip_priv->control;
|
||||
|
||||
if (bch) {
|
||||
free_bch(bch);
|
||||
chip_priv->control = NULL;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_NAND_OMAP_BCH8 */
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* omap_nand_switch_ecc - switch the ECC operation between different engines
|
||||
|
|
@ -651,13 +818,17 @@ void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
|
|||
omap_hwecc_init(nand);
|
||||
printf("1-bit hamming HW ECC selected\n");
|
||||
}
|
||||
#ifdef CONFIG_AM33XX
|
||||
#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
|
||||
else if (eccstrength == 8) {
|
||||
nand->ecc.mode = NAND_ECC_HW;
|
||||
nand->ecc.layout = &hw_bch8_nand_oob;
|
||||
nand->ecc.size = 512;
|
||||
#ifdef CONFIG_AM33XX
|
||||
nand->ecc.bytes = 14;
|
||||
nand->ecc.read_page = omap_read_page_bch;
|
||||
#else
|
||||
nand->ecc.bytes = 13;
|
||||
#endif
|
||||
nand->ecc.hwctl = omap_enable_ecc_bch;
|
||||
nand->ecc.correct = omap_correct_data_bch;
|
||||
nand->ecc.calculate = omap_calculate_ecc_bch;
|
||||
|
|
@ -737,16 +908,28 @@ int board_nand_init(struct nand_chip *nand)
|
|||
|
||||
nand->chip_delay = 100;
|
||||
|
||||
#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
|
||||
#ifdef CONFIG_AM33XX
|
||||
/* AM33xx uses the ELM */
|
||||
/* required in case of BCH */
|
||||
elm_init();
|
||||
|
||||
#else
|
||||
/*
|
||||
* Whereas other OMAP based SoC do not have the ELM, they use the BCH
|
||||
* SW library.
|
||||
*/
|
||||
bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
|
||||
if (!bch_priv.control) {
|
||||
puts("Could not init_bch()\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
/* BCH info that will be correct for SPL or overridden otherwise. */
|
||||
nand->priv = &bch_priv;
|
||||
#endif
|
||||
|
||||
/* Default ECC mode */
|
||||
#ifdef CONFIG_AM33XX
|
||||
#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
|
||||
nand->ecc.mode = NAND_ECC_HW;
|
||||
nand->ecc.layout = &hw_bch8_nand_oob;
|
||||
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
|
||||
|
|
@ -754,7 +937,9 @@ int board_nand_init(struct nand_chip *nand)
|
|||
nand->ecc.hwctl = omap_enable_ecc_bch;
|
||||
nand->ecc.correct = omap_correct_data_bch;
|
||||
nand->ecc.calculate = omap_calculate_ecc_bch;
|
||||
#ifdef CONFIG_AM33XX
|
||||
nand->ecc.read_page = omap_read_page_bch;
|
||||
#endif
|
||||
omap_hwecc_init_bch(nand, NAND_ECC_READ);
|
||||
#else
|
||||
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@ LIB = $(obj)libgeneric.o
|
|||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
|
||||
COBJS-$(CONFIG_BCH) += bch.o
|
||||
COBJS-$(CONFIG_AES) += aes.o
|
||||
COBJS-$(CONFIG_BZIP2) += bzlib.o
|
||||
COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
|
||||
|
|
@ -67,6 +66,7 @@ COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
|
|||
COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
|
||||
COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
|
||||
endif
|
||||
COBJS-$(CONFIG_BCH) += bch.o
|
||||
COBJS-y += crc32.o
|
||||
COBJS-y += ctype.o
|
||||
COBJS-y += div64.o
|
||||
|
|
|
|||
Loading…
Reference in New Issue