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Merge remote-tracking branch 'u-boot-imx/master' 

The single file conflict below is actually trivial.

Conflicts:
	board/boundary/nitrogen6x/nitrogen6x.c
This commit is contained in:
Albert ARIBAUD 2014-10-08 21:20:49 +02:00
parent c19a8bc571 5e3a388cdd
commit 4b19b7448e
57 changed files with 3118 additions and 342 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Kconfig
View File

@ -414,6 +414,9 @@ config TARGET_HUMMINGBOARD
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
config TARGET_OT1200
bool "Bachmann OT1200"
config OMAP34XX
bool "OMAP34XX SoC"
@ -583,6 +586,7 @@ source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"

104
arch/arm/cpu/arm1136/mx31/timer.c
View File

@ -7,9 +7,6 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <div64.h>
#include <watchdog.h>
#include <asm/io.h>
#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
@ -28,57 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= MXC_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * MXC_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / MXC_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
@ -95,53 +41,7 @@ int timer_init(void)
return 0;
}
unsigned long long get_ticks(void)
unsigned long timer_read_counter(void)
{
ulong now = GPTCNT; /* current tick value */
if (now >= gd->arch.lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
gd->arch.tbl += (now - gd->arch.lastinc);
else /* we have rollover of incrementer */
gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
gd->arch.lastinc = now;
return gd->arch.tbl;
}
ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timestamp value */
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return MXC_CLK32;
return GPTCNT;
}

83
arch/arm/cpu/arm1136/mx35/timer.c
View File

@ -9,43 +9,17 @@
#include <common.h>
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->arch.tbl)
#define lastinc (gd->arch.lastinc)
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * MXC_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
/*
* nothing really to do with interrupts, just starts up a counter.
* The 32KHz 32-bit timer overruns in 134217 seconds
@ -71,60 +45,3 @@ int timer_init(void)
return 0;
}
unsigned long long get_ticks(void)
{
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
ulong now = readl(&gpt->counter); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return MXC_CLK32;
}

13
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View File

@ -240,9 +240,14 @@ static void mx23_mem_setup_vddmem(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* We must wait before and after disabling the current limiter! */
early_delay(10000);
clrbits_le32(&power_regs->hw_power_vddmemctrl,
POWER_VDDMEMCTRL_ENABLE_ILIMIT);
early_delay(10000);
}
static void mx23_mem_init(void)
@ -269,7 +274,13 @@ static void mx23_mem_init(void)
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
early_delay(20000);
/* Wait for EMI_STAT bit DRAM_HALTED */
for (;;) {
if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
break;
early_delay(1000);
}
/* Adjust EMI port priority. */
clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);

27
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -642,6 +642,33 @@ int enable_pcie_clock(void)
BM_ANADIG_PLL_ENET_ENABLE_PCIE);
}
#ifdef CONFIG_SECURE_BOOT
void hab_caam_clock_enable(unsigned char enable)
{
u32 reg;
/* CG4 ~ CG6, CAAM clocks */
reg = __raw_readl(&imx_ccm->CCGR0);
if (enable)
reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
else
reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
__raw_writel(reg, &imx_ccm->CCGR0);
/* EMI slow clk */
reg = __raw_readl(&imx_ccm->CCGR6);
if (enable)
reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
else
reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
__raw_writel(reg, &imx_ccm->CCGR6);
}
#endif
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {

169
arch/arm/cpu/armv7/mx6/hab.c
View File

@ -1,12 +1,14 @@
/*
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
* Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/hab.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
/* -------- start of HAB API updates ------------*/
@ -71,6 +73,44 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT) \
)
#define IVT_SIZE 0x20
#define ALIGN_SIZE 0x1000
#define CSF_PAD_SIZE 0x2000
#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
/*
* +------------+ 0x0 (DDR_UIMAGE_START) -
* | Header | |
* +------------+ 0x40 |
* | | |
* | | |
* | | |
* | | |
* | Image Data | |
* . | |
* . | > Stuff to be authenticated ----+
* . | | |
* | | | |
* | | | |
* +------------+ | |
* | | | |
* | Fill Data | | |
* | | | |
* +------------+ Align to ALIGN_SIZE | |
* | IVT | | |
* +------------+ + IVT_SIZE - |
* | | |
* | CSF DATA | <---------------------------------------------------------+
* | |
* +------------+
* | |
* | Fill Data |
* | |
* +------------+ + CSF_PAD_SIZE
*/
bool is_hab_enabled(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@ -144,6 +184,108 @@ int get_hab_status(void)
return 0;
}
uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
{
uint32_t load_addr = 0;
size_t bytes;
ptrdiff_t ivt_offset = 0;
int result = 0;
ulong start;
hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
hab_rvt_entry_t *hab_rvt_entry;
hab_rvt_exit_t *hab_rvt_exit;
hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
hab_rvt_entry = hab_rvt_entry_p;
hab_rvt_exit = hab_rvt_exit_p;
if (is_hab_enabled()) {
printf("\nAuthenticate image from DDR location 0x%x...\n",
ddr_start);
hab_caam_clock_enable(1);
if (hab_rvt_entry() == HAB_SUCCESS) {
/* If not already aligned, Align to ALIGN_SIZE */
ivt_offset = (image_size + ALIGN_SIZE - 1) &
~(ALIGN_SIZE - 1);
start = ddr_start;
bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
#ifdef DEBUG
printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
ivt_offset, ddr_start + ivt_offset);
puts("Dumping IVT\n");
print_buffer(ddr_start + ivt_offset,
(void *)(ddr_start + ivt_offset),
4, 0x8, 0);
puts("Dumping CSF Header\n");
print_buffer(ddr_start + ivt_offset+IVT_SIZE,
(void *)(ddr_start + ivt_offset+IVT_SIZE),
4, 0x10, 0);
get_hab_status();
puts("\nCalling authenticate_image in ROM\n");
printf("\tivt_offset = 0x%x\n", ivt_offset);
printf("\tstart = 0x%08lx\n", start);
printf("\tbytes = 0x%x\n", bytes);
#endif
/*
* If the MMU is enabled, we have to notify the ROM
* code, or it won't flush the caches when needed.
* This is done, by setting the "pu_irom_mmu_enabled"
* word to 1. You can find its address by looking in
* the ROM map. This is critical for
* authenticate_image(). If MMU is enabled, without
* setting this bit, authentication will fail and may
* crash.
*/
/* Check MMU enabled */
if (get_cr() & CR_M) {
if (is_cpu_type(MXC_CPU_MX6Q) ||
is_cpu_type(MXC_CPU_MX6D)) {
/*
* This won't work on Rev 1.0.0 of
* i.MX6Q/D, since their ROM doesn't
* do cache flushes. don't think any
* exist, so we ignore them.
*/
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
} else if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO)) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
} else if (is_cpu_type(MXC_CPU_MX6SL)) {
writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
}
}
load_addr = (uint32_t)hab_rvt_authenticate_image(
HAB_CID_UBOOT,
ivt_offset, (void **)&start,
(size_t *)&bytes, NULL);
if (hab_rvt_exit() != HAB_SUCCESS) {
puts("hab exit function fail\n");
load_addr = 0;
}
} else {
puts("hab entry function fail\n");
}
hab_caam_clock_enable(0);
get_hab_status();
} else {
puts("hab fuse not enabled\n");
}
if ((!is_hab_enabled()) || (load_addr != 0))
result = 1;
return result;
}
int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if ((argc != 1)) {
@ -156,8 +298,33 @@ int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
ulong addr, ivt_offset;
int rcode = 0;
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
ivt_offset = simple_strtoul(argv[2], NULL, 16);
rcode = authenticate_image(addr, ivt_offset);
return rcode;
}
U_BOOT_CMD(
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
"display HAB status",
""
);
U_BOOT_CMD(
hab_auth_img, 3, 0, do_authenticate_image,
"authenticate image via HAB",
"addr ivt_offset\n"
"addr - image hex address\n"
"ivt_offset - hex offset of IVT in the image"
);

39
arch/arm/cpu/armv7/mx6/soc.c
View File

@ -273,10 +273,25 @@ int board_postclk_init(void)
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
enum dcache_option option = DCACHE_WRITETHROUGH;
#else
enum dcache_option option = DCACHE_WRITEBACK;
#endif
/* Avoid random hang when download by usb */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
/* Enable caching on OCRAM and ROM */
mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
ROMCP_ARB_END_ADDR,
option);
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
IRAM_SIZE,
option);
}
#endif
@ -339,10 +354,10 @@ const struct boot_mode soc_boot_modes[] = {
void s_init(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int is_6q = is_cpu_type(MXC_CPU_MX6Q);
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 mask480;
u32 mask528;
u32 reg, periph1, periph2;
if (is_cpu_type(MXC_CPU_MX6SX))
return;
@ -357,15 +372,23 @@ void s_init(void)
ANATOP_PFD_CLKGATE_MASK(1) |
ANATOP_PFD_CLKGATE_MASK(2) |
ANATOP_PFD_CLKGATE_MASK(3);
mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
ANATOP_PFD_CLKGATE_MASK(1) |
mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
ANATOP_PFD_CLKGATE_MASK(3);
/*
* Don't reset PFD2 on DL/S
*/
if (is_6q)
reg = readl(&ccm->cbcmr);
periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
if ((periph2 != 0x2) && (periph1 != 0x2))
mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
if ((periph2 != 0x1) && (periph1 != 0x1) &&
(periph2 != 0x3) && (periph1 != 0x3))
mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
writel(mask480, &anatop->pfd_480_set);
writel(mask528, &anatop->pfd_528_set);
writel(mask480, &anatop->pfd_480_clr);

10
arch/arm/include/asm/arch-mx31/imx-regs.h
View File

@ -909,9 +909,19 @@ struct esdc_regs {
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
#define MAX_SPI_BYTES 4
#define MXC_SPI_BASE_ADDRESSES \
0x43fa4000, \
0x50010000, \
0x53f84000,
/*
* Generic timer support
*/
#ifdef CONFIG_MX31_CLK32
#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32
#else
#define CONFIG_SYS_TIMER_RATE 32768
#endif
#endif /* __ASM_ARCH_MX31_IMX_REGS_H */

12
arch/arm/include/asm/arch-mx35/imx-regs.h
View File

@ -372,4 +372,16 @@ struct aips_regs {
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
#endif
/*
* Generic timer support
*/
#ifdef CONFIG_MX35_CLK32
#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32
#else
#define CONFIG_SYS_TIMER_RATE 32768
#endif
#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36)
#endif /* __ASM_ARCH_MX35_H */

1
arch/arm/include/asm/arch-mx6/clock.h
View File

@ -53,6 +53,7 @@ u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
void setup_gpmi_io_clk(u32 cfg);
void hab_caam_clock_enable(unsigned char enable);
void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
void enable_uart_clk(unsigned char enable);

16
arch/arm/include/asm/arch-mx6/hab.h
View File

@ -53,11 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
typedef void hapi_clock_init_t(void);
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
#ifdef CONFIG_MX6SX
#define HAB_RVT_BASE 0x00000100
#else
#define HAB_RVT_BASE 0x00000094
#endif
#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)

9
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -215,13 +215,8 @@
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
#ifdef CONFIG_MX6SL
#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#else
#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#endif
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
#ifdef CONFIG_MX6SL

23
board/bachmann/ot1200/Kconfig Normal file
View File

@ -0,0 +1,23 @@
if TARGET_OT1200
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "ot1200"
config SYS_VENDOR
string
default "bachmann"
config SYS_SOC
string
default "mx6"
config SYS_CONFIG_NAME
string
default "ot1200"
endif

6
board/bachmann/ot1200/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
BACHMANN ELECTRONIC OT1200 BOARD
M: Christian Gmeiner <christian.gmeiner@gmail.com>
S: Maintained
F: board/bachmann/ot1200
F: include/configs/ot1200.h
F: configs/ot1200*_defconfig

9
board/bachmann/ot1200/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ot1200.o

20
board/bachmann/ot1200/README Normal file
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@ -0,0 +1,20 @@
U-Boot for the Bachmann electronic GmbH OT1200 devices
There are two different versions of the base board, which differ
in the way ethernet is done. The variant detection is done during
runtime based on the address of the found phy.
- "mr" variant
FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
port is always up and auto-negotiation is not possible.
- normal variant
FEC is connected to a normal phy and auto-negotiation is possible.
The variant name is part of the dtb file name loaded by u-boot. This
make is possible to boot the linux kernel and make use variant specific
devicetree (fixed-phy link).
In order to support different display resoltuions/sizes the OT1200 devices
are making use of EDID data stored in an i2c EEPROM.

0
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg → board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
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251
board/bachmann/ot1200/ot1200.c Normal file
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@ -0,0 +1,251 @@
/*
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
* Copyright (C) 2014, Bachmann electronic GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>
#include <asm/gpio.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};
static void setup_iomux_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_spi();
return 0;
}
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1;
}
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC3_BASE_ADDR},
};
int board_mmc_init(bd_t *bis)
{
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].max_bus_width = 8;
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C3 - IO expander */
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
.gp = IMX_GPIO_NR(3, 17)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
static iomux_v3_cfg_t const pwm_pad[] = {
MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
};
static void leds_on(void)
{
/* turn on all possible leds connected via GPIO expander */
i2c_set_bus_num(2);
pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
}
static void backlight_lcd_off(void)
{
unsigned gpio = IMX_GPIO_NR(2, 0);
gpio_direction_output(gpio, 0);
gpio = IMX_GPIO_NR(2, 3);
gpio_direction_output(gpio, 0);
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
bus = fec_get_miibus(base, -1);
if (!bus)
return 0;
/* scan phy 0 and 5 */
phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
return 0;
}
/* depending on the phy address we can detect our board version */
if (phydev->addr == 0)
setenv("boardver", "");
else
setenv("boardver", "mr");
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret) {
printf("FEC MXC: %s:failed\n", __func__);
free(phydev);
free(bus);
}
return 0;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
backlight_lcd_off();
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
leds_on();
/* enable ecspi3 clocks */
enable_cspi_clock(1, 2);
return 0;
}
int checkboard(void)
{
puts("Board: "CONFIG_SYS_BOARD"\n");
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{NULL, 0},
};
#endif
int misc_init_r(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}

24
board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
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@ -24,18 +24,18 @@ DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

292
board/boundary/nitrogen6x/nitrogen6x.c
View File

@ -28,6 +28,9 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <i2c.h>
#include <input.h>
#include <netdev.h>
#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
@ -70,12 +73,12 @@ int dram_init(void)
return 0;
}
iomux_v3_cfg_t const uart1_pads[] = {
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
@ -83,7 +86,7 @@ iomux_v3_cfg_t const uart2_pads[] = {
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1, SGTL5000 */
struct i2c_pads_info i2c_pad_info0 = {
static struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
@ -97,7 +100,7 @@ struct i2c_pads_info i2c_pad_info0 = {
};
/* I2C2 Camera, MIPI */
struct i2c_pads_info i2c_pad_info1 = {
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
@ -111,7 +114,7 @@ struct i2c_pads_info i2c_pad_info1 = {
};
/* I2C3, J15 - RGB connector */
struct i2c_pads_info i2c_pad_info2 = {
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
@ -124,7 +127,16 @@ struct i2c_pads_info i2c_pad_info2 = {
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@ -134,7 +146,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@ -144,7 +156,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
@ -171,7 +183,7 @@ iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
static iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
@ -189,7 +201,7 @@ static iomux_v3_cfg_t const misc_pads[] = {
};
/* wl1271 pads on nitrogen6x */
iomux_v3_cfg_t const wl12xx_pads[] = {
static iomux_v3_cfg_t const wl12xx_pads[] = {
(MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(WEAK_PULLDOWN),
(MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
@ -235,9 +247,10 @@ static void setup_iomux_enet(void)
gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
udelay(100); /* Wait 100 us before using mii interface */
}
iomux_v3_cfg_t const usb_pads[] = {
static iomux_v3_cfg_t const usb_pads[] = {
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
@ -271,7 +284,7 @@ int board_ehci_power(int port, int on)
#endif
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
@ -279,17 +292,11 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = {
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
IMX_GPIO_NR(2, 6);
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
gpio_direction_input(IMX_GPIO_NR(7, 0));
ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
} else {
gpio_direction_input(IMX_GPIO_NR(2, 6));
ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
}
return ret;
gpio_direction_input(gp_cd);
return !gpio_get_value(gp_cd);
}
int board_mmc_init(bd_t *bis)
@ -333,7 +340,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
}
iomux_v3_cfg_t const ecspi1_pads[] = {
static iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
@ -341,7 +348,7 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};
void setup_spi(void)
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
@ -472,6 +479,17 @@ static void enable_lvds(struct display_info_t const *dev)
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
}
static void enable_lvds_jeida(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
|IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
writel(reg, &iomux->gpr[2]);
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
}
static void enable_rgb(struct display_info_t const *dev)
{
imx_iomux_v3_setup_multiple_pads(
@ -481,10 +499,10 @@ static void enable_rgb(struct display_info_t const *dev)
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.bus = 1,
.addr = 0x50,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.detect = detect_i2c,
.enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
@ -500,6 +518,46 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = enable_lvds_jeida,
.mode = {
.name = "LDB-WXGA",
.refresh = 60,
.xres = 1280,
.yres = 800,
.pixclock = 14065,
.left_margin = 40,
.right_margin = 40,
.upper_margin = 3,
.lower_margin = 80,
.hsync_len = 10,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = enable_lvds,
.mode = {
.name = "LDB-WXGA-S",
.refresh = 60,
.xres = 1280,
.yres = 800,
.pixclock = 14065,
.left_margin = 40,
.right_margin = 40,
.upper_margin = 3,
.lower_margin = 80,
.hsync_len = 10,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x4,
@ -520,6 +578,26 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = NULL,
.enable = enable_lvds,
.mode = {
.name = "LG-9.7",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385, /* ~65MHz */
.left_margin = 480,
.right_margin = 260,
.upper_margin = 16,
.lower_margin = 6,
.hsync_len = 250,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x38,
@ -540,6 +618,86 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x10,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = detect_i2c,
.enable = enable_rgb,
.mode = {
.name = "fusion7",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 33898,
.left_margin = 96,
.right_margin = 24,
.upper_margin = 3,
.lower_margin = 10,
.hsync_len = 72,
.vsync_len = 7,
.sync = 0x40000002,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
.enable = enable_rgb,
.mode = {
.name = "svga",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x41,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = detect_i2c,
.enable = enable_lvds,
.mode = {
.name = "amp1024x600",
.refresh = 60,
.xres = 1024,
.yres = 600,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = 0,
.enable = enable_lvds,
.mode = {
.name = "wvga-lvds",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x48,
@ -560,9 +718,34 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 0,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = enable_rgb,
.mode = {
.name = "qvga",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = 37037,
.left_margin = 38,
.right_margin = 37,
.upper_margin = 16,
.lower_margin = 15,
.hsync_len = 30,
.vsync_len = 3,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
int board_cfb_skip(void)
{
return NULL != getenv("novideo");
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -619,17 +802,62 @@ static void setup_display(void)
}
#endif
static iomux_v3_cfg_t const init_pads[] = {
/* SGTL5000 sys_mclk */
NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
/* J5 - Camera MCLK */
NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
/* wl1271 pads on nitrogen6x */
/* WL12XX_WL_IRQ_GP */
NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
/* WL12XX_WL_ENABLE_GP */
NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
/* WL12XX_BT_ENABLE_GP */
NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
/* USB otg power */
NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
static unsigned gpios_out_low[] = {
/* Disable wl1271 */
IMX_GPIO_NR(6, 15), /* disable wireless */
IMX_GPIO_NR(6, 16), /* disable bluetooth */
IMX_GPIO_NR(3, 22), /* disable USB otg power */
IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
IMX_GPIO_NR(1, 8), /* ov5642 reset */
};
static unsigned gpios_out_high[] = {
IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
};
static void set_gpios(unsigned *p, int cnt, int val)
{
int i;
for (i = 0; i < cnt; i++)
gpio_direction_output(*p++, val);
}
int board_early_init_f(void)
{
setup_iomux_uart();
/* Disable wl1271 For Nitrogen6w */
set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
gpio_direction_input(WL12XX_WL_IRQ_GP);
gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
setup_buttons();
#if defined(CONFIG_VIDEO_IPUV3)
@ -663,6 +891,8 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

169
board/congatec/cgtqmx6eval/imximage.cfg Normal file
View File

@ -0,0 +1,169 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e05ac 0x00020030
DATA 4 0x020e05b4 0x00020030
DATA 4 0x020e0528 0x00020030
DATA 4 0x020e0520 0x00020030
DATA 4 0x020e0514 0x00020030
DATA 4 0x020e0510 0x00020030
DATA 4 0x020e05bc 0x00020030
DATA 4 0x020e05c4 0x00020030
DATA 4 0x020e056c 0x00020030
DATA 4 0x020e0578 0x00020030
DATA 4 0x020e0588 0x00020030
DATA 4 0x020e0594 0x00020030
DATA 4 0x020e057c 0x00020030
DATA 4 0x020e0590 0x00003000
DATA 4 0x020e0598 0x00003000
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0798 0x000C0000
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b000c 0x555A7974
DATA 4 0x021b0010 0xDB538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
DATA 4 0x021b0030 0x005A1023
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b001c 0x04088032
DATA 4 0x021b001c 0x0408803A
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803B
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x19308030
DATA 4 0x021b001c 0x19308038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0800 0xA1380003
DATA 4 0x021b4800 0xA1380003
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b4818 0x00022227
DATA 4 0x021b083c 0x434B0350
DATA 4 0x021b0840 0x034C0359
DATA 4 0x021b483c 0x434B0350
DATA 4 0x021b4840 0x03650348
DATA 4 0x021b0848 0x4436383B
DATA 4 0x021b4848 0x39393341
DATA 4 0x021b0850 0x35373933
DATA 4 0x021b4850 0x48254A36
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x00440044
DATA 4 0x021b4810 0x00440044
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4 0x020c4060 0x000000fb

4
board/freescale/mx6qarm2/MAINTAINERS
View File

@ -1,6 +1,10 @@
MX6QARM2 BOARD
M: Jason Liu <r64343@freescale.com>
M: Ye Li <b37916@freescale.com>
S: Maintained
F: board/freescale/mx6qarm2/
F: include/configs/mx6qarm2.h
F: configs/mx6qarm2_defconfig
F: configs/mx6dlarm2_defconfig
F: configs/mx6qarm2_lpddr2_defconfig
F: configs/mx6dlarm2_lpddr2_defconfig

189
board/freescale/mx6qarm2/imximage.cfg
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -30,6 +30,185 @@ BOOT_FROM sd
* Address absolute address of the register
* value value to be stored in the register
*/
#ifdef CONFIG_MX6DQ_LPDDR2
/* DCD */
DATA 4 0x020C4018 0x60324
DATA 4 0x020E05a8 0x00003038
DATA 4 0x020E05b0 0x00003038
DATA 4 0x020E0524 0x00003038
DATA 4 0x020E051c 0x00003038
DATA 4 0x020E0518 0x00003038
DATA 4 0x020E050c 0x00003038
DATA 4 0x020E05b8 0x00003038
DATA 4 0x020E05c0 0x00003038
DATA 4 0x020E05ac 0x00000038
DATA 4 0x020E05b4 0x00000038
DATA 4 0x020E0528 0x00000038
DATA 4 0x020E0520 0x00000038
DATA 4 0x020E0514 0x00000038
DATA 4 0x020E0510 0x00000038
DATA 4 0x020E05bc 0x00000038
DATA 4 0x020E05c4 0x00000038
DATA 4 0x020E056c 0x00000038
DATA 4 0x020E0578 0x00000038
DATA 4 0x020E0588 0x00000038
DATA 4 0x020E0594 0x00000038
DATA 4 0x020E057c 0x00000038
DATA 4 0x020E0590 0x00000038
DATA 4 0x020E0598 0x00000038
DATA 4 0x020E058c 0x00000000
DATA 4 0x020E059c 0x00000038
DATA 4 0x020E05a0 0x00000038
DATA 4 0x020E0784 0x00000038
DATA 4 0x020E0788 0x00000038
DATA 4 0x020E0794 0x00000038
DATA 4 0x020E079c 0x00000038
DATA 4 0x020E07a0 0x00000038
DATA 4 0x020E07a4 0x00000038
DATA 4 0x020E07a8 0x00000038
DATA 4 0x020E0748 0x00000038
DATA 4 0x020E074c 0x00000038
DATA 4 0x020E0750 0x00020000
DATA 4 0x020E0758 0x00000000
DATA 4 0x020E0774 0x00020000
DATA 4 0x020E078c 0x00000038
DATA 4 0x020E0798 0x00080000
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b401c 0x00008000
DATA 4 0x021b085c 0x1b5f01ff
DATA 4 0x021b485c 0x1b5f01ff
DATA 4 0x021b0800 0xa1390000
DATA 4 0x021b4800 0xa1390000
DATA 4 0x021b0890 0x00400000
DATA 4 0x021b4890 0x00400000
DATA 4 0x021b48bc 0x00055555
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b082c 0xf3333333
DATA 4 0x021b0830 0xf3333333
DATA 4 0x021b0834 0xf3333333
DATA 4 0x021b0838 0xf3333333
DATA 4 0x021b482c 0xf3333333
DATA 4 0x021b4830 0xf3333333
DATA 4 0x021b4834 0xf3333333
DATA 4 0x021b4838 0xf3333333
DATA 4 0x021b0848 0x49383b39
DATA 4 0x021b0850 0x30364738
DATA 4 0x021b4848 0x3e3c3846
DATA 4 0x021b4850 0x4c294b35
DATA 4 0x021b083c 0x20000000
DATA 4 0x021b0840 0x0
DATA 4 0x021b483c 0x20000000
DATA 4 0x021b4840 0x0
DATA 4 0x021b0858 0xf00
DATA 4 0x021b4858 0xf00
DATA 4 0x021b08b8 0x800
DATA 4 0x021b48b8 0x800
DATA 4 0x021b000c 0x555a61a5
DATA 4 0x021b0004 0x20036
DATA 4 0x021b0010 0x160e83
DATA 4 0x021b0014 0xdd
DATA 4 0x021b0018 0x8174c
DATA 4 0x021b002c 0xf9f26d2
DATA 4 0x021b0030 0x20e
DATA 4 0x021b0038 0x200aac
DATA 4 0x021b0008 0x0
DATA 4 0x021b0040 0x5f
DATA 4 0x021b0000 0xc3010000
DATA 4 0x021b400c 0x555a61a5
DATA 4 0x021b4004 0x20036
DATA 4 0x021b4010 0x160e83
DATA 4 0x021b4014 0xdd
DATA 4 0x021b4018 0x8174c
DATA 4 0x021b402c 0xf9f26d2
DATA 4 0x021b4030 0x20e
DATA 4 0x021b4038 0x200aac
DATA 4 0x021b4008 0x0
DATA 4 0x021b4040 0x3f
DATA 4 0x021b4000 0xc3010000
DATA 4 0x021b001c 0x3f8030
DATA 4 0x021b001c 0xff0a8030
DATA 4 0x021b001c 0xc2018030
DATA 4 0x021b001c 0x6028030
DATA 4 0x021b001c 0x2038030
DATA 4 0x021b401c 0x3f8030
DATA 4 0x021b401c 0xff0a8030
DATA 4 0x021b401c 0xc2018030
DATA 4 0x021b401c 0x6028030
DATA 4 0x021b401c 0x2038030
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b4800 0xa1390003
DATA 4 0x021b0020 0x7800
DATA 4 0x021b4020 0x7800
DATA 4 0x021b0818 0x0
DATA 4 0x021b4818 0x0
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b4800 0xa1390003
DATA 4 0x021b08b8 0x800
DATA 4 0x021b48b8 0x800
DATA 4 0x021b001c 0x0
DATA 4 0x021b401c 0x0
DATA 4 0x021b0404 0x00011006
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#else
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@ -142,12 +321,8 @@ DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
DATA 4 0x020e0010 0xF00000FF
DATA 4 0x020e0018 0x00070007
DATA 4 0x020e001c 0x00070007
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC00
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
@ -159,3 +334,5 @@ DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#endif /* CONFIG_MX6DQ_LPDDR2 */

462
board/freescale/mx6qarm2/imximage_mx6dl.cfg Normal file
View File

@ -0,0 +1,462 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifdef CONFIG_MX6DL_LPDDR2
/* IOMUX SETTINGS */
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
DATA 4 0x020E04bc 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
DATA 4 0x020E04c0 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
DATA 4 0x020E04c4 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
DATA 4 0x020E04c8 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
DATA 4 0x020E04cc 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
DATA 4 0x020E04d0 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
DATA 4 0x020E04d4 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
DATA 4 0x020E04d8 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
DATA 4 0x020E0470 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
DATA 4 0x020E0474 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
DATA 4 0x020E0478 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
DATA 4 0x020E047c 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
DATA 4 0x020E0480 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
DATA 4 0x020E0484 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
DATA 4 0x020E0488 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
DATA 4 0x020E048c 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
DATA 4 0x020E0464 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
DATA 4 0x020E0490 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
DATA 4 0x020E04ac 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
DATA 4 0x020E04b0 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
DATA 4 0x020E0494 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
DATA 4 0x020E04a4 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
DATA 4 0x020E04a8 0x00000038
/*
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
* DSE can be configured using Group Control Register:
* IOMUXC_SW_PAD_CTL_GRP_CTLDS
*/
DATA 4 0x020E04a0 0x00000000
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
DATA 4 0x020E04b4 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
DATA 4 0x020E04b8 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
DATA 4 0x020E0764 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
DATA 4 0x020E0770 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
DATA 4 0x020E0778 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
DATA 4 0x020E077c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
DATA 4 0x020E0780 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
DATA 4 0x020E0784 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
DATA 4 0x020E078c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
DATA 4 0x020E0748 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
DATA 4 0x020E074c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
DATA 4 0x020E076c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
DATA 4 0x020E0750 0x00020000
/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
DATA 4 0x020E0754 0x00000000
/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
DATA 4 0x020E0760 0x00020000
/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
DATA 4 0x020E0774 0x00080000
/*
* DDR Controller Registers
*
* Manufacturer: Mocron
* Device Part Number: MT42L64M64D2KH-18
* Clock Freq.: 528MHz
* MMDC channels: Both MMDC0, MMDC1
*Density per CS in Gb: 256M
* Chip Selects used: 2
* Number of Banks: 8
* Row address: 14
* Column address: 9
* Data bus width 32
*/
/* MMDC_P0_BASE_ADDR = 0x021b0000 */
/* MMDC_P1_BASE_ADDR = 0x021b4000 */
/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
DATA 4 0x021b001c 0x00008000
/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
DATA 4 0x021b401c 0x00008000
/*LPDDR2 ZQ params */
DATA 4 0x021b085c 0x1b5f01ff
DATA 4 0x021b485c 0x1b5f01ff
/* Calibration setup. */
/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
DATA 4 0x021b0800 0xa1390003
/*ca bus abs delay */
DATA 4 0x021b0890 0x00400000
/*ca bus abs delay */
DATA 4 0x021b4890 0x00400000
/* values of 20,40,50,60,7f tried. no difference seen */
/* DDR_PHY_P1_MPWRCADL */
DATA 4 0x021b48bc 0x00055555
/*frc_msr.*/
DATA 4 0x021b08b8 0x00000800
/*frc_msr.*/
DATA 4 0x021b48b8 0x00000800
/* DDR_PHY_P0_MPREDQBY0DL3 */
DATA 4 0x021b081c 0x33333333
/* DDR_PHY_P0_MPREDQBY1DL3 */
DATA 4 0x021b0820 0x33333333
/* DDR_PHY_P0_MPREDQBY2DL3 */
DATA 4 0x021b0824 0x33333333
/* DDR_PHY_P0_MPREDQBY3DL3 */
DATA 4 0x021b0828 0x33333333
/* DDR_PHY_P1_MPREDQBY0DL3 */
DATA 4 0x021b481c 0x33333333
/* DDR_PHY_P1_MPREDQBY1DL3 */
DATA 4 0x021b4820 0x33333333
/* DDR_PHY_P1_MPREDQBY2DL3 */
DATA 4 0x021b4824 0x33333333
/* DDR_PHY_P1_MPREDQBY3DL3 */
DATA 4 0x021b4828 0x33333333
/*
* Read and write data delay, per byte.
* For optimized DDR operation it is recommended to run mmdc_calibration
* on your board, and replace 4 delay register assigns with resulted values
* Note:
* a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
* should be skipped, or the write/read calibration comming after that
* will stall
* b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
*/
DATA 4 0x021b0848 0x4b4b524f
DATA 4 0x021b4848 0x494f4c44
DATA 4 0x021b0850 0x3c3d303c
DATA 4 0x021b4850 0x3c343d38
/*dqs gating dis */
DATA 4 0x021b083c 0x20000000
DATA 4 0x021b0840 0x0
DATA 4 0x021b483c 0x20000000
DATA 4 0x021b4840 0x0
/*clk delay */
DATA 4 0x021b0858 0xa00
/*clk delay */
DATA 4 0x021b4858 0xa00
/*frc_msr */
DATA 4 0x021b08b8 0x00000800
/*frc_msr */
DATA 4 0x021b48b8 0x00000800
/* Calibration setup end */
/* Channel0 - startng address 0x80000000 */
/* MMDC0_MDCFG0 */
DATA 4 0x021b000c 0x34386145
/* MMDC0_MDPDC */
DATA 4 0x021b0004 0x00020036
/* MMDC0_MDCFG1 */
DATA 4 0x021b0010 0x00100c83
/* MMDC0_MDCFG2 */
DATA 4 0x021b0014 0x000000Dc
/* MMDC0_MDMISC */
DATA 4 0x021b0018 0x0000174C
/* MMDC0_MDRWD;*/
DATA 4 0x021b002c 0x0f9f26d2
/* MMDC0_MDOR */
DATA 4 0x021b0030 0x0000020e
/* MMDC0_MDCFG3LP */
DATA 4 0x021b0038 0x00190778
/* MMDC0_MDOTC */
DATA 4 0x021b0008 0x00000000
/* CS0_END */
DATA 4 0x021b0040 0x0000005f
/* ROC */
DATA 4 0x021b0404 0x0000000f
/* MMDC0_MDCTL */
DATA 4 0x021b0000 0xc3010000
/* Channel1 - starting address 0x10000000 */
/* MMDC1_MDCFG0 */
DATA 4 0x021b400c 0x34386145
/* MMDC1_MDPDC */
DATA 4 0x021b4004 0x00020036
/* MMDC1_MDCFG1 */
DATA 4 0x021b4010 0x00100c83
/* MMDC1_MDCFG2 */
DATA 4 0x021b4014 0x000000Dc
/* MMDC1_MDMISC */
DATA 4 0x021b4018 0x0000174C
/* MMDC1_MDRWD;*/
DATA 4 0x021b402c 0x0f9f26d2
/* MMDC1_MDOR */
DATA 4 0x021b4030 0x0000020e
/* MMDC1_MDCFG3LP */
DATA 4 0x021b4038 0x00190778
/* MMDC1_MDOTC */
DATA 4 0x021b4008 0x00000000
/* CS0_END */
DATA 4 0x021b4040 0x0000003f
/* MMDC1_MDCTL */
DATA 4 0x021b4000 0xc3010000
/* Channel0 : Configure DDR device:*/
/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
DATA 4 0x021b001c 0x003f8030
/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
DATA 4 0x021b001c 0xff0a8030
/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
DATA 4 0x021b001c 0xa2018030
/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
DATA 4 0x021b001c 0x06028030
/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
DATA 4 0x021b001c 0x01038030
/* Channel1 : Configure DDR device:*/
/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
DATA 4 0x021b401c 0x003f8030
/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
DATA 4 0x021b401c 0xff0a8030
/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
DATA 4 0x021b401c 0xa2018030
/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
DATA 4 0x021b401c 0x06028030
/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
DATA 4 0x021b401c 0x01038030
/* MMDC0_MDREF */
DATA 4 0x021b0020 0x00005800
/* MMDC1_MDREF */
DATA 4 0x021b4020 0x00005800
/* DDR_PHY_P0_MPODTCTRL */
DATA 4 0x021b0818 0x0
/* DDR_PHY_P1_MPODTCTRL */
DATA 4 0x021b4818 0x0
/*
* calibration values based on calibration compare of 0x00ffff00:
* Note, these calibration values are based on Freescale's board
* May need to run calibration on target board to fine tune these
*/
/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
DATA 4 0x021b0800 0xa1310003
/* DDR_PHY_P0_MPMUR0, frc_msr */
DATA 4 0x021b08b8 0x00000800
/* DDR_PHY_P1_MPMUR0, frc_msr */
DATA 4 0x021b48b8 0x00000800
/*
* MMDC0_MDSCR, clear this register
* (especially the configuration bit as initialization is complete)
*/
DATA 4 0x021b001c 0x00000000
/*
* MMDC0_MDSCR, clear this register
* (especially the configuration bit as initialization is complete)
*/
DATA 4 0x021b401c 0x00000000
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
DATA 4 0x020e0010 0xF00000CF
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#else /* CONFIG_MX6DL_LPDDR2 */
DATA 4 0x020e0798 0x000c0000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0588 0x00000030
DATA 4 0x020e0594 0x00000030
DATA 4 0x020e056c 0x00000030
DATA 4 0x020e0578 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e057c 0x00000030
DATA 4 0x020e0590 0x00003000
DATA 4 0x020e0598 0x00003000
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e05ac 0x00000030
DATA 4 0x020e05b4 0x00000030
DATA 4 0x020e0528 0x00000030
DATA 4 0x020e0520 0x00000030
DATA 4 0x020e0514 0x00000030
DATA 4 0x020e0510 0x00000030
DATA 4 0x020e05bc 0x00000030
DATA 4 0x020e05c4 0x00000030
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b4800 0xa1390003
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x00370037
DATA 4 0x021b4810 0x00370037
DATA 4 0x021b083c 0x422f0220
DATA 4 0x021b0840 0x021f0219
DATA 4 0x021b483C 0x422f0220
DATA 4 0x021b4840 0x022d022f
DATA 4 0x021b0848 0x47494b49
DATA 4 0x021b4848 0x48484c47
DATA 4 0x021b0850 0x39382b2f
DATA 4 0x021b4850 0x2f35312c
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b0004 0x0002002d
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x40445323
DATA 4 0x021b0010 0xb66e8c63
DATA 4 0x021b0014 0x01ff00db
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x00440e21
#ifdef CONFIG_DDR_32BIT
DATA 4 0x021b0040 0x00000017
DATA 4 0x021b0000 0xc3190000
#else
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0xc31a0000
#endif
DATA 4 0x021b001c 0x04008032
DATA 4 0x021b001c 0x0400803a
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803b
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x07208030
DATA 4 0x021b001c 0x07208038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00000007
DATA 4 0x021b4818 0x00000007
DATA 4 0x021b0004 0x0002556d
DATA 4 0x021b4004 0x00011006
DATA 4 0x021b001c 0x00000000
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
DATA 4 0x020e0010 0xF00000CF
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#endif /* CONFIG_MX6DL_LPDDR2 */

11
board/freescale/mx6qarm2/mx6qarm2.c
View File

@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
defined(CONFIG_DDR_32BIT)
gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
#else
gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
#endif
return 0;
}
@ -224,7 +229,11 @@ int board_init(void)
int checkboard(void)
{
#ifdef CONFIG_MX6DL
puts("Board: MX6DL-Armadillo2\n");
#else
puts("Board: MX6Q-Armadillo2\n");
#endif
return 0;
}

16
board/freescale/mx6qsabreauto/mx6qsabreauto.c
View File

@ -50,12 +50,12 @@ int dram_init(void)
return 0;
}
iomux_v3_cfg_t const uart4_pads[] = {
static iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads[] = {
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
@ -74,7 +74,7 @@ iomux_v3_cfg_t const enet_pads[] = {
};
/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
struct i2c_pads_info i2c_pad_info1 = {
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
@ -91,7 +91,7 @@ struct i2c_pads_info i2c_pad_info1 = {
* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
* Compass Sensor, Accelerometer, Res Touch
*/
struct i2c_pads_info i2c_pad_info2 = {
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
@ -104,11 +104,11 @@ struct i2c_pads_info i2c_pad_info2 = {
}
};
iomux_v3_cfg_t const i2c3_pads[] = {
static iomux_v3_cfg_t const i2c3_pads[] = {
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const port_exp[] = {
static iomux_v3_cfg_t const port_exp[] = {
MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
@ -117,7 +117,7 @@ static void setup_iomux_enet(void)
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
iomux_v3_cfg_t const usdhc3_pads[] = {
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@ -138,7 +138,7 @@ static void setup_iomux_uart(void)
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[1] = {
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC3_BASE_ADDR},
};

169
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg Normal file
View File

@ -0,0 +1,169 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e05ac 0x00020030
DATA 4 0x020e05b4 0x00020030
DATA 4 0x020e0528 0x00020030
DATA 4 0x020e0520 0x00020030
DATA 4 0x020e0514 0x00020030
DATA 4 0x020e0510 0x00020030
DATA 4 0x020e05bc 0x00020030
DATA 4 0x020e05c4 0x00020030
DATA 4 0x020e056c 0x00020030
DATA 4 0x020e0578 0x00020030
DATA 4 0x020e0588 0x00020030
DATA 4 0x020e0594 0x00020030
DATA 4 0x020e057c 0x00020030
DATA 4 0x020e0590 0x00003000
DATA 4 0x020e0598 0x00003000
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0798 0x000C0000
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b000c 0x555A7974
DATA 4 0x021b0010 0xDB538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
DATA 4 0x021b0030 0x005A1023
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b001c 0x04088032
DATA 4 0x021b001c 0x0408803A
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803B
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x19308030
DATA 4 0x021b001c 0x19308038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0800 0xA1380003
DATA 4 0x021b4800 0xA1380003
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b4818 0x00022227
DATA 4 0x021b083c 0x434B0350
DATA 4 0x021b0840 0x034C0359
DATA 4 0x021b483c 0x434B0350
DATA 4 0x021b4840 0x03650348
DATA 4 0x021b0848 0x4436383B
DATA 4 0x021b4848 0x39393341
DATA 4 0x021b0850 0x35373933
DATA 4 0x021b4850 0x48254A36
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x00440044
DATA 4 0x021b4810 0x00440044
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4 0x020c4060 0x000000fb

2
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View File

@ -157,7 +157,7 @@ int board_eth_init(bd_t *bis)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,

1
board/freescale/vf610twr/MAINTAINERS
View File

@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/vf610twr/
F: include/configs/vf610twr.h
F: configs/vf610twr_defconfig
F: configs/vf610twr_nand_defconfig

47
board/freescale/vf610twr/vf610twr.c
View File

@ -304,6 +304,39 @@ static void setup_iomux_i2c(void)
imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
}
#ifdef CONFIG_NAND_VF610_NFC
static void setup_iomux_nfc(void)
{
static const iomux_v3_cfg_t nfc_pads[] = {
VF610_PAD_PTD31__NF_IO15,
VF610_PAD_PTD30__NF_IO14,
VF610_PAD_PTD29__NF_IO13,
VF610_PAD_PTD28__NF_IO12,
VF610_PAD_PTD27__NF_IO11,
VF610_PAD_PTD26__NF_IO10,
VF610_PAD_PTD25__NF_IO9,
VF610_PAD_PTD24__NF_IO8,
VF610_PAD_PTD23__NF_IO7,
VF610_PAD_PTD22__NF_IO6,
VF610_PAD_PTD21__NF_IO5,
VF610_PAD_PTD20__NF_IO4,
VF610_PAD_PTD19__NF_IO3,
VF610_PAD_PTD18__NF_IO2,
VF610_PAD_PTD17__NF_IO1,
VF610_PAD_PTD16__NF_IO0,
VF610_PAD_PTB24__NF_WE_B,
VF610_PAD_PTB25__NF_CE0_B,
VF610_PAD_PTB27__NF_RE_B,
VF610_PAD_PTC26__NF_RB_B,
VF610_PAD_PTC27__NF_ALE,
VF610_PAD_PTC28__NF_CLE
};
imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
}
#endif
static void setup_iomux_qspi(void)
{
static const iomux_v3_cfg_t qspi0_pads[] = {
@ -380,6 +413,8 @@ static void clock_init(void)
CCM_CCGR7_SDHC1_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
CCM_CCGR10_NFC_CTRL_MASK);
clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
@ -399,14 +434,17 @@ static void clock_init(void)
CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
CCM_CACRR_ARM_CLK_DIV(0));
clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
CCM_CSCMR1_NFC_CLK_SEL(0));
clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
CCM_CSCDR1_RMII_CLK_EN);
clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
CCM_CSCDR2_NFC_EN);
clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
CCM_CSCDR3_NFC_PRE_DIV(5));
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
CCM_CSCMR2_RMII_CLK_SEL(0));
}
@ -437,6 +475,9 @@ int board_early_init_f(void)
setup_iomux_enet();
setup_iomux_i2c();
setup_iomux_qspi();
#ifdef CONFIG_NAND_VF610_NFC
setup_iomux_nfc();
#endif
return 0;
}

7
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -402,13 +402,6 @@ void board_init_f(ulong dummy)
struct ventana_board_info ventana_info;
int board_model;
/*
* Zero out global data:
* - this shoudl be done by crt0.S
* - failure to zero it will cause i2c_setup to fail
*/
memset((void *)gd, 0, sizeof(struct global_data));
/* setup AIPS and disable watchdog */
arch_cpu_init();

52
board/olimex/mx23_olinuxino/mx23_olinuxino.c
View File

@ -30,14 +30,26 @@ int board_early_init_f(void)
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
#ifdef CONFIG_CMD_USB
/* Enable LAN9512 */
gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
#endif
return 0;
}
#ifdef CONFIG_CMD_USB
int board_ehci_hcd_init(int port)
{
/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
udelay(100);
return 0;
}
int board_ehci_hcd_exit(int port)
{
/* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
return 0;
}
#endif
int dram_init(void)
{
return mxs_dram_init();
@ -66,3 +78,33 @@ int board_init(void)
return 0;
}
/* Fine-tune the DRAM configuration. */
void mxs_adjust_memory_params(uint32_t *dram_vals)
{
/* Enable Auto Precharge. */
dram_vals[3] |= 1 << 8;
/* Enable Fast Writes. */
dram_vals[5] |= 1 << 8;
/* tEMRS = 3*tCK */
dram_vals[10] &= ~(0x3 << 8);
dram_vals[10] |= (0x3 << 8);
/* CASLAT = 3*tCK */
dram_vals[11] &= ~(0x3 << 0);
dram_vals[11] |= (0x3 << 0);
/* tCKE = 1*tCK */
dram_vals[12] &= ~(0x7 << 0);
dram_vals[12] |= (0x1 << 0);
/* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
/* tDAL = 6*tCK */
dram_vals[15] &= ~(0xf << 16);
dram_vals[15] |= (0x6 << 16);
/* tREF = 1040*tCK */
dram_vals[26] &= ~0xffff;
dram_vals[26] |= 0x0410;
/* tRAS_MAX = 9334*tCK */
dram_vals[32] &= ~0xffff;
dram_vals[32] |= 0x2475;
}

2
configs/cgtqmx6qeval_defconfig
View File

@ -1,3 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
CONFIG_ARM=y
CONFIG_TARGET_CGTQMX6EVAL=y

3
configs/mx6dlarm2_defconfig Normal file
View File

@ -0,0 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y

3
configs/mx6dlarm2_lpddr2_defconfig Normal file
View File

@ -0,0 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y

2
configs/mx6qarm2_defconfig
View File

@ -1,3 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y

3
configs/mx6qarm2_lpddr2_defconfig Normal file
View File

@ -0,0 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
CONFIG_ARM=y
CONFIG_TARGET_MX6QARM2=y

2
configs/mx6qsabresd_defconfig
View File

@ -1,3 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_ARM=y
CONFIG_TARGET_MX6SABRESD=y

3
configs/ot1200_defconfig Normal file
View File

@ -0,0 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_ARM=y
CONFIG_TARGET_OT1200=y

2
configs/vf610twr_defconfig
View File

@ -1,3 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
CONFIG_ARM=y
CONFIG_TARGET_VF610TWR=y

3
configs/vf610twr_nand_defconfig Normal file
View File

@ -0,0 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
CONFIG_ARM=y
CONFIG_TARGET_VF610TWR=y

1
drivers/mtd/nand/Makefile
View File

@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
obj-$(CONFIG_NAND_NDFC) += ndfc.o

724
drivers/mtd/nand/vf610_nfc.c Normal file
View File

@ -0,0 +1,724 @@
/*
* Copyright 2009-2014 Freescale Semiconductor, Inc. and others
*
* Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
* Ported to U-Boot by Stefan Agner
* Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
* Jason ported to M54418TWR and MVFA5.
* Authors: Stefan Agner <stefan.agner@toradex.com>
* Bill Pringlemeir <bpringlemeir@nbsps.com>
* Shaohui Xie <b21989@freescale.com>
* Jason Jin <Jason.jin@freescale.com>
*
* Based on original driver mpc5121_nfc.c.
*
* This is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Limitations:
* - Untested on MPC5125 and M54418.
* - DMA not used.
* - 2K pages or less.
* - Only 2K page w. 64+OOB and hardware ECC.
*/
#include <common.h>
#include <malloc.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <nand.h>
#include <errno.h>
#include <asm/io.h>
/* Register Offsets */
#define NFC_FLASH_CMD1 0x3F00
#define NFC_FLASH_CMD2 0x3F04
#define NFC_COL_ADDR 0x3F08
#define NFC_ROW_ADDR 0x3F0c
#define NFC_ROW_ADDR_INC 0x3F14
#define NFC_FLASH_STATUS1 0x3F18
#define NFC_FLASH_STATUS2 0x3F1c
#define NFC_CACHE_SWAP 0x3F28
#define NFC_SECTOR_SIZE 0x3F2c
#define NFC_FLASH_CONFIG 0x3F30
#define NFC_IRQ_STATUS 0x3F38
/* Addresses for NFC MAIN RAM BUFFER areas */
#define NFC_MAIN_AREA(n) ((n) * 0x1000)
#define PAGE_2K 0x0800
#define OOB_64 0x0040
/*
* NFC_CMD2[CODE] values. See section:
* - 31.4.7 Flash Command Code Description, Vybrid manual
* - 23.8.6 Flash Command Sequencer, MPC5125 manual
*
* Briefly these are bitmasks of controller cycles.
*/
#define READ_PAGE_CMD_CODE 0x7EE0
#define PROGRAM_PAGE_CMD_CODE 0x7FC0
#define ERASE_CMD_CODE 0x4EC0
#define READ_ID_CMD_CODE 0x4804
#define RESET_CMD_CODE 0x4040
#define STATUS_READ_CMD_CODE 0x4068
/* NFC ECC mode define */
#define ECC_BYPASS 0
#define ECC_45_BYTE 6
/*** Register Mask and bit definitions */
/* NFC_FLASH_CMD1 Field */
#define CMD_BYTE2_MASK 0xFF000000
#define CMD_BYTE2_SHIFT 24
/* NFC_FLASH_CM2 Field */
#define CMD_BYTE1_MASK 0xFF000000
#define CMD_BYTE1_SHIFT 24
#define CMD_CODE_MASK 0x00FFFF00
#define CMD_CODE_SHIFT 8
#define BUFNO_MASK 0x00000006
#define BUFNO_SHIFT 1
#define START_BIT (1<<0)
/* NFC_COL_ADDR Field */
#define COL_ADDR_MASK 0x0000FFFF
#define COL_ADDR_SHIFT 0
/* NFC_ROW_ADDR Field */
#define ROW_ADDR_MASK 0x00FFFFFF
#define ROW_ADDR_SHIFT 0
#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
#define ROW_ADDR_CHIP_SEL_SHIFT 24
/* NFC_FLASH_STATUS2 Field */
#define STATUS_BYTE1_MASK 0x000000FF
/* NFC_FLASH_CONFIG Field */
#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
#define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
#define CONFIG_DMA_REQ_BIT (1<<20)
#define CONFIG_ECC_MODE_MASK 0x000E0000
#define CONFIG_ECC_MODE_SHIFT 17
#define CONFIG_FAST_FLASH_BIT (1<<16)
#define CONFIG_16BIT (1<<7)
#define CONFIG_BOOT_MODE_BIT (1<<6)
#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
#define CONFIG_PAGE_CNT_MASK 0xF
#define CONFIG_PAGE_CNT_SHIFT 0
/* NFC_IRQ_STATUS Field */
#define IDLE_IRQ_BIT (1<<29)
#define IDLE_EN_BIT (1<<20)
#define CMD_DONE_CLEAR_BIT (1<<18)
#define IDLE_CLEAR_BIT (1<<17)
#define NFC_TIMEOUT (1000)
/* ECC status placed at end of buffers. */
#define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3)
#define ECC_STATUS_MASK 0x80
#define ECC_ERR_COUNT 0x3F
/*
* ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
* and +7 for big-endian SOC.
*/
#ifdef CONFIG_VF610
#define ECC_OFFSET 4
#else
#define ECC_OFFSET 7
#endif
struct vf610_nfc {
struct mtd_info *mtd;
struct nand_chip chip;
void __iomem *regs;
uint column;
int spareonly;
int page;
/* Status and ID are in alternate locations. */
int alt_buf;
#define ALT_BUF_ID 1
#define ALT_BUF_STAT 2
struct clk *clk;
};
#define mtd_to_nfc(_mtd) \
(struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
static struct nand_bbt_descr bbt_main_descr = {
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
NAND_BBT_2BIT | NAND_BBT_VERSION,
.offs = 11,
.len = 4,
.veroffs = 15,
.maxblocks = 4,
.pattern = bbt_pattern,
};
static struct nand_bbt_descr bbt_mirror_descr = {
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
NAND_BBT_2BIT | NAND_BBT_VERSION,
.offs = 11,
.len = 4,
.veroffs = 15,
.maxblocks = 4,
.pattern = mirror_pattern,
};
static struct nand_ecclayout vf610_nfc_ecc45 = {
.eccbytes = 45,
.eccpos = {19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37, 38, 39,
40, 41, 42, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63},
.oobfree = {
{.offset = 8,
.length = 11} }
};
static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
return readl(nfc->regs + reg);
}
static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
writel(val, nfc->regs + reg);
}
static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
{
vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
}
static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
{
vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
}
static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
u32 mask, u32 shift, u32 val)
{
vf610_nfc_write(mtd, reg,
(vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
}
static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
{
/*
* Use this accessor for the interal SRAM buffers. On ARM we can
* treat the SRAM buffer as if its memory, hence use memcpy
*/
memcpy(dst, src, n);
}
/* Clear flags for upcoming command */
static inline void vf610_nfc_clear_status(void __iomem *regbase)
{
void __iomem *reg = regbase + NFC_IRQ_STATUS;
u32 tmp = __raw_readl(reg);
tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
__raw_writel(tmp, reg);
}
/* Wait for complete operation */
static inline void vf610_nfc_done(struct mtd_info *mtd)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
uint start;
/*
* Barrier is needed after this write. This write need
* to be done before reading the next register the first
* time.
* vf610_nfc_set implicates such a barrier by using writel
* to write to the register.
*/
vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
start = get_timer(0);
while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
if (get_timer(start) > NFC_TIMEOUT) {
printf("Timeout while waiting for !BUSY.\n");
return;
}
}
vf610_nfc_clear_status(nfc->regs);
}
static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
{
u32 flash_id;
if (col < 4) {
flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
return (flash_id >> (3-col)*8) & 0xff;
} else {
flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
return flash_id >> 24;
}
}
static u8 vf610_nfc_get_status(struct mtd_info *mtd)
{
return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
}
/* Single command */
static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
u32 cmd_code)
{
void __iomem *reg = regbase + NFC_FLASH_CMD2;
u32 tmp;
vf610_nfc_clear_status(regbase);
tmp = __raw_readl(reg);
tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
tmp |= cmd_code << CMD_CODE_SHIFT;
__raw_writel(tmp, reg);
}
/* Two commands */
static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
u32 cmd_byte2, u32 cmd_code)
{
void __iomem *reg = regbase + NFC_FLASH_CMD1;
u32 tmp;
vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
tmp = __raw_readl(reg);
tmp &= ~CMD_BYTE2_MASK;
tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
__raw_writel(tmp, reg);
}
static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
{
if (column != -1) {
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
if (nfc->chip.options | NAND_BUSWIDTH_16)
column = column/2;
vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
COL_ADDR_SHIFT, column);
}
if (page != -1)
vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
ROW_ADDR_SHIFT, page);
}
/* Send command to NAND chip */
static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
int column, int page)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
nfc->column = max(column, 0);
nfc->spareonly = 0;
nfc->alt_buf = 0;
switch (command) {
case NAND_CMD_PAGEPROG:
nfc->page = -1;
vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
command, PROGRAM_PAGE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_RESET:
vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
break;
/*
* NFC does not support sub-page reads and writes,
* so emulate them using full page transfers.
*/
case NAND_CMD_READOOB:
nfc->spareonly = 1;
case NAND_CMD_SEQIN: /* Pre-read for partial writes. */
case NAND_CMD_READ0:
column = 0;
/* Already read? */
if (nfc->page == page)
return;
nfc->page = page;
vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_ERASE1:
if (nfc->page == page)
nfc->page = -1;
vf610_nfc_send_commands(nfc->regs, command,
NAND_CMD_ERASE2, ERASE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_READID:
nfc->alt_buf = ALT_BUF_ID;
vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
break;
case NAND_CMD_STATUS:
nfc->alt_buf = ALT_BUF_STAT;
vf610_nfc_send_command(nfc->regs, command,
STATUS_READ_CMD_CODE);
break;
default:
return;
}
vf610_nfc_done(mtd);
}
static inline void vf610_nfc_read_spare(struct mtd_info *mtd, void *buf,
int len)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
len = min(mtd->oobsize, (uint)len);
if (len > 0)
vf610_nfc_memcpy(buf, nfc->regs + mtd->writesize, len);
}
/* Read data from NFC buffers */
static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
uint c = nfc->column;
uint l;
/* Handle main area */
if (!nfc->spareonly) {
l = min((uint)len, mtd->writesize - c);
nfc->column += l;
if (!nfc->alt_buf)
vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c,
l);
else
if (nfc->alt_buf & ALT_BUF_ID)
*buf = vf610_nfc_get_id(mtd, c);
else
*buf = vf610_nfc_get_status(mtd);
buf += l;
len -= l;
}
/* Handle spare area access */
if (len) {
nfc->column += len;
vf610_nfc_read_spare(mtd, buf, len);
}
}
/* Write data to NFC buffers */
static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf,
int len)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
uint c = nfc->column;
uint l;
l = min((uint)len, mtd->writesize + mtd->oobsize - c);
nfc->column += l;
vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
}
/* Read byte from NFC buffers */
static u8 vf610_nfc_read_byte(struct mtd_info *mtd)
{
u8 tmp;
vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp));
return tmp;
}
/* Read word from NFC buffers */
static u16 vf610_nfc_read_word(struct mtd_info *mtd)
{
u16 tmp;
vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
return tmp;
}
/* If not provided, upper layers apply a fixed delay. */
static int vf610_nfc_dev_ready(struct mtd_info *mtd)
{
/* NFC handles R/B internally; always ready. */
return 1;
}
/*
* This function supports Vybrid only (MPC5125 would have full RB and four CS)
*/
static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
{
#ifdef CONFIG_VF610
u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
if (chip == 0)
tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT;
else if (chip == 1)
tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT;
vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
#endif
}
/* Count the number of 0's in buff upto max_bits */
static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
{
uint32_t *buff32 = (uint32_t *)buff;
int k, written_bits = 0;
for (k = 0; k < (size / 4); k++) {
written_bits += hweight32(~buff32[k]);
if (written_bits > max_bits)
break;
}
return written_bits;
}
static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat)
{
struct vf610_nfc *nfc = mtd_to_nfc(mtd);
u8 ecc_status;
u8 ecc_count;
int flip;
ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET);
ecc_count = ecc_status & ECC_ERR_COUNT;
if (!(ecc_status & ECC_STATUS_MASK))
return ecc_count;
/* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
/* ECC failed. */
if (flip > ecc_count) {
nfc->page = -1;
return -1;
}
/* Erased page. */
memset(dat, 0xff, nfc->chip.ecc.size);
return 0;
}
static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
int eccsize = chip->ecc.size;
int stat;
uint8_t *p = buf;
vf610_nfc_read_buf(mtd, p, eccsize);
if (oob_required)
vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
stat = vf610_nfc_correct_data(mtd, p);
if (stat < 0)
mtd->ecc_stats.failed++;
else
mtd->ecc_stats.corrected += stat;
return 0;
}
/*
* ECC will be calculated automatically
*/
static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
const uint8_t *buf, int oob_required)
{
vf610_nfc_write_buf(mtd, buf, mtd->writesize);
if (oob_required)
vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
return 0;
}
struct vf610_nfc_config {
int hardware_ecc;
int width;
int flash_bbt;
};
static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
{
struct mtd_info *mtd = &nand_info[devnum];
struct nand_chip *chip;
struct vf610_nfc *nfc;
int err = 0;
int page_sz;
struct vf610_nfc_config cfg = {
.hardware_ecc = 1,
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
.width = 16,
#else
.width = 8,
#endif
.flash_bbt = 1,
};
nfc = malloc(sizeof(*nfc));
if (!nfc) {
printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
return -ENOMEM;
}
chip = &nfc->chip;
nfc->regs = addr;
mtd->priv = chip;
chip->priv = nfc;
if (cfg.width == 16) {
chip->options |= NAND_BUSWIDTH_16;
vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
} else {
chip->options &= ~NAND_BUSWIDTH_16;
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
}
chip->dev_ready = vf610_nfc_dev_ready;
chip->cmdfunc = vf610_nfc_command;
chip->read_byte = vf610_nfc_read_byte;
chip->read_word = vf610_nfc_read_word;
chip->read_buf = vf610_nfc_read_buf;
chip->write_buf = vf610_nfc_write_buf;
chip->select_chip = vf610_nfc_select_chip;
/* Bad block options. */
if (cfg.flash_bbt)
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE;
/* Default to software ECC until flash ID. */
vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
CONFIG_ECC_MODE_MASK,
CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
chip->bbt_td = &bbt_main_descr;
chip->bbt_md = &bbt_mirror_descr;
page_sz = PAGE_2K + OOB_64;
page_sz += cfg.width == 16 ? 1 : 0;
vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
/* Set configuration register. */
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
/* Enable Idle IRQ */
vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
/* PAGE_CNT = 1 */
vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
CONFIG_PAGE_CNT_SHIFT, 1);
/* Set ECC_STATUS offset */
vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
CONFIG_ECC_SRAM_ADDR_MASK,
CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
/* first scan to find the device and get the page size */
if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
err = -ENXIO;
goto error;
}
chip->ecc.mode = NAND_ECC_SOFT; /* default */
page_sz = mtd->writesize + mtd->oobsize;
/* Single buffer only, max 256 OOB minus ECC status */
if (page_sz > PAGE_2K + 256 - 8) {
dev_err(nfc->dev, "Unsupported flash size\n");
err = -ENXIO;
goto error;
}
page_sz += cfg.width == 16 ? 1 : 0;
vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
if (cfg.hardware_ecc) {
if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
dev_err(nfc->dev, "Unsupported flash with hwecc\n");
err = -ENXIO;
goto error;
}
chip->ecc.layout = &vf610_nfc_ecc45;
/* propagate ecc.layout to mtd_info */
mtd->ecclayout = chip->ecc.layout;
chip->ecc.read_page = vf610_nfc_read_page;
chip->ecc.write_page = vf610_nfc_write_page;
chip->ecc.mode = NAND_ECC_HW;
chip->ecc.bytes = 45;
chip->ecc.size = PAGE_2K;
chip->ecc.strength = 24;
/* set ECC mode to 45 bytes OOB with 24 bits correction */
vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
CONFIG_ECC_MODE_MASK,
CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
/* Enable ECC_STATUS */
vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
}
/* second phase scan */
err = nand_scan_tail(mtd);
if (err)
return err;
err = nand_register(devnum);
if (err)
return err;
return 0;
error:
return err;
}
void board_nand_init(void)
{
int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
if (err)
printf("VF610 NAND init failed (err %d)\n", err);
}

4
drivers/usb/host/ehci-mx6.c
View File

@ -174,7 +174,7 @@ struct usbnc_regs {
static void usb_oc_config(int index)
{
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR +
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
u32 val;
@ -207,7 +207,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
enum usb_init_type type;
struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
(0x200 * index));
if (index > 3)

16
drivers/usb/host/ehci-mxs.c
View File

@ -77,6 +77,16 @@ static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
return 0;
}
int __weak board_ehci_hcd_init(int port)
{
return 0;
}
int __weak board_ehci_hcd_exit(int port)
{
return 0;
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
@ -90,6 +100,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
return -EINVAL;
}
ret = board_ehci_hcd_init(index);
if (ret)
return ret;
port = &mxs_port[index];
/* Reset the PHY block */
@ -154,5 +168,7 @@ int ehci_hcd_stop(int index)
/* Disable USB clock */
ret = ehci_mxs_toggle_clock(port, 0);
board_ehci_hcd_exit(index);
return ret;
}

1
include/configs/cm_fx6.h
View File

@ -222,7 +222,6 @@
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_NET_RETRY_COUNT 5
/* USB */

13
include/configs/m28evk.h
View File

@ -32,6 +32,7 @@
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_I2C
@ -236,7 +237,7 @@
"addargs=run addcons addmtd addmisc\0" \
"mmcload=" \
"mmc rescan ; " \
"ext4load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
"load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
"ubiload=" \
"ubi part UBI ; ubifsmount ubi0:rootfs ; " \
"ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
@ -279,10 +280,12 @@
"bootm ${kernel_addr_r}\0" \
"try_bootscript=" \
"mmc rescan;" \
"if ext4load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
"then;" \
"\techo Running bootscript...;" \
"\tsource ${kernel_addr_r};" \
"if test -e mmc 0:2 ${bootscript} ; then " \
"if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
"then ; " \
"echo Running bootscript... ; " \
"source ${kernel_addr_r} ; " \
"fi ; " \
"fi\0"
/* The rest of the configuration is shared */

13
include/configs/m53evk.h
View File

@ -38,6 +38,7 @@
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
@ -305,7 +306,7 @@
"addargs=run addcons addmtd addmisc\0" \
"mmcload=" \
"mmc rescan ; " \
"ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
"load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
"ubiload=" \
"ubi part UBI ; ubifsmount ubi0:rootfs ; " \
"ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
@ -348,10 +349,12 @@
"bootm ${kernel_addr_r}\0" \
"try_bootscript=" \
"mmc rescan;" \
"if ext4load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
"then;" \
"\techo Running bootscript...;" \
"\tsource ${kernel_addr_r};" \
"if test -e mmc 0:1 ${bootscript} ; then " \
"if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
"then ; " \
"echo Running bootscript... ; " \
"source ${kernel_addr_r} ; " \
"fi ; " \
"fi\0"
#endif /* __M53EVK_CONFIG_H__ */

3
include/configs/mx25pdk.h
View File

@ -14,6 +14,7 @@
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
@ -100,7 +101,7 @@
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* PMIC Configs */

3
include/configs/mx51evk.h
View File

@ -26,6 +26,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_OF_LIBFDT
@ -69,7 +70,7 @@
* MMC Configs
* */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
#define CONFIG_MMC

49
include/configs/mx6qarm2.h
View File

@ -10,7 +10,6 @@
#define __CONFIG_H
#define CONFIG_MX6
#define CONFIG_MX6Q
#include "mx6_common.h"
@ -37,7 +36,7 @@
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMC
@ -69,18 +68,22 @@
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x10800000
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc3\0" \
"fdt_file=imx6q-arm2.dtb\0" \
"fdt_addr=0x18000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=1\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
@ -88,15 +91,46 @@
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootz\0" \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"dhcp ${image}; bootz\0" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
@ -134,7 +168,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

2
include/configs/mx6slevk.h
View File

@ -40,7 +40,7 @@
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_MMC
#define CONFIG_CMD_MMC

6
include/configs/mx6sxsabresd.h
View File

@ -159,7 +159,7 @@
/* MMC Configuration */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
#define CONFIG_MMC
#define CONFIG_CMD_MMC
@ -204,8 +204,8 @@
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 1)
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 0)
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
#endif
/* FLASH and environment organization */

113
include/configs/nitrogen6x.h
View File

@ -32,6 +32,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
@ -63,6 +64,7 @@
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_EDID
/* MMC Configs */
#define CONFIG_FSL_ESDHC
@ -75,6 +77,8 @@
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
@ -122,6 +126,8 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
@ -137,7 +143,6 @@
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_CONSOLE_MUX
@ -173,7 +178,14 @@
#define CONFIG_DRIVE_MMC
#endif
#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
#ifdef CONFIG_USB_STORAGE
#define CONFIG_DRIVE_USB "usb "
#else
#define CONFIG_DRIVE_USB
#endif
#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB
#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
#if defined(CONFIG_SABRELITE)
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -186,7 +198,7 @@
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcdevs=0 1\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
@ -238,47 +250,71 @@
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
"for mmcdev in ${mmcdevs}; do " \
"mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"fi; " \
"fi; " \
"fi; " \
"done; " \
"run netboot; "
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootdevs=" CONFIG_DRIVE_TYPES "\0" \
"umsdevs=" CONFIG_UMSDEVS "\0" \
"console=ttymxc1\0" \
"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
"sf erase 0xc0000 0x2000 && " \
"echo restored environment to factory default ; fi\0" \
"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
"bootcmd=for dtype in ${bootdevs}" \
"; do " \
"if itest.s \"xusb\" == \"x${dtype}\" ; then " \
"usb start ;" \
"fi; " \
"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
"for fs in fat ext2 ; do " \
"${fs}load " \
"${dtype} ${disk}:1 " \
"10008000 " \
"/6x_bootscript" \
"&& source 10008000 ; " \
"done ; " \
"load " \
"${dtype} ${disk}:1 " \
"10008000 " \
"/6x_bootscript" \
"&& source 10008000 ; " \
"done ; " \
"done; " \
"setenv stdout serial,vga ; " \
"echo ; echo 6x_bootscript not found ; " \
"echo ; echo serial console at 115200, 8N1 ; echo ; " \
"echo details at http://boundarydevices.com/6q_bootscript ; " \
"setenv stdout serial\0" \
"upgradeu=for dtype in " CONFIG_DRIVE_TYPES \
"setenv stdout serial;" \
"setenv stdin serial,usbkbd;" \
"for dtype in ${umsdevs} ; do " \
"if itest.s sata == ${dtype}; then " \
"initcmd='sata init' ;" \
"else " \
"initcmd='mmc rescan' ;" \
"fi; " \
"for disk in 0 1 ; do " \
"if $initcmd && $dtype dev $disk ; then " \
"setenv stdout serial,vga; " \
"echo expose ${dtype} ${disk} " \
"over USB; " \
"ums 0 $dtype $disk ;" \
"fi; " \
" done; " \
"done ;" \
"setenv stdout serial,vga; " \
"echo no block devices found;" \
"\0" \
"initrd_high=0xffffffff\0" \
"upgradeu=for dtype in ${bootdevs}" \
"; do " \
"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
"for fs in fat ext2 ; do " \
"${fs}load ${dtype} ${disk}:1 10008000 " \
"/6x_upgrade " \
"&& source 10008000 ; " \
"done ; " \
"load ${dtype} ${disk}:1 10008000 " \
"/6x_upgrade " \
"&& source 10008000 ; " \
"done ; " \
"done\0" \
@ -292,7 +328,7 @@
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MAXARGS 48
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x10000000
@ -349,6 +385,7 @@
#define CONFIG_CMD_BMP
#define CONFIG_CMD_TIME
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_CMD_BOOTZ
@ -365,4 +402,22 @@
#define CONFIG_PCIE_IMX
#endif
#define CONFIG_CMD_ELF
#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* Netchip IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "Boundary"
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
#endif /* __CONFIG_H */

197
include/configs/ot1200.h Normal file
View File

@ -0,0 +1,197 @@
/*
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
* Copyright (C) 2014 Bachmann electronic GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_GENERIC_BOARD
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
/* FUSE Configs */
#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
/* UART Configs */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SF Configs */
#define CONFIG_CMD_SF
#define CONFIG_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8))
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
/* IO expander */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
/* OCOTP Configs */
#define CONFIG_CMD_IMXOTP
#define CONFIG_IMX_OTP
#define IMX_OTP_BASE OCOTP_BASE_ADDR
#define IMX_OTP_ADDR_MAX 0x7F
#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
#define IMX_OTPWRITE_ENABLED
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#ifdef CONFIG_MX6Q
#define CONFIG_CMD_SATA
#endif
/*
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
#endif
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x5
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 2
#define CONFIG_PREBOOT ""
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_CBSIZE 1024
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
#define CONFIG_ENV_OFFSET (1024 * 1024)
/* M25P16 has an erase size of 64 KiB */
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD
/* FS Configs */
#define CONFIG_CMD_EXT3
#define CONFIG_CMD_EXT4
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTFILE
#endif /* __CONFIG_H */

46
include/configs/vf610twr.h
View File

@ -14,6 +14,7 @@
#define CONFIG_VF610
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@ -44,6 +45,41 @@
#undef CONFIG_CMD_IMLS
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_VF610_NFC
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
/* UBI */
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=fsl_nfc"
#define MTDPARTS_DEFAULT "mtdparts=fsl_nfc:" \
"128k(vf-bcb)ro," \
"1408k(u-boot)ro," \
"512k(u-boot-env)," \
"4m(kernel)," \
"512k(fdt)," \
"-(rootfs)"
#endif
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@ -218,11 +254,19 @@
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE (64 * 2048)
#define CONFIG_ENV_SECT_SIZE (64 * 2048)
#define CONFIG_ENV_RANGE (512 * 1024)
#define CONFIG_ENV_OFFSET 0x180000
#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ

5
include/configs/wandboard.h
View File

@ -110,6 +110,11 @@
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
#elif defined(CONFIG_MX6Q)