Add support for ECC DDR initialization on MPC83xx.
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61f25155ac
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@ -2,6 +2,8 @@
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Changes since U-Boot 1.1.4:
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Changes since U-Boot 1.1.4:
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======================================================================
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======================================================================
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* Add support for ECC DDR initialization on MPC83xx.
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* Add DMA support for MPC83xx.
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* Add DMA support for MPC83xx.
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* Add sync in do_reset() routine for MPC83xx after RPR register
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* Add sync in do_reset() routine for MPC83xx after RPR register
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@ -63,12 +63,16 @@ picos_to_clk(int picos)
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return clks;
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return clks;
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}
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}
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unsigned int
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unsigned int banksize(unsigned char row_dens)
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banksize(unsigned char row_dens)
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{
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{
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return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
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return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
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}
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}
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int read_spd(uint addr)
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{
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return ((int) addr);
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}
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long int spd_sdram(int(read_spd)(uint addr))
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long int spd_sdram(int(read_spd)(uint addr))
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{
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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@ -282,8 +286,13 @@ long int spd_sdram(int(read_spd)(uint addr))
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*/
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*/
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#if defined(CONFIG_DDR_ECC)
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#if defined(CONFIG_DDR_ECC)
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if (spd.config == 0x02) {
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if (spd.config == 0x02) {
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ddr->err_disable = 0x0000000d;
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/* disable error detection */
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ddr->err_sbe = 0x00ff0000;
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ddr->err_disable = ~ECC_ERROR_ENABLE;
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/* set single bit error threshold to maximum value,
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* reset counter to zero */
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ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
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(0 << ECC_ERROR_MAN_SBEC_SHIFT);
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}
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}
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debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
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debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
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debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
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debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
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@ -297,7 +306,8 @@ long int spd_sdram(int(read_spd)(uint addr))
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* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
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* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
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* clock cycle after address/command
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* clock cycle after address/command
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*/
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*/
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ddr->sdram_clk_cntl = 0x82000000;
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/*ddr->sdram_clk_cntl = 0x82000000;*/
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ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
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/*
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/*
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* Figure out the settings for the sdram_cfg register. Build up
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* Figure out the settings for the sdram_cfg register. Build up
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@ -324,7 +334,7 @@ long int spd_sdram(int(read_spd)(uint addr))
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* If the user wanted ECC (enabled via sdram_cfg[2])
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* If the user wanted ECC (enabled via sdram_cfg[2])
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*/
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*/
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if (spd.config == 0x02) {
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if (spd.config == 0x02) {
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tmp |= 0x20000000;
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tmp |= SDRAM_CFG_ECC_EN;
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}
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}
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#endif
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#endif
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@ -347,30 +357,88 @@ long int spd_sdram(int(read_spd)(uint addr))
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#if defined(CONFIG_DDR_ECC)
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#if defined(CONFIG_DDR_ECC)
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/*
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* Use timebase counter, get_timer() is not availabe
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* at this point of initialization yet.
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*/
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static __inline__ unsigned long get_tbms (void)
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{
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unsigned long tbl;
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unsigned long tbu1, tbu2;
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unsigned long ms;
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unsigned long long tmp;
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ulong tbclk = get_tbclk();
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/* get the timebase ticks */
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do {
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asm volatile ("mftbu %0":"=r" (tbu1):);
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asm volatile ("mftb %0":"=r" (tbl):);
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asm volatile ("mftbu %0":"=r" (tbu2):);
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} while (tbu1 != tbu2);
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/* convert ticks to ms */
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tmp = (unsigned long long)(tbu1);
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tmp = (tmp << 32);
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tmp += (unsigned long long)(tbl);
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ms = tmp/(tbclk/1000);
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return ms;
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}
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/*
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/*
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* Initialize all of memory for ECC, then enable errors.
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* Initialize all of memory for ECC, then enable errors.
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*/
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*/
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//#define CONFIG_DDR_ECC_INIT_VIA_DMA
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void
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void ddr_enable_ecc(unsigned int dram_size)
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ddr_enable_ecc(unsigned int dram_size)
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{
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{
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#ifndef FIXME
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uint *p;
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uint *p = 0;
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uint i = 0;
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile ccsr_ddr_t *ddr= &immap->im_ddr;
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volatile ddr8349_t *ddr = &immap->ddr;
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unsigned long t_start, t_end;
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#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
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uint i;
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#endif
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debug("Initialize a Cachline in DRAM\n");
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icache_enable();
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#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
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/* Initialise DMA for direct Transfers */
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dma_init();
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dma_init();
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#endif
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for (*p = 0; p < (uint *)(8 * 1024); p++) {
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t_start = get_tbms();
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#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
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debug("DDR init: Cache flush method\n");
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for (p = 0; p < (uint *)(dram_size); p++) {
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if (((unsigned int)p & 0x1f) == 0) {
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if (((unsigned int)p & 0x1f) == 0) {
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ppcDcbz((unsigned long) p);
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ppcDcbz((unsigned long) p);
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}
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}
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/* write pattern to cache and flush */
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*p = (unsigned int)0xdeadbeef;
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*p = (unsigned int)0xdeadbeef;
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if (((unsigned int)p & 0x1c) == 0x1c) {
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if (((unsigned int)p & 0x1c) == 0x1c) {
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ppcDcbf((unsigned long) p);
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ppcDcbf((unsigned long) p);
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}
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}
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}
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}
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#else
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printf("DDR init: DMA method\n");
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for (p = 0; p < (uint *)(8 * 1024); p++) {
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/* zero one data cache line */
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if (((unsigned int)p & 0x1f) == 0) {
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ppcDcbz((unsigned long)p);
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}
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/* write pattern to it and flush */
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*p = (unsigned int)0xdeadbeef;
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if (((unsigned int)p & 0x1c) == 0x1c) {
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ppcDcbf((unsigned long)p);
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}
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}
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/* 8K */
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/* 8K */
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dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
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dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
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@ -396,13 +464,31 @@ ddr_enable_ecc(unsigned int dram_size)
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for (i = 1; i < dram_size / 0x800000; i++) {
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for (i = 1; i < dram_size / 0x800000; i++) {
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dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
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dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
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}
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}
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/*
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* Enable errors for ECC.
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*/
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ddr->err_disable = 0x00000000;
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asm("sync;isync");
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#endif
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#endif
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}
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t_end = get_tbms();
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icache_disable();
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debug("\nREADY!!\n");
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debug("ddr init duration: %ld ms\n", t_end - t_start);
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/* Clear All ECC Errors */
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if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
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ddr->err_detect |= ECC_ERROR_DETECT_MME;
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if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
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ddr->err_detect |= ECC_ERROR_DETECT_MBE;
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if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
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ddr->err_detect |= ECC_ERROR_DETECT_SBE;
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if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
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ddr->err_detect |= ECC_ERROR_DETECT_MSE;
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/* Disable ECC-Interrupts */
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ddr->err_int_en &= ECC_ERR_INT_DISABLE;
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/* Enable errors for ECC */
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ddr->err_disable &= ECC_ERROR_ENABLE;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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}
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#endif /* CONFIG_DDR_ECC */
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#endif /* CONFIG_DDR_ECC */
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