* Enable NAND flash support for NC650 board.
* Patch by Thomas Lange 07 Oct 2004: Updated README for DBAu1x00 boards to match current status
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Changes since U-Boot 1.1.1:
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Changes since U-Boot 1.1.1:
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======================================================================
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======================================================================
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* Enable NAND flash support for NC650 board.
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* Patch by Thomas Lange 07 Oct 2004:
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Updated README for DBAu1x00 boards to match current status
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* Patch by Philippe Robin, 28 Sept 2004:
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* Patch by Philippe Robin, 28 Sept 2004:
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Fix Flash support for Versatile.
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Fix Flash support for Versatile.
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@ -1,30 +1,40 @@
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By Thomas.Lange@corelatus.se 2003-10-06
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By Thomas.Lange@corelatus.se 2004-Oct-05
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----------------------------------------
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----------------------------------------
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DbAu1000 is a development board from AMD containing
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DbAu1xx0 are development boards from AMD containing
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an Alchemy AU1000 with mips32 core.
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an Alchemy AU1xx0 series cpu with mips32 core.
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Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
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Limitations & comments
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Limitations & comments
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----------------------
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----------------------
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I assume that you set board to BIG endian!
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Support was originally big endian only.
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Little endian not tested, most probably broken.
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I have not tested, but several u-boot users report working
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configurations in little endian mode.
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I named the board dbau1x00, to allow
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I named the board dbau1x00, to allow
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support for all three development boards
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support for all three development boards
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some day ( dbau1000, dbau1100 and dbau1500 ).
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( dbau1000, dbau1100 and dbau1500 ).
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Now there is a new board called dbau1550 also, which
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should be supported RSN.
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I only have a dbau1000, so all testing is limited
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I only have a dbau1000, so my testing is limited
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to this board!
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to this board.
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The board has two different flash banks, that can
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The board has two different flash banks, that can
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be selected via dip switch. This makes it possible
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be selected via dip switch. This makes it possible
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to test new bootloaders without thrashing the YAMON
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to test new bootloaders without thrashing the YAMON
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boot loader deliviered with board.
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boot loader delivered with board.
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NOTE! When you switch between the two boot flashes, the
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base addresses will be swapped.
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Have this in mind when you compile u-boot. TEXT_BASE has
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to match the address where u-boot is located when you
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actually launch.
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Ethernet only supported for mac0.
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Ethernet only supported for mac0.
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Pcmcia only supported for slot 0, only 3.3V.
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PCMCIA only supported for slot 0, only 3.3V.
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Pcmcia IDE tested with Sandisk Compact Flash and
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PCMCIA IDE tested with Sandisk Compact Flash and
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IBM microdrive.
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IBM microdrive.
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###################################
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###################################
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@ -32,7 +42,7 @@ IBM microdrive.
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###################################
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###################################
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If you partition a disk on another system (e.g. laptop),
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If you partition a disk on another system (e.g. laptop),
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all bytes will be swapped on 16bit level when using
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all bytes will be swapped on 16bit level when using
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PCMCIA!!!!
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PCMCIA and running cpu in big endian mode!!!!
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This is probably due to an error in Au1000 chip.
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This is probably due to an error in Au1000 chip.
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@ -205,3 +205,13 @@ static long int dram_size (long int mamr_value, long int *base,
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return (get_ram_size(base, maxsize));
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return (get_ram_size(base, maxsize));
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}
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}
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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void nand_init(void)
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{
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unsigned long totlen = nand_probe(CFG_NAND_BASE);
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printf ("%4lu MB\n", totlen >> 20);
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}
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#endif
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@ -96,8 +96,8 @@
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/*
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/*
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* Software (bit-bang) I2C driver configuration
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* Software (bit-bang) I2C driver configuration
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*/
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*/
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#define SCL 0x10000000 /* PA 3 */
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#define SCL 0x1000 /* PA 3 */
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#define SDA 0x40000000 /* PA 1 */
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#define SDA 0x2000 /* PA 2 */
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#define PAR immr->im_ioport.iop_papar
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#define PAR immr->im_ioport.iop_papar
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#define DIR immr->im_ioport.iop_padir
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#define DIR immr->im_ioport.iop_padir
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@ -111,19 +111,16 @@
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else DAT &= ~SDA
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else DAT &= ~SDA
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#define I2C_SCL(bit) if (bit) DAT |= SCL; \
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#define I2C_SCL(bit) if (bit) DAT |= SCL; \
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else DAT &= ~SCL
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else DAT &= ~SCL
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#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CONFIG_RTC_PCF8563
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_I2C_RTC_ADDR 0x51
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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CFG_CMD_DHCP | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C | \
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CFG_CMD_I2C | \
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CFG_CMD_NAND | \
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CFG_CMD_DATE )
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CFG_CMD_DATE )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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#endif
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/*
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* NAND flash support
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*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_ChipID_UNKNOWN 0x00
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#define SECTORSIZE 512
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define ADDR_COLUMN 1
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#define NAND_NO_RB
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#define NAND_WAIT_READY(nand) udelay(12)
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#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2)
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#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1)
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#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d))
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#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
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#define NAND_DISABLE_CE(nand) /* nop */
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#define NAND_ENABLE_CE(nand) /* nop */
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#define NAND_CTL_CLRALE(nandptr) /* nop */
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#define NAND_CTL_SETALE(nandptr) /* nop */
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#define NAND_CTL_CLRCLE(nandptr) /* nop */
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#define NAND_CTL_SETCLE(nandptr) /* nop */
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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* SYPCR can only be written once after reset!
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
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/*
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* BR2 and OR2 (NAND Flash)
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*/
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#define CFG_NAND_BASE 0x50000000
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#define CFG_NAND_SIZE 0x04000000
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#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
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OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
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#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_NAND)
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/*
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/*
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* BR3 and OR3 (SDRAM)
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* BR3 and OR3 (SDRAM)
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*/
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*/
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