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ARM: k2g: Update PLL Multiplier and divider values 

Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18

[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla 2016-11-03 15:35:02 +05:30 committed by Tom Rini
parent 8b01ebd812
commit 4d0fec0e69
1 changed files with 1 additions and 1 deletions
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2
board/ti/ks2_evm/board_k2g.c
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@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
struct pll_init_data *get_pll_init_data(int pll)
{