sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

Coding style cleanup

This commit is contained in:
Wolfgang Denk 2006-10-09 00:42:01 +02:00
parent 8d4ac79436
commit 511d0c72b8
28 changed files with 79 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CHANGELOG
View File

@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* Coding style cleanup
* Add support for EP82xxM boards * Add support for EP82xxM boards
Patch by Aaron Sells, 20 Jun 2006 Patch by Aaron Sells, 20 Jun 2006

72
board/amcc/sequoia/sequoia.c
View File

@ -4,7 +4,7 @@
* *
* (C) Copyright 2006 * (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
@ -123,12 +123,12 @@ int board_early_init_f(void)
/* setup NAND FLASH */ /* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0); mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_NDFC_ARE_MASK |
(0x80000000 >> (28 + CFG_NAND_CS)); (0x80000000 >> (28 + CFG_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0); mtsdr(SDR0_CUST0, sdr0_cust0);
return 0; return 0;
} }
@ -216,38 +216,38 @@ int misc_init_r(void)
#ifdef CONFIG_440EPX #ifdef CONFIG_440EPX
if (act == NULL || strcmp(act, "hostdev") == 0) { if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */ /* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/* An 8-bit/60MHz interface is the only possible alternative /* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */ when connecting the Device to the PHY */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
/* To enable the USB 2.0 Device function through the UTMI interface */ /* To enable the USB 2.0 Device function through the UTMI interface */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr);
/*clear resets*/ /*clear resets*/
udelay (1000); udelay (1000);
@ -264,11 +264,11 @@ int misc_init_r(void)
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay (1000); udelay (1000);
@ -287,33 +287,33 @@ int misc_init_r(void)
/*-------------------PATCH-------------------------------*/ /*-------------------PATCH-------------------------------*/
/* SDR Setting */ /* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr);
mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
mtsdr(SDR0_USB2H0CR, usb2h0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_PFC1, sdr0_pfc1);

3
board/amcc/yucca/yucca.c
View File

@ -958,7 +958,6 @@ int is_pci_host(struct pci_controller *hose)
return 1; return 1;
} }
int yucca_pcie_card_present(int port) int yucca_pcie_card_present(int port)
{ {
u16 reg; u16 reg;
@ -1084,8 +1083,6 @@ void yucca_setup_pcie_fpga_endpoint(int port)
(endpoint | in_be16((u16 *)FPGA_REG1C))); (endpoint | in_be16((u16 *)FPGA_REG1C)));
} }
static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void) void pcie_setup_hoses(void)

24
cpu/ppc4xx/ndfc.c
View File

@ -65,8 +65,8 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W; ulong base = (ulong) this->IO_ADDR_W;
if (hwctl & 0x1) if (hwctl & 0x1)
out8(base + NDFC_CMD, byte); out8(base + NDFC_CMD, byte);
@ -78,16 +78,16 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
static u_char ndfc_read_byte(struct mtd_info *mtdinfo) static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W; ulong base = (ulong) this->IO_ADDR_W;
return (in8(base + NDFC_DATA)); return (in8(base + NDFC_DATA));
} }
static int ndfc_dev_ready(struct mtd_info *mtdinfo) static int ndfc_dev_ready(struct mtd_info *mtdinfo)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W; ulong base = (ulong) this->IO_ADDR_W;
while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
; ;
@ -110,8 +110,8 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
*/ */
static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W; ulong base = (ulong) this->IO_ADDR_W;
uint32_t *p = (uint32_t *) buf; uint32_t *p = (uint32_t *) buf;
for(;len > 0; len -= 4) for(;len > 0; len -= 4)
@ -120,8 +120,8 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W; ulong base = (ulong) this->IO_ADDR_W;
uint32_t *p = (uint32_t *) buf; uint32_t *p = (uint32_t *) buf;
for(; len > 0; len -= 4) for(; len > 0; len -= 4)
@ -130,8 +130,8 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{ {
struct nand_chip *this = mtdinfo->priv; struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W; ulong base = (ulong) this->IO_ADDR_W;
uint32_t *p = (uint32_t *) buf; uint32_t *p = (uint32_t *) buf;
for(; len > 0; len -= 4) for(; len > 0; len -= 4)

6
cpu/ppc4xx/start.S
View File

@ -173,9 +173,9 @@
/**************************************************************************/ /**************************************************************************/
_start_440: _start_440:
/*--------------------------------------------------------------------+ /*--------------------------------------------------------------------+
| 440EPX BUP Change - Hardware team request | 440EPX BUP Change - Hardware team request
+--------------------------------------------------------------------*/ +--------------------------------------------------------------------*/
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
sync sync
nop nop

1
drivers/sk98lin/Makefile
View File

@ -104,4 +104,3 @@ include $(SRCTREE)/rules.mk
sinclude $(obj).depend sinclude $(obj).depend
######################################################################### #########################################################################

2
include/common.h
View File

@ -110,7 +110,7 @@ typedef volatile unsigned char vu_char;
#endif /* DEBUG */ #endif /* DEBUG */
#define BUG() do { \ #define BUG() do { \
printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
panic("BUG!"); \ panic("BUG!"); \
} while (0) } while (0)
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)

4
nand_spl/nand_boot.c
View File

@ -34,7 +34,7 @@ extern int jump_to_uboot(ulong addr);
static int nand_is_bad_block(struct mtd_info *mtd, int block) static int nand_is_bad_block(struct mtd_info *mtd, int block)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
int page_addr = block * CFG_NAND_PAGE_COUNT; int page_addr = block * CFG_NAND_PAGE_COUNT;
/* Begin command latch cycle */ /* Begin command latch cycle */
@ -73,7 +73,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{ {
struct nand_chip *this = mtd->priv; struct nand_chip *this = mtd->priv;
int page_addr = page + block * CFG_NAND_PAGE_COUNT; int page_addr = page + block * CFG_NAND_PAGE_COUNT;
int i; int i;