nand: Freescale Integrated Flash Controller NAND support
Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
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49249e137d
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52f90dad60
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@ -21,10 +21,12 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <asm/fsl_ifc.h>
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#include <asm/io.h>
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#include <asm/io.h>
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void cpu_init_f(void)
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void cpu_init_f(void)
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{
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{
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#ifdef CONFIG_FSL_LBC
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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/*
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/*
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@ -39,6 +41,14 @@ void cpu_init_f(void)
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#else
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#else
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#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
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#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
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#endif
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#endif
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#endif
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#ifdef CONFIG_FSL_IFC
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#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
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set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
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set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
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set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
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#endif
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#endif
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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@ -23,6 +23,8 @@
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* MA 02111-1307 USA
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* MA 02111-1307 USA
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*/
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*/
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#include "config.h" /* CONFIG_BOARDDIR */
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OUTPUT_ARCH(powerpc)
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OUTPUT_ARCH(powerpc)
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SECTIONS
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SECTIONS
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{
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{
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@ -52,8 +54,18 @@ SECTIONS
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. = ALIGN(8);
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. = ALIGN(8);
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__init_begin = .;
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__init_begin = .;
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__init_end = .;
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__init_end = .;
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#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
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.resetvec ADDR(.text) + 0xffc : {
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.bootpg ADDR(.text) + 0x1000 :
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{
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start.o (.bootpg)
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}
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#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
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#elif defined(CONFIG_FSL_ELBC)
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#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
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#else
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#error unknown NAND controller
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#endif
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.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
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KEEP(*(.resetvec))
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KEEP(*(.resetvec))
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} = 0xffff
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} = 0xffff
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@ -64,4 +76,4 @@ SECTIONS
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}
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}
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__bss_end__ = .;
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__bss_end__ = .;
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}
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}
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ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
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ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");
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@ -69,6 +69,7 @@
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*/
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*/
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/* Enable ECC Encoder */
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/* Enable ECC Encoder */
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#define CSOR_NAND_ECC_ENC_EN 0x80000000
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#define CSOR_NAND_ECC_ENC_EN 0x80000000
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#define CSOR_NAND_ECC_MODE_MASK 0x30000000
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/* 4 bit correction per 520 Byte sector */
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/* 4 bit correction per 520 Byte sector */
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#define CSOR_NAND_ECC_MODE_4 0x00000000
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#define CSOR_NAND_ECC_MODE_4 0x00000000
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/* 8 bit correction per 528 Byte sector */
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/* 8 bit correction per 528 Byte sector */
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@ -857,10 +858,7 @@ struct fsl_ifc_nand {
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u32 res19[0x10];
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u32 res19[0x10];
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u32 nand_fsr;
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u32 nand_fsr;
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u32 res20;
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u32 res20;
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u32 nand_eccstat0;
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u32 nand_eccstat[4];
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u32 nand_eccstat1;
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u32 nand_eccstat2;
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u32 nand_eccstat3;
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u32 res21[0x20];
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u32 res21[0x20];
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u32 nanndcr;
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u32 nanndcr;
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u32 res22[0x2];
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u32 res22[0x2];
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@ -37,6 +37,7 @@ COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
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COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
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COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
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COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
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COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
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COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
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COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
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COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
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COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
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COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
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COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
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COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
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COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
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COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
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@ -0,0 +1,850 @@
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/* Integrated Flash Controller NAND Machine Driver
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*
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* Copyright (c) 2011 Freescale Semiconductor, Inc
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*
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* Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/fsl_ifc.h>
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#define MAX_BANKS 4
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#define ERR_BYTE 0xFF /* Value returned for read bytes
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when read failed */
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#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
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NAND Machine */
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struct fsl_ifc_ctrl;
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/* mtd information per set */
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struct fsl_ifc_mtd {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct fsl_ifc_ctrl *ctrl;
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struct device *dev;
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int bank; /* Chip select bank number */
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unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
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u8 __iomem *vbase; /* Chip select base virtual address */
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};
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/* overview of the fsl ifc controller */
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struct fsl_ifc_ctrl {
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struct nand_hw_control controller;
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struct fsl_ifc_mtd *chips[MAX_BANKS];
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/* device info */
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struct fsl_ifc *regs;
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uint8_t __iomem *addr; /* Address of assigned IFC buffer */
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unsigned int cs_nand; /* On which chipsel NAND is connected */
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unsigned int page; /* Last page written to / read from */
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unsigned int read_bytes; /* Number of bytes read during command */
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unsigned int column; /* Saved column from SEQIN */
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unsigned int index; /* Pointer to next byte to 'read' */
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unsigned int status; /* status read from NEESR after last op */
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unsigned int oob; /* Non zero if operating on OOB data */
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unsigned int eccread; /* Non zero for a full-page ECC read */
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};
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static struct fsl_ifc_ctrl *ifc_ctrl;
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/* 512-byte page with 4-bit ECC, 8-bit */
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static struct nand_ecclayout oob_512_8bit_ecc4 = {
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.eccbytes = 8,
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.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
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.oobfree = { {0, 5}, {6, 2} },
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};
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/* 512-byte page with 4-bit ECC, 16-bit */
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static struct nand_ecclayout oob_512_16bit_ecc4 = {
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.eccbytes = 8,
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.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
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.oobfree = { {2, 6}, },
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};
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/* 2048-byte page size with 4-bit ECC */
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static struct nand_ecclayout oob_2048_ecc4 = {
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.eccbytes = 32,
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.eccpos = {
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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},
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.oobfree = { {2, 6}, {40, 24} },
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};
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/* 4096-byte page size with 4-bit ECC */
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static struct nand_ecclayout oob_4096_ecc4 = {
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.eccbytes = 64,
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.eccpos = {
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71,
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},
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.oobfree = { {2, 6}, {72, 56} },
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};
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/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
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static struct nand_ecclayout oob_4096_ecc8 = {
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.eccbytes = 128,
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.eccpos = {
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71,
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72, 73, 74, 75, 76, 77, 78, 79,
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80, 81, 82, 83, 84, 85, 86, 87,
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88, 89, 90, 91, 92, 93, 94, 95,
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96, 97, 98, 99, 100, 101, 102, 103,
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104, 105, 106, 107, 108, 109, 110, 111,
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112, 113, 114, 115, 116, 117, 118, 119,
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120, 121, 122, 123, 124, 125, 126, 127,
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128, 129, 130, 131, 132, 133, 134, 135,
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},
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.oobfree = { {2, 6}, {136, 82} },
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};
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/*
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* Generic flash bbt descriptors
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*/
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 2, /* 0 on 8-bit small page */
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.len = 4,
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.veroffs = 6,
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.maxblocks = 4,
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.pattern = bbt_pattern,
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 2, /* 0 on 8-bit small page */
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.len = 4,
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.veroffs = 6,
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.maxblocks = 4,
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.pattern = mirror_pattern,
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};
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/*
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* Set up the IFC hardware block and page address fields, and the ifc nand
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* structure addr field to point to the correct IFC buffer in memory
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*/
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static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc *ifc = ctrl->regs;
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int buf_num;
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ctrl->page = page_addr;
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/* Program ROW0/COL0 */
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out_be32(&ifc->ifc_nand.row0, page_addr);
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out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
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buf_num = page_addr & priv->bufnum_mask;
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ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
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ctrl->index = column;
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/* for OOB data point to the second half of the buffer */
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if (oob)
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ctrl->index += mtd->writesize;
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}
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static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
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unsigned int bufnum)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
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u32 __iomem *main = (u32 *)addr;
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u8 __iomem *oob = addr + mtd->writesize;
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int i;
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for (i = 0; i < mtd->writesize / 4; i++) {
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if (__raw_readl(&main[i]) != 0xffffffff)
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return 0;
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}
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for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
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int pos = chip->ecc.layout->eccpos[i];
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if (__raw_readb(&oob[pos]) != 0xff)
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return 0;
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}
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return 1;
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}
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/* returns nonzero if entire page is blank */
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static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
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u32 *eccstat, unsigned int bufnum)
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{
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u32 reg = eccstat[bufnum / 4];
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int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
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if (errors == 15) { /* uncorrectable */
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/* Blank pages fail hw ECC checks */
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||||||
|
if (is_blank(mtd, ctrl, bufnum))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We disable ECCER reporting in hardware due to
|
||||||
|
* erratum IFC-A002770 -- so report it now if we
|
||||||
|
* see an uncorrectable error in ECCSTAT.
|
||||||
|
*/
|
||||||
|
ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
|
||||||
|
} else if (errors > 0) {
|
||||||
|
mtd->ecc_stats.corrected += errors;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* execute IFC NAND command and wait for it to complete
|
||||||
|
*/
|
||||||
|
static int fsl_ifc_run_command(struct mtd_info *mtd)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
struct fsl_ifc *ifc = ctrl->regs;
|
||||||
|
long long end_tick;
|
||||||
|
u32 eccstat[4];
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* set the chip select for NAND Transaction */
|
||||||
|
out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
|
||||||
|
|
||||||
|
/* start read/write seq */
|
||||||
|
out_be32(&ifc->ifc_nand.nandseq_strt,
|
||||||
|
IFC_NAND_SEQ_STRT_FIR_STRT);
|
||||||
|
|
||||||
|
/* wait for NAND Machine complete flag or timeout */
|
||||||
|
end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
|
||||||
|
|
||||||
|
while (end_tick > get_ticks()) {
|
||||||
|
ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
|
||||||
|
|
||||||
|
if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
|
||||||
|
|
||||||
|
if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
|
||||||
|
printf("%s: Flash Time Out Error\n", __func__);
|
||||||
|
if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
|
||||||
|
printf("%s: Write Protect Error\n", __func__);
|
||||||
|
|
||||||
|
if (ctrl->eccread) {
|
||||||
|
int bufperpage = mtd->writesize / 512;
|
||||||
|
int bufnum = (ctrl->page & priv->bufnum_mask) * bufperpage;
|
||||||
|
int bufnum_end = bufnum + bufperpage - 1;
|
||||||
|
|
||||||
|
for (i = bufnum / 4; i <= bufnum_end / 4; i++)
|
||||||
|
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
|
||||||
|
|
||||||
|
for (i = bufnum; i <= bufnum_end; i++) {
|
||||||
|
if (check_read_ecc(mtd, ctrl, eccstat, i))
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
ctrl->eccread = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* returns 0 on success otherwise non-zero) */
|
||||||
|
return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_ifc_do_read(struct nand_chip *chip,
|
||||||
|
int oob,
|
||||||
|
struct mtd_info *mtd)
|
||||||
|
{
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
struct fsl_ifc *ifc = ctrl->regs;
|
||||||
|
|
||||||
|
/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
|
||||||
|
if (mtd->writesize > 512) {
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
|
||||||
|
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
|
||||||
|
} else {
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
|
||||||
|
|
||||||
|
if (oob)
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
else
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* cmdfunc send commands to the IFC NAND Machine */
|
||||||
|
static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
|
||||||
|
int column, int page_addr)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
struct fsl_ifc *ifc = ctrl->regs;
|
||||||
|
|
||||||
|
/* clear the read buffer */
|
||||||
|
ctrl->read_bytes = 0;
|
||||||
|
if (command != NAND_CMD_PAGEPROG)
|
||||||
|
ctrl->index = 0;
|
||||||
|
|
||||||
|
switch (command) {
|
||||||
|
/* READ0 read the entire buffer to use hardware ECC. */
|
||||||
|
case NAND_CMD_READ0: {
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
||||||
|
set_addr(mtd, 0, page_addr, 0);
|
||||||
|
|
||||||
|
ctrl->read_bytes = mtd->writesize + mtd->oobsize;
|
||||||
|
ctrl->index += column;
|
||||||
|
|
||||||
|
if (chip->ecc.mode == NAND_ECC_HW)
|
||||||
|
ctrl->eccread = 1;
|
||||||
|
|
||||||
|
fsl_ifc_do_read(chip, 0, mtd);
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* READOOB reads only the OOB because no ECC is performed. */
|
||||||
|
case NAND_CMD_READOOB:
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
|
||||||
|
set_addr(mtd, column, page_addr, 1);
|
||||||
|
|
||||||
|
ctrl->read_bytes = mtd->writesize + mtd->oobsize;
|
||||||
|
|
||||||
|
fsl_ifc_do_read(chip, 1, mtd);
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* READID must read all possible bytes while CEB is active */
|
||||||
|
case NAND_CMD_READID:
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
/* 4 bytes for manuf, device and exts */
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 4);
|
||||||
|
ctrl->read_bytes = 4;
|
||||||
|
|
||||||
|
set_addr(mtd, 0, 0, 0);
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* ERASE1 stores the block and page address */
|
||||||
|
case NAND_CMD_ERASE1:
|
||||||
|
set_addr(mtd, 0, page_addr, 0);
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* ERASE2 uses the block and page address from ERASE1 */
|
||||||
|
case NAND_CMD_ERASE2:
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
(NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
|
||||||
|
(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
||||||
|
ctrl->read_bytes = 0;
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* SEQIN sets up the addr buffer and all registers except the length */
|
||||||
|
case NAND_CMD_SEQIN: {
|
||||||
|
u32 nand_fcr0;
|
||||||
|
ctrl->column = column;
|
||||||
|
ctrl->oob = 0;
|
||||||
|
|
||||||
|
if (mtd->writesize > 512) {
|
||||||
|
nand_fcr0 =
|
||||||
|
(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
|
||||||
|
(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||||
|
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir1, 0);
|
||||||
|
} else {
|
||||||
|
nand_fcr0 = ((NAND_CMD_PAGEPROG <<
|
||||||
|
IFC_NAND_FCR0_CMD1_SHIFT) |
|
||||||
|
(NAND_CMD_SEQIN <<
|
||||||
|
IFC_NAND_FCR0_CMD2_SHIFT));
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
|
||||||
|
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir1,
|
||||||
|
(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
|
||||||
|
|
||||||
|
if (column >= mtd->writesize) {
|
||||||
|
/* OOB area --> READOOB */
|
||||||
|
column -= mtd->writesize;
|
||||||
|
nand_fcr0 |= NAND_CMD_READOOB <<
|
||||||
|
IFC_NAND_FCR0_CMD0_SHIFT;
|
||||||
|
ctrl->oob = 1;
|
||||||
|
} else if (column < 256) {
|
||||||
|
/* First 256 bytes --> READ0 */
|
||||||
|
nand_fcr0 |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
|
||||||
|
} else {
|
||||||
|
/* Second 256 bytes --> READ1 */
|
||||||
|
nand_fcr0 |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
|
||||||
|
set_addr(mtd, column, page_addr, ctrl->oob);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
|
||||||
|
case NAND_CMD_PAGEPROG:
|
||||||
|
if (ctrl->oob)
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, ctrl->index);
|
||||||
|
else
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
||||||
|
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
return;
|
||||||
|
|
||||||
|
case NAND_CMD_STATUS:
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 1);
|
||||||
|
set_addr(mtd, 0, 0, 0);
|
||||||
|
ctrl->read_bytes = 1;
|
||||||
|
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
|
||||||
|
/* Chip sometimes reporting write protect even when it's not */
|
||||||
|
out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
|
||||||
|
return;
|
||||||
|
|
||||||
|
case NAND_CMD_RESET:
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
return;
|
||||||
|
|
||||||
|
default:
|
||||||
|
printf("%s: error, unsupported command 0x%x.\n",
|
||||||
|
__func__, command);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write buf to the IFC NAND Controller Data Buffer
|
||||||
|
*/
|
||||||
|
static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
unsigned int bufsize = mtd->writesize + mtd->oobsize;
|
||||||
|
|
||||||
|
if (len <= 0) {
|
||||||
|
printf("%s of %d bytes", __func__, len);
|
||||||
|
ctrl->status = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((unsigned int)len > bufsize - ctrl->index) {
|
||||||
|
printf("%s beyond end of buffer "
|
||||||
|
"(%d requested, %u available)\n",
|
||||||
|
__func__, len, bufsize - ctrl->index);
|
||||||
|
len = bufsize - ctrl->index;
|
||||||
|
}
|
||||||
|
|
||||||
|
memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
|
||||||
|
ctrl->index += len;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* read a byte from either the IFC hardware buffer if it has any data left
|
||||||
|
* otherwise issue a command to read a single byte.
|
||||||
|
*/
|
||||||
|
static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
|
||||||
|
/* If there are still bytes in the IFC buffer, then use the
|
||||||
|
* next byte. */
|
||||||
|
if (ctrl->index < ctrl->read_bytes)
|
||||||
|
return in_8(&ctrl->addr[ctrl->index++]);
|
||||||
|
|
||||||
|
printf("%s beyond end of buffer\n", __func__);
|
||||||
|
return ERR_BYTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read two bytes from the IFC hardware buffer
|
||||||
|
* read function for 16-bit buswith
|
||||||
|
*/
|
||||||
|
static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
uint16_t data;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If there are still bytes in the IFC buffer, then use the
|
||||||
|
* next byte.
|
||||||
|
*/
|
||||||
|
if (ctrl->index < ctrl->read_bytes) {
|
||||||
|
data = in_be16((uint16_t *)&ctrl->
|
||||||
|
addr[ctrl->index]);
|
||||||
|
ctrl->index += 2;
|
||||||
|
return (uint8_t)data;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("%s beyond end of buffer\n", __func__);
|
||||||
|
return ERR_BYTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read from the IFC Controller Data Buffer
|
||||||
|
*/
|
||||||
|
static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
int avail;
|
||||||
|
|
||||||
|
if (len < 0)
|
||||||
|
return;
|
||||||
|
|
||||||
|
avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
|
||||||
|
memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
|
||||||
|
ctrl->index += avail;
|
||||||
|
|
||||||
|
if (len > avail)
|
||||||
|
printf("%s beyond end of buffer "
|
||||||
|
"(%d requested, %d available)\n",
|
||||||
|
__func__, len, avail);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Verify buffer against the IFC Controller Data Buffer
|
||||||
|
*/
|
||||||
|
static int fsl_ifc_verify_buf(struct mtd_info *mtd,
|
||||||
|
const u_char *buf, int len)
|
||||||
|
{
|
||||||
|
struct nand_chip *chip = mtd->priv;
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (len < 0) {
|
||||||
|
printf("%s of %d bytes", __func__, len);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
|
||||||
|
printf("%s beyond end of buffer "
|
||||||
|
"(%d requested, %u available)\n",
|
||||||
|
__func__, len, ctrl->read_bytes - ctrl->index);
|
||||||
|
|
||||||
|
ctrl->index = ctrl->read_bytes;
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < len; i++)
|
||||||
|
if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
|
||||||
|
break;
|
||||||
|
|
||||||
|
ctrl->index += len;
|
||||||
|
return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* This function is called after Program and Erase Operations to
|
||||||
|
* check for success or failure.
|
||||||
|
*/
|
||||||
|
static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
||||||
|
{
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
struct fsl_ifc *ifc = ctrl->regs;
|
||||||
|
u32 nand_fsr;
|
||||||
|
|
||||||
|
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
|
||||||
|
return NAND_STATUS_FAIL;
|
||||||
|
|
||||||
|
/* Use READ_STATUS command, but wait for the device to be ready */
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
|
||||||
|
IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 1);
|
||||||
|
set_addr(mtd, 0, 0, 0);
|
||||||
|
ctrl->read_bytes = 1;
|
||||||
|
|
||||||
|
fsl_ifc_run_command(mtd);
|
||||||
|
|
||||||
|
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
|
||||||
|
return NAND_STATUS_FAIL;
|
||||||
|
|
||||||
|
nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
|
||||||
|
|
||||||
|
/* Chip sometimes reporting write protect even when it's not */
|
||||||
|
nand_fsr = nand_fsr | NAND_STATUS_WP;
|
||||||
|
return nand_fsr;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int fsl_ifc_read_page(struct mtd_info *mtd,
|
||||||
|
struct nand_chip *chip,
|
||||||
|
uint8_t *buf, int page)
|
||||||
|
{
|
||||||
|
struct fsl_ifc_mtd *priv = chip->priv;
|
||||||
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
||||||
|
|
||||||
|
fsl_ifc_read_buf(mtd, buf, mtd->writesize);
|
||||||
|
fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||||
|
|
||||||
|
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
|
||||||
|
mtd->ecc_stats.failed++;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ECC will be calculated automatically, and errors will be detected in
|
||||||
|
* waitfunc.
|
||||||
|
*/
|
||||||
|
static void fsl_ifc_write_page(struct mtd_info *mtd,
|
||||||
|
struct nand_chip *chip,
|
||||||
|
const uint8_t *buf)
|
||||||
|
{
|
||||||
|
fsl_ifc_write_buf(mtd, buf, mtd->writesize);
|
||||||
|
fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_ifc_ctrl_init(void)
|
||||||
|
{
|
||||||
|
ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
|
||||||
|
if (!ifc_ctrl)
|
||||||
|
return;
|
||||||
|
|
||||||
|
ifc_ctrl->regs = IFC_BASE_ADDR;
|
||||||
|
|
||||||
|
/* clear event registers */
|
||||||
|
out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
|
||||||
|
out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
|
||||||
|
|
||||||
|
/* Enable error and event for any detected errors */
|
||||||
|
out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
|
||||||
|
IFC_NAND_EVTER_EN_OPC_EN |
|
||||||
|
IFC_NAND_EVTER_EN_PGRDCMPL_EN |
|
||||||
|
IFC_NAND_EVTER_EN_FTOER_EN |
|
||||||
|
IFC_NAND_EVTER_EN_WPER_EN);
|
||||||
|
|
||||||
|
out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_nand_init(struct nand_chip *nand)
|
||||||
|
{
|
||||||
|
struct fsl_ifc_mtd *priv;
|
||||||
|
struct nand_ecclayout *layout;
|
||||||
|
uint32_t cspr = 0, csor = 0;
|
||||||
|
|
||||||
|
if (!ifc_ctrl) {
|
||||||
|
fsl_ifc_ctrl_init();
|
||||||
|
if (!ifc_ctrl)
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||||
|
if (!priv)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
priv->ctrl = ifc_ctrl;
|
||||||
|
priv->vbase = nand->IO_ADDR_R;
|
||||||
|
|
||||||
|
/* Find which chip select it is connected to.
|
||||||
|
*/
|
||||||
|
for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
|
||||||
|
phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
|
||||||
|
|
||||||
|
cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
|
||||||
|
csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
|
||||||
|
|
||||||
|
if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
|
||||||
|
(cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
|
||||||
|
ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (priv->bank >= MAX_BANKS) {
|
||||||
|
printf("%s: address did not match any "
|
||||||
|
"chip selects\n", __func__);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
ifc_ctrl->chips[priv->bank] = priv;
|
||||||
|
|
||||||
|
/* fill in nand_chip structure */
|
||||||
|
/* set up function call table */
|
||||||
|
|
||||||
|
nand->write_buf = fsl_ifc_write_buf;
|
||||||
|
nand->read_buf = fsl_ifc_read_buf;
|
||||||
|
nand->verify_buf = fsl_ifc_verify_buf;
|
||||||
|
nand->select_chip = fsl_ifc_select_chip;
|
||||||
|
nand->cmdfunc = fsl_ifc_cmdfunc;
|
||||||
|
nand->waitfunc = fsl_ifc_wait;
|
||||||
|
|
||||||
|
/* set up nand options */
|
||||||
|
nand->bbt_td = &bbt_main_descr;
|
||||||
|
nand->bbt_md = &bbt_mirror_descr;
|
||||||
|
|
||||||
|
/* set up nand options */
|
||||||
|
nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
|
||||||
|
NAND_USE_FLASH_BBT;
|
||||||
|
|
||||||
|
if (cspr & CSPR_PORT_SIZE_16) {
|
||||||
|
nand->read_byte = fsl_ifc_read_byte16;
|
||||||
|
nand->options |= NAND_BUSWIDTH_16;
|
||||||
|
} else {
|
||||||
|
nand->read_byte = fsl_ifc_read_byte;
|
||||||
|
}
|
||||||
|
|
||||||
|
nand->controller = &ifc_ctrl->controller;
|
||||||
|
nand->priv = priv;
|
||||||
|
|
||||||
|
nand->ecc.read_page = fsl_ifc_read_page;
|
||||||
|
nand->ecc.write_page = fsl_ifc_write_page;
|
||||||
|
|
||||||
|
/* Hardware generates ECC per 512 Bytes */
|
||||||
|
nand->ecc.size = 512;
|
||||||
|
nand->ecc.bytes = 8;
|
||||||
|
|
||||||
|
switch (csor & CSOR_NAND_PGS_MASK) {
|
||||||
|
case CSOR_NAND_PGS_512:
|
||||||
|
if (nand->options & NAND_BUSWIDTH_16) {
|
||||||
|
layout = &oob_512_16bit_ecc4;
|
||||||
|
} else {
|
||||||
|
layout = &oob_512_8bit_ecc4;
|
||||||
|
|
||||||
|
/* Avoid conflict with bad block marker */
|
||||||
|
bbt_main_descr.offs = 0;
|
||||||
|
bbt_mirror_descr.offs = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->bufnum_mask = 15;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CSOR_NAND_PGS_2K:
|
||||||
|
layout = &oob_2048_ecc4;
|
||||||
|
priv->bufnum_mask = 3;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CSOR_NAND_PGS_4K:
|
||||||
|
if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
|
||||||
|
CSOR_NAND_ECC_MODE_4) {
|
||||||
|
layout = &oob_4096_ecc4;
|
||||||
|
} else {
|
||||||
|
layout = &oob_4096_ecc8;
|
||||||
|
nand->ecc.bytes = 16;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->bufnum_mask = 1;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
printf("ifc nand: bad csor %#x: bad page size\n", csor);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
|
||||||
|
if (csor & CSOR_NAND_ECC_DEC_EN) {
|
||||||
|
nand->ecc.mode = NAND_ECC_HW;
|
||||||
|
nand->ecc.layout = layout;
|
||||||
|
} else {
|
||||||
|
nand->ecc.mode = NAND_ECC_SOFT;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
|
@ -0,0 +1,271 @@
|
||||||
|
/*
|
||||||
|
* NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
|
||||||
|
*
|
||||||
|
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||||
|
* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/fsl_ifc.h>
|
||||||
|
#include <linux/mtd/nand.h>
|
||||||
|
|
||||||
|
static inline int is_blank(uchar *addr, int page_size)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < page_size; i++) {
|
||||||
|
if (__raw_readb(&addr[i]) != 0xff)
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For the SPL, don't worry about uncorrectable errors
|
||||||
|
* where the main area is all FFs but shouldn't be.
|
||||||
|
*/
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* returns nonzero if entire page is blank */
|
||||||
|
static inline int check_read_ecc(uchar *buf, u32 *eccstat,
|
||||||
|
unsigned int bufnum, int page_size)
|
||||||
|
{
|
||||||
|
u32 reg = eccstat[bufnum / 4];
|
||||||
|
int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
|
||||||
|
|
||||||
|
if (errors == 15) { /* uncorrectable */
|
||||||
|
/* Blank pages fail hw ECC checks */
|
||||||
|
if (is_blank(buf, page_size))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
puts("ecc error\n");
|
||||||
|
for (;;)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void nand_wait(uchar *buf, int bufnum, int page_size)
|
||||||
|
{
|
||||||
|
struct fsl_ifc *ifc = IFC_BASE_ADDR;
|
||||||
|
u32 status;
|
||||||
|
u32 eccstat[4];
|
||||||
|
int bufperpage = page_size / 512;
|
||||||
|
int bufnum_end, i;
|
||||||
|
|
||||||
|
bufnum *= bufperpage;
|
||||||
|
bufnum_end = bufnum + bufperpage - 1;
|
||||||
|
|
||||||
|
do {
|
||||||
|
status = in_be32(&ifc->ifc_nand.nand_evter_stat);
|
||||||
|
} while (!(status & IFC_NAND_EVTER_STAT_OPC));
|
||||||
|
|
||||||
|
if (status & IFC_NAND_EVTER_STAT_FTOER) {
|
||||||
|
puts("flash time out error\n");
|
||||||
|
for (;;)
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = bufnum / 4; i <= bufnum_end / 4; i++)
|
||||||
|
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
|
||||||
|
|
||||||
|
for (i = bufnum; i <= bufnum_end; i++) {
|
||||||
|
if (check_read_ecc(buf, eccstat, i, page_size))
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_evter_stat, status);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int bad_block(uchar *marker, int port_size)
|
||||||
|
{
|
||||||
|
if (port_size == 8)
|
||||||
|
return __raw_readb(marker) != 0xff;
|
||||||
|
else
|
||||||
|
return __raw_readw((u16 *)marker) != 0xffff;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
|
||||||
|
{
|
||||||
|
struct fsl_ifc *ifc = IFC_BASE_ADDR;
|
||||||
|
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
|
||||||
|
int page_size;
|
||||||
|
int port_size;
|
||||||
|
int pages_per_blk;
|
||||||
|
int blk_size;
|
||||||
|
int bad_marker = 0;
|
||||||
|
int bufnum_mask, bufnum;
|
||||||
|
|
||||||
|
int csor, cspr;
|
||||||
|
int pos = 0;
|
||||||
|
int j = 0;
|
||||||
|
|
||||||
|
int sram_addr;
|
||||||
|
int pg_no;
|
||||||
|
|
||||||
|
/* Get NAND Flash configuration */
|
||||||
|
csor = CONFIG_SYS_NAND_CSOR;
|
||||||
|
cspr = CONFIG_SYS_NAND_CSPR;
|
||||||
|
|
||||||
|
if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
|
||||||
|
/* soft ECC in SPL is unimplemented */
|
||||||
|
puts("WARNING: soft ECC not checked in SPL\n");
|
||||||
|
} else {
|
||||||
|
u32 hwcsor;
|
||||||
|
|
||||||
|
/* make sure board is configured with ECC on boot */
|
||||||
|
hwcsor = in_be32(&ifc->csor_cs[0].csor);
|
||||||
|
if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
|
||||||
|
puts("WARNING: ECC not checked in SPL, "
|
||||||
|
"check board cfg\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
|
||||||
|
|
||||||
|
if (csor & CSOR_NAND_PGS_4K) {
|
||||||
|
page_size = 4096;
|
||||||
|
bufnum_mask = 1;
|
||||||
|
} else if (csor & CSOR_NAND_PGS_2K) {
|
||||||
|
page_size = 2048;
|
||||||
|
bufnum_mask = 3;
|
||||||
|
} else {
|
||||||
|
page_size = 512;
|
||||||
|
bufnum_mask = 15;
|
||||||
|
|
||||||
|
if (port_size == 8)
|
||||||
|
bad_marker = 5;
|
||||||
|
}
|
||||||
|
|
||||||
|
pages_per_blk =
|
||||||
|
32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
|
||||||
|
|
||||||
|
blk_size = pages_per_blk * page_size;
|
||||||
|
|
||||||
|
/* Open Full SRAM mapping for spare are access */
|
||||||
|
out_be32(&ifc->ifc_nand.ncfgr, 0x0);
|
||||||
|
|
||||||
|
/* Clear Boot events */
|
||||||
|
out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
|
||||||
|
|
||||||
|
/* Program FIR/FCR for Large/Small page */
|
||||||
|
if (page_size > 512) {
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
|
||||||
|
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
|
||||||
|
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
|
||||||
|
} else {
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||||
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||||
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||||
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
||||||
|
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||||
|
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Program FBCR = 0 for full page read */
|
||||||
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
||||||
|
|
||||||
|
/* Read and copy u-boot on SDRAM from NAND device, In parallel
|
||||||
|
* check for Bad block if found skip it and read continue to
|
||||||
|
* next Block
|
||||||
|
*/
|
||||||
|
while (pos < uboot_size) {
|
||||||
|
int i = 0;
|
||||||
|
do {
|
||||||
|
pg_no = offs / page_size;
|
||||||
|
bufnum = pg_no & bufnum_mask;
|
||||||
|
sram_addr = bufnum * page_size * 2;
|
||||||
|
|
||||||
|
out_be32(&ifc->ifc_nand.row0, pg_no);
|
||||||
|
out_be32(&ifc->ifc_nand.col0, 0);
|
||||||
|
/* start read */
|
||||||
|
out_be32(&ifc->ifc_nand.nandseq_strt,
|
||||||
|
IFC_NAND_SEQ_STRT_FIR_STRT);
|
||||||
|
|
||||||
|
/* wait for read to complete */
|
||||||
|
nand_wait(&buf[sram_addr], bufnum, page_size);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If either of the first two pages are marked bad,
|
||||||
|
* continue to the next block.
|
||||||
|
*/
|
||||||
|
if (i++ < 2 &&
|
||||||
|
bad_block(&buf[sram_addr + page_size + bad_marker],
|
||||||
|
port_size)) {
|
||||||
|
puts("skipping\n");
|
||||||
|
offs = (offs + blk_size) & ~(blk_size - 1);
|
||||||
|
pos &= ~(blk_size - 1);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (j = 0; j < page_size; j++)
|
||||||
|
dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
|
||||||
|
|
||||||
|
pos += page_size;
|
||||||
|
offs += page_size;
|
||||||
|
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
|
||||||
|
* configured and available since this code loads the main U-boot image
|
||||||
|
* from NAND into SDRAM and starts from there.
|
||||||
|
*/
|
||||||
|
void nand_boot(void)
|
||||||
|
{
|
||||||
|
__attribute__((noreturn)) void (*uboot)(void);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Load U-Boot image from NAND into RAM
|
||||||
|
*/
|
||||||
|
nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
|
||||||
|
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
|
||||||
|
|
||||||
|
#ifdef CONFIG_NAND_ENV_DST
|
||||||
|
nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||||
|
(uchar *)CONFIG_NAND_ENV_DST);
|
||||||
|
|
||||||
|
#ifdef CONFIG_ENV_OFFSET_REDUND
|
||||||
|
nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
|
||||||
|
(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Jump to U-Boot image
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* Clean d-cache and invalidate i-cache, to
|
||||||
|
* make sure that no stale data is executed.
|
||||||
|
*/
|
||||||
|
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
|
||||||
|
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
|
||||||
|
uboot();
|
||||||
|
}
|
Loading…
Reference in New Issue