x86: Do CPU identification in the early phase
The CPU identification happens in x86_cpu_init_f() and corresponding fields are saved in the global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bin Meng
Simon Glass
parent
f67cd51e65
commit
52f952bf5e
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@ -13,6 +13,9 @@
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* Part of this file is adapted from coreboot
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* src/arch/x86/lib/cpu.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -27,6 +30,8 @@
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#include <asm/interrupt.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Constructor for a conventional segment GDT (or LDT) entry
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* This is a macro so it can be used in initialisers
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@ -43,6 +48,52 @@ struct gdt_ptr {
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u32 ptr;
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} __packed;
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struct cpu_device_id {
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unsigned vendor;
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unsigned device;
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};
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struct cpuinfo_x86 {
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uint8_t x86; /* CPU family */
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uint8_t x86_vendor; /* CPU vendor */
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uint8_t x86_model;
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uint8_t x86_mask;
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};
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/*
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* List of cpu vendor strings along with their normalized
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* id values.
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*/
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static struct {
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int vendor;
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const char *name;
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} x86_vendors[] = {
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{ X86_VENDOR_INTEL, "GenuineIntel", },
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{ X86_VENDOR_CYRIX, "CyrixInstead", },
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{ X86_VENDOR_AMD, "AuthenticAMD", },
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{ X86_VENDOR_UMC, "UMC UMC UMC ", },
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{ X86_VENDOR_NEXGEN, "NexGenDriven", },
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{ X86_VENDOR_CENTAUR, "CentaurHauls", },
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{ X86_VENDOR_RISE, "RiseRiseRise", },
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{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
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{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
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{ X86_VENDOR_NSC, "Geode by NSC", },
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{ X86_VENDOR_SIS, "SiS SiS SiS ", },
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};
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static const char *const x86_vendor_name[] = {
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[X86_VENDOR_INTEL] = "Intel",
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[X86_VENDOR_CYRIX] = "Cyrix",
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[X86_VENDOR_AMD] = "AMD",
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[X86_VENDOR_UMC] = "UMC",
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[X86_VENDOR_NEXGEN] = "NexGen",
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[X86_VENDOR_CENTAUR] = "Centaur",
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[X86_VENDOR_RISE] = "Rise",
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[X86_VENDOR_TRANSMETA] = "Transmeta",
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[X86_VENDOR_NSC] = "NSC",
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[X86_VENDOR_SIS] = "SiS",
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};
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static void load_ds(u32 segment)
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{
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asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
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@ -115,6 +166,128 @@ int __weak x86_cleanup_before_linux(void)
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return 0;
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}
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/*
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* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
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* by the fact that they preserve the flags across the division of 5/2.
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* PII and PPro exhibit this behavior too, but they have cpuid available.
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*/
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/*
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* Perform the Cyrix 5/2 test. A Cyrix won't change
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* the flags, while other 486 chips will.
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*/
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static inline int test_cyrix_52div(void)
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{
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unsigned int test;
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__asm__ __volatile__(
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"sahf\n\t" /* clear flags (%eax = 0x0005) */
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"div %b2\n\t" /* divide 5 by 2 */
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"lahf" /* store flags into %ah */
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: "=a" (test)
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: "0" (5), "q" (2)
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: "cc");
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/* AH is 0x02 on Cyrix after the divide.. */
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return (unsigned char) (test >> 8) == 0x02;
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}
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/*
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* Detect a NexGen CPU running without BIOS hypercode new enough
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* to have CPUID. (Thanks to Herbert Oppmann)
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*/
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static int deep_magic_nexgen_probe(void)
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{
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int ret;
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__asm__ __volatile__ (
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" movw $0x5555, %%ax\n"
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" xorw %%dx,%%dx\n"
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" movw $2, %%cx\n"
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" divw %%cx\n"
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" movl $0, %%eax\n"
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" jnz 1f\n"
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" movl $1, %%eax\n"
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"1:\n"
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: "=a" (ret) : : "cx", "dx");
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return ret;
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}
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static bool has_cpuid(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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static int build_vendor_name(char *vendor_name)
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{
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struct cpuid_result result;
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result = cpuid(0x00000000);
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unsigned int *name_as_ints = (unsigned int *)vendor_name;
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name_as_ints[0] = result.ebx;
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name_as_ints[1] = result.edx;
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name_as_ints[2] = result.ecx;
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return result.eax;
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}
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static void identify_cpu(struct cpu_device_id *cpu)
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{
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char vendor_name[16];
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int i;
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vendor_name[0] = '\0'; /* Unset */
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/* Find the id and vendor_name */
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if (!has_cpuid()) {
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/* Its a 486 if we can modify the AC flag */
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if (flag_is_changeable_p(X86_EFLAGS_AC))
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cpu->device = 0x00000400; /* 486 */
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else
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cpu->device = 0x00000300; /* 386 */
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if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
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memcpy(vendor_name, "CyrixInstead", 13);
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/* If we ever care we can enable cpuid here */
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}
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/* Detect NexGen with old hypercode */
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else if (deep_magic_nexgen_probe())
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memcpy(vendor_name, "NexGenDriven", 13);
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}
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if (has_cpuid()) {
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int cpuid_level;
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cpuid_level = build_vendor_name(vendor_name);
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vendor_name[12] = '\0';
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/* Intel-defined flags: level 0x00000001 */
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if (cpuid_level >= 0x00000001) {
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cpu->device = cpuid_eax(0x00000001);
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} else {
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/* Have CPUID level 0 only unheard of */
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cpu->device = 0x00000400;
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}
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}
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cpu->vendor = X86_VENDOR_UNKNOWN;
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for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
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if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
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cpu->vendor = x86_vendors[i].vendor;
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break;
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}
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}
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}
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static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
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{
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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}
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int x86_cpu_init_f(void)
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{
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const u32 em_rst = ~X86_CR0_EM;
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@ -128,6 +301,20 @@ int x86_cpu_init_f(void)
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"movl %%eax, %%cr0\n" \
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: : "i" (em_rst), "i" (mp_ne_set) : "eax");
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/* identify CPU via cpuid and store the decoded info into gd->arch */
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if (has_cpuid()) {
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struct cpu_device_id cpu;
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struct cpuinfo_x86 c;
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identify_cpu(&cpu);
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get_fms(&c, cpu.device);
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gd->arch.x86 = c.x86;
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gd->arch.x86_vendor = cpu.vendor;
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gd->arch.x86_model = c.x86_model;
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gd->arch.x86_mask = c.x86_mask;
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gd->arch.x86_device = cpu.device;
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}
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return 0;
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}
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@ -277,55 +464,14 @@ void cpu_disable_paging_pae(void)
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: "eax");
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}
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static bool has_cpuid(void)
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{
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unsigned long flag;
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asm volatile("pushf\n" \
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"pop %%eax\n"
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"mov %%eax, %%ecx\n" /* ecx = flags */
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"xor %1, %%eax\n"
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"push %%eax\n"
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"popf\n" /* flags ^= $2 */
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"pushf\n"
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"pop %%eax\n" /* eax = flags */
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"push %%ecx\n"
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"popf\n" /* flags = ecx */
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"xor %%ecx, %%eax\n"
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"mov %%eax, %0"
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: "=r" (flag)
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: "i" (1 << 21)
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: "eax", "ecx", "memory");
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return flag != 0;
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}
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static bool can_detect_long_mode(void)
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{
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unsigned long flag;
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asm volatile("mov $0x80000000, %%eax\n"
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"cpuid\n"
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"mov %%eax, %0"
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: "=r" (flag)
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:
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: "eax", "ebx", "ecx", "edx", "memory");
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return flag > 0x80000000UL;
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return cpuid_eax(0x80000000) > 0x80000000UL;
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}
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static bool has_long_mode(void)
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{
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unsigned long flag;
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asm volatile("mov $0x80000001, %%eax\n"
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"cpuid\n"
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"mov %%edx, %0"
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: "=r" (flag)
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:
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: "eax", "ebx", "ecx", "edx", "memory");
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return flag & (1 << 29) ? true : false;
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return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
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}
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int cpu_has_64bit(void)
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@ -334,9 +480,49 @@ int cpu_has_64bit(void)
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has_long_mode();
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}
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const char *cpu_vendor_name(int vendor)
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{
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const char *name;
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name = "<invalid cpu vendor>";
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if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
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(x86_vendor_name[vendor] != 0))
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name = x86_vendor_name[vendor];
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return name;
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}
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void fill_processor_name(char *processor_name)
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{
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struct cpuid_result regs;
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char temp_processor_name[49];
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char *processor_name_start;
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unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
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int i;
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for (i = 0; i < 3; i++) {
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regs = cpuid(0x80000002 + i);
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name_as_ints[i * 4 + 0] = regs.eax;
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name_as_ints[i * 4 + 1] = regs.ebx;
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name_as_ints[i * 4 + 2] = regs.ecx;
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name_as_ints[i * 4 + 3] = regs.edx;
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}
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temp_processor_name[48] = 0;
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/* Skip leading spaces. */
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processor_name_start = temp_processor_name;
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while (*processor_name_start == ' ')
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processor_name_start++;
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memset(processor_name, 0, 49);
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strcpy(processor_name, processor_name_start);
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}
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int print_cpuinfo(void)
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{
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printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
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printf("CPU: %s, vendor %s, device %xh\n",
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cpu_has_64bit() ? "x86_64" : "x86",
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cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
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return 0;
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}
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@ -1,16 +1,160 @@
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/*
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* Copyright (c) 2014 The Chromium OS Authors.
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*
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* Part of this file is adapted from coreboot
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* src/arch/x86/include/arch/cpu.h and
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* src/arch/x86/lib/cpu.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __X86_CPU_H
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#define __X86_CPU_H
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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/**
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enum {
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X86_VENDOR_INVALID = 0,
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X86_VENDOR_INTEL,
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X86_VENDOR_CYRIX,
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X86_VENDOR_AMD,
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X86_VENDOR_UMC,
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X86_VENDOR_NEXGEN,
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X86_VENDOR_CENTAUR,
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X86_VENDOR_RISE,
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X86_VENDOR_TRANSMETA,
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X86_VENDOR_NSC,
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X86_VENDOR_SIS,
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X86_VENDOR_ANY = 0xfe,
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X86_VENDOR_UNKNOWN = 0xff
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};
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struct cpuid_result {
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uint32_t eax;
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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};
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/*
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* Generic CPUID function
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*/
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static inline struct cpuid_result cpuid(int op)
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{
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struct cpuid_result result;
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asm volatile(
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"mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%ebx, %%esi;"
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"mov %%edi, %%ebx;"
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: "=a" (result.eax),
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"=S" (result.ebx),
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"=c" (result.ecx),
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"=d" (result.edx)
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: "0" (op)
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: "edi");
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return result;
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}
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/*
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* Generic Extended CPUID function
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*/
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static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
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{
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struct cpuid_result result;
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asm volatile(
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"mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%ebx, %%esi;"
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"mov %%edi, %%ebx;"
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: "=a" (result.eax),
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"=S" (result.ebx),
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"=c" (result.ecx),
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"=d" (result.edx)
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: "0" (op), "2" (ecx)
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: "edi");
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return result;
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%edi, %%ebx;"
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: "=a" (eax)
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: "0" (op)
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: "ecx", "edx", "edi");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%ebx, %%esi;"
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"mov %%edi, %%ebx;"
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: "=a" (eax), "=S" (ebx)
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: "0" (op)
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: "ecx", "edx", "edi");
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%edi, %%ebx;"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "edx", "edi");
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("mov %%ebx, %%edi;"
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"cpuid;"
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"mov %%edi, %%ebx;"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "ecx", "edi");
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return edx;
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}
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(uint32_t flag)
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{
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uint32_t f1, f2;
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asm(
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"pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
|
||||
"popl %0\n\t"
|
||||
"popfl\n\t"
|
||||
: "=&r" (f1), "=&r" (f2)
|
||||
: "ir" (flag));
|
||||
return ((f1^f2) & flag) != 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cpu_enable_paging_pae() - Enable PAE-paging
|
||||
*
|
||||
* @pdpt: Value to set in cr3 (PDPT or PML4T)
|
||||
* @cr3: Value to set in cr3 (PDPT or PML4T)
|
||||
*/
|
||||
void cpu_enable_paging_pae(ulong cr3);
|
||||
|
||||
|
|
@ -26,6 +170,22 @@ void cpu_disable_paging_pae(void);
|
|||
*/
|
||||
int cpu_has_64bit(void);
|
||||
|
||||
/**
|
||||
* cpu_vendor_name() - Get CPU vendor name
|
||||
*
|
||||
* @vendor: CPU vendor enumeration number
|
||||
*
|
||||
* @return: Address to hold the CPU vendor name string
|
||||
*/
|
||||
const char *cpu_vendor_name(int vendor);
|
||||
|
||||
/**
|
||||
* fill_processor_name() - Get processor name
|
||||
*
|
||||
* @processor_name: Address to hold the processor name string
|
||||
*/
|
||||
void fill_processor_name(char *processor_name);
|
||||
|
||||
/**
|
||||
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
|
||||
*
|
||||
|
|
|
|||
|
|
@ -13,6 +13,11 @@
|
|||
/* Architecture-specific global data */
|
||||
struct arch_global_data {
|
||||
struct global_data *gd_addr; /* Location of Global Data */
|
||||
uint8_t x86; /* CPU family */
|
||||
uint8_t x86_vendor; /* CPU vendor */
|
||||
uint8_t x86_model;
|
||||
uint8_t x86_mask;
|
||||
uint32_t x86_device;
|
||||
uint64_t tsc_base; /* Initial value returned by rdtsc() */
|
||||
uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
|
||||
uint32_t tsc_prev; /* For show_boot_progress() */
|
||||
|
|
|
|||
Loading…
Reference in New Issue