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ARM: Remove apollon board 

This board is the only board that still sticks to OneNAND IPL.
Remove this board, since we have SPL around for a while and
OneNAND is well supported in the SPL framework. The board can
be revived if necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Marek Vasut 2012-09-05 17:16:55 +00:00 committed by Tom Rini
parent e4a189acfe
commit 535c74f80c
17 changed files with 1 additions and 2383 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -777,10 +777,6 @@ Nagendra T S <nagendra@mistralsolutions.com>
am3517_crane ARM ARMV7 (AM35x SoC)
Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS

10
arch/arm/include/asm/arch-omap24xx/omap2420.h
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@ -228,16 +228,6 @@
#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
#endif /* endif CONFIG_2420H4 */
#if defined(CONFIG_APOLLON)
#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */
#define APOLLON_CS1_BASE 0x08000000 /* ethernet */
#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */
#define APOLLON_CS3_BASE 0x18000000 /* NOR */
#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b)
#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c)
#endif /* endif CONFIG_APOLLON */
/* Common */
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC

43
board/apollon/Makefile
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@ -1,43 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := apollon.o mem.o sys_info.o
SOBJS := lowlevel_init.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend

470
board/apollon/apollon.c
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@ -1,470 +0,0 @@
/*
* (C) Copyright 2005-2007
* Samsung Electronics.
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from omap2420
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/mem.h>
#include <asm/mach-types.h>
void wait_for_command_complete(unsigned int wd_base);
DECLARE_GLOBAL_DATA_PTR;
#define write_config_reg(reg, value) \
do { \
writeb(value, reg); \
} while (0)
#define mask_config_reg(reg, mask) \
do { \
char value = readb(reg) & ~(mask); \
writeb(value, reg); \
} while (0)
/*******************************************************
* Routine: delay
* Description: spinning delay to use before udelay works
******************************************************/
static inline void delay(unsigned long loops)
{
__asm__("1:\n" "subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0"(loops));
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
gd->bd->bi_arch_number = 919;
/* adress of boot parameters */
gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
return 0;
}
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with sram stack.
**********************************************************/
void s_init(void)
{
watchdog_init();
set_muxconf_regs();
delay(100);
peripheral_enable();
icache_enable();
}
/*******************************************************
* Routine: misc_init_r
* Description: Init ethernet (done here so udelay works)
********************************************************/
int misc_init_r(void)
{
return (0);
}
/****************************************
* Routine: watchdog_init
* Description: Shut down watch dogs
*****************************************/
void watchdog_init(void)
{
/* There are 4 watch dogs. 1 secure, and 3 general purpose.
* The ROM takes care of the secure one. Of the 3 GP ones,
* 1 can reset us directly, the other 2 only generate MPU interrupts.
*/
__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
wait_for_command_complete(WD2_BASE);
__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
#define MPU_WD_CLOCKED 1
#if MPU_WD_CLOCKED
/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
wait_for_command_complete(WD3_BASE);
__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
wait_for_command_complete(WD4_BASE);
__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
#endif
}
/******************************************************
* Routine: wait_for_command_complete
* Description: Wait for posting to finish on watchdog
******************************************************/
void wait_for_command_complete(unsigned int wd_base)
{
int pending = 1;
do {
pending = __raw_readl(wd_base + WWPS);
} while (pending);
}
/*******************************************************************
* Routine:board_eth_init
* Description: take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
******************************************************************/
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_LAN91C96
int cnt = 20;
__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
__raw_writew(0x0, LAN_RESET_REGISTER);
do {
__raw_writew(0x1, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0)
goto eth_reset_err_out;
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
cnt = 20;
do {
__raw_writew(0x0, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0)
goto eth_reset_err_out;
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
udelay(1000);
mask_config_reg(ETH_CONTROL_REG, 0x01);
udelay(1000);
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
eth_reset_err_out:
#endif
return rc;
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
unsigned int size;
u32 mtype, btype;
#define NOT_EARLY 0
btype = get_board_type();
mtype = get_mem_type();
display_board_info(btype);
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
/* init other chip select */
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size = get_sdr_cs_size(SDRC_CS0_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size;
#if CONFIG_NR_DRAM_BANKS > 1
size = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->bd->bi_dram[1].size = size;
#endif
return 0;
}
/**********************************************************
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers
* specific to the hardware
*********************************************************/
void set_muxconf_regs(void)
{
muxSetupSDRC();
muxSetupGPMC();
muxSetupUsb0(); /* USB Device */
muxSetupUsbHost(); /* USB Host */
muxSetupUART1();
muxSetupLCD();
muxSetupMMCSD();
muxSetupTouchScreen();
}
/*****************************************************************
* Routine: peripheral_enable
* Description: Enable the clks & power for perifs (GPT2, UART1,...)
******************************************************************/
void peripheral_enable(void)
{
unsigned int v, if_clks = 0, func_clks = 0;
/* Enable GP2 timer. */
if_clks |= BIT4 | BIT3;
func_clks |= BIT4 | BIT3;
/* Sys_clk input OMAP2420_GPT2 */
v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2;
__raw_writel(v, CM_CLKSEL2_CORE);
__raw_writel(0x1, CM_CLKSEL_WKUP);
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clock */
func_clks |= BIT21;
if_clks |= BIT21;
#endif
/* Interface clocks on */
v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;
__raw_writel(v, CM_ICLKEN1_CORE);
/* Functional Clocks on */
v = __raw_readl(CM_FCLKEN1_CORE) | func_clks;
__raw_writel(v, CM_FCLKEN1_CORE);
delay(1000);
#ifndef KERNEL_UPDATED
{
#define V1 0xffffffff
#define V2 0x00000007
__raw_writel(V1, CM_FCLKEN1_CORE);
__raw_writel(V2, CM_FCLKEN2_CORE);
__raw_writel(V1, CM_ICLKEN1_CORE);
__raw_writel(V1, CM_ICLKEN2_CORE);
}
#endif
}
/****************************************
* Routine: muxSetupUsb0 (ostboot)
* Description: Setup usb muxing
*****************************************/
void muxSetupUsb0(void)
{
mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f);
mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f);
}
/****************************************
* Routine: muxSetupUSBHost (ostboot)
* Description: Setup USB Host muxing
*****************************************/
void muxSetupUsbHost(void)
{
/* V19 */
write_config_reg(CONTROL_PADCONF_USB1_RCV, 1);
/* W20 */
write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1);
/* N14 */
write_config_reg(CONTROL_PADCONF_GPIO69, 3);
/* P15 */
write_config_reg(CONTROL_PADCONF_GPIO70, 3);
/* L18 */
write_config_reg(CONTROL_PADCONF_GPIO102, 3);
/* L19 */
write_config_reg(CONTROL_PADCONF_GPIO103, 3);
/* K15 */
write_config_reg(CONTROL_PADCONF_GPIO104, 3);
/* K14 */
write_config_reg(CONTROL_PADCONF_GPIO105, 3);
}
/****************************************
* Routine: muxSetupUART1 (ostboot)
* Description: Set up uart1 muxing
*****************************************/
void muxSetupUART1(void)
{
/* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
/* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
/* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
/* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
}
/****************************************
* Routine: muxSetupLCD (ostboot)
* Description: Setup lcd muxing
*****************************************/
void muxSetupLCD(void)
{
/* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D0, 0);
/* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D1, 0);
/* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D2, 0);
/* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D3, 0);
/* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D4, 0);
/* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D5, 0);
/* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D6, 0);
/* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D7, 0);
/* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D8, 0);
/* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D9, 0);
/* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D10, 0);
/* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D11, 0);
/* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D12, 0);
/* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D13, 0);
/* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D14, 0);
/* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D15, 0);
/* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D16, 0);
/* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_D17, 0);
/* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0);
/* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0);
/* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0);
/* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0);
}
/****************************************
* Routine: muxSetupMMCSD (ostboot)
* Description: set up MMC muxing
*****************************************/
void muxSetupMMCSD(void)
{
/* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0);
/* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0);
/* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CMD, 0);
/* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0);
/* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0);
/* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0);
/* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0);
/* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0);
/* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0);
/* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0);
/* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0);
/* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0);
}
/******************************************
* Routine: muxSetupTouchScreen (ostboot)
* Description: Set up touch screen muxing
*******************************************/
void muxSetupTouchScreen(void)
{
/* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0);
/* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0);
/* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0);
/* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0);
#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
/* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */
write_config_reg(CONTROL_PADCONF_GPIO85, 3);
}
/***************************************************************
* Routine: muxSetupGPMC (ostboot)
* Description: Configures balls which cam up in protected mode
***************************************************************/
void muxSetupGPMC(void)
{
/* gpmc_io_dir, MCR */
volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
*MCR = 0x19000000;
/* NOR FLASH CS0 */
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */
write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0);
/* MPDB(Multi Port Debug Port) CS1 */
/* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0);
/* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0);
/* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0);
/* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0);
/* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0);
/* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0);
/* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */
write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0);
}
/****************************************************************
* Routine: muxSetupSDRC (ostboot)
* Description: Configures balls which come up in protected mode
****************************************************************/
void muxSetupSDRC(void)
{
/* It's set by IPL */
}

25
board/apollon/config.mk
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@ -1,25 +0,0 @@
#
# (C) Copyright 2005-2007
# Samsung Electronics
#
# Samsung December board with OMAP2420 (ARM1136) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# December has 1 bank of 128MB mDDR-SDRAM on CS0
# December has 1 bank of 00MB mDDR-SDRAM on CS1
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1) ES2 will be configurable
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
CONFIG_SYS_TEXT_BASE = 0x83e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
#CONFIG_SYS_TEXT_BASE = 0x40270000
# Handy to get symbols to debug ROM version.
#CONFIG_SYS_TEXT_BASE = 0x0
#CONFIG_SYS_TEXT_BASE = 0x08000000

337
board/apollon/lowlevel_init.S
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@ -1,337 +0,0 @@
/*
* Board specific setup info
*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#include "mem.h"
#define APOLLON_CS0_BASE 0x00000000
#ifdef PRCM_CONFIG_I
#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
#define SDRC_RFR_CTRL_0_VAL 0x00044C01
#elif defined(PRCM_CONFIG_II)
#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
#define SDRC_RFR_CTRL_0_VAL 0x00030001
#endif
#define SDRAM_BASE_ADDRESS 0x80008000
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
#ifdef CONFIG_SYS_NOR_BOOT
/* Check running in SDRAM */
mov r0, pc, lsr #28
cmp r0, #8
beq prcm_setup
flash_setup:
/* In Flash */
ldr r0, =WD2_BASE
ldr r1, =WD_UNLOCK1
str r1, [r0, #WSPR]
ldr r1, =WD_UNLOCK2
str r1, [r0, #WSPR]
/* Pin muxing for SDRC */
mov r1, #0x00
ldr r0, =0x480000A1 /* ball C12, mode 0 */
strb r1, [r0]
ldr r0, =0x48000032 /* ball D11, mode 0 */
strb r1, [r0]
ldr r0, =0x480000A3 /* ball B13, mode 0 */
strb r1, [r0]
/* SDRC setting */
ldr r0, =OMAP2420_SDRC_BASE
ldr r1, =0x00000010
str r1, [r0, #0x10]
ldr r1, =0x00000100
str r1, [r0, #0x44]
/* SDRC CS0 configuration */
ldr r1, =0x00d04011
str r1, [r0, #0x80]
ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
str r1, [r0, #0x9C]
ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
str r1, [r0, #0xA0]
ldr r1, =SDRC_RFR_CTRL_0_VAL
str r1, [r0, #0xA4]
ldr r1, =0x00000041
str r1, [r0, #0x70]
/* Manual command sequence */
ldr r1, =0x00000007
str r1, [r0, #0xA8]
ldr r1, =0x00000000
str r1, [r0, #0xA8]
ldr r1, =0x00000001
str r1, [r0, #0xA8]
ldr r1, =0x00000002
str r1, [r0, #0xA8]
str r1, [r0, #0xA8]
/*
* CS0 SDRC Mode register
* Burst length = 4 - DDR memory
* Serial mode
* CAS latency = 3
*/
ldr r1, =0x00000032
str r1, [r0, #0x84]
/* Note: You MUST set EMR values */
/* EMR1 & EMR2 */
ldr r1, =0x00000000
str r1, [r0, #0x88]
str r1, [r0, #0x8C]
#ifdef OLD_SDRC_DLLA_CTRL
/* SDRC_DLLA_CTRL */
ldr r1, =0x00007306
str r1, [r0, #0x60]
ldr r1, =0x00007303
str r1, [r0, #0x60]
#else
/* SDRC_DLLA_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x60]
ldr r1, =0x00000503
str r1, [r0, #0x60]
#endif
#ifdef __BROKEN_FEATURE__
/* SDRC_DLLB_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x68]
ldr r1, =0x00000503
str r1, [r0, #0x68]
#endif
/* little delay after init */
mov r2, #0x1800
1:
subs r2, r2, #0x1
bne 1b
/* Setup base address */
ldr r0, =0x00000000 /* NOR address */
ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
ldr r2, =0x20000 /* Size: 128KB */
copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
ble copy_loop
ldr r1, =SDRAM_BASE_ADDRESS
mov lr, pc
mov pc, r1
#endif
prcm_setup:
ldr r0, =OMAP2420_CM_BASE
ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
bic r1, r1, #0x03
orr r1, r1, #0x02
str r1, [r0, #0x544]
ldr r1, [r0, #0x500]
bic r1, r1, #0x03
orr r1, r1, #0x01
str r1, [r0, #0x500]
ldr r1, [r0, #0x140]
bic r1, r1, #0x1f
orr r1, r1, #0x02
str r1, [r0, #0x140]
#ifdef PRCM_CONFIG_I
ldr r1, =0x000003C3
#else
ldr r1, =0x00000343
#endif
str r1, [r0, #0x840]
ldr r1, =0x00000002
str r1, [r0, #0x340]
ldr r1, =CM_CLKSEL1_CORE
#ifdef PRCM_CONFIG_I
ldr r2, =0x08300C44
#else
ldr r2, =0x04600C26
#endif
str r2, [r1]
ldr r0, =OMAP2420_CM_BASE
ldr r1, [r0, #0x084]
and r1, r1, #0x01
cmp r1, #0x01
bne clkvalid
b .
clkvalid:
mov r1, #0x01
str r1, [r0, #0x080]
waitvalid:
ldr r1, [r0, #0x084]
and r1, r1, #0x01
cmp r1, #0x00
bne waitvalid
ldr r0, =CM_CLKSEL1_PLL
#ifdef PRCM_CONFIG_I
ldr r1, =0x01837100
#else
ldr r1, =0x01832100
#endif
str r1, [r0]
ldr r0, =PRCM_CLKCFG_CTRL
mov r1, #0x01
str r1, [r0]
mov r6, #0x50
loop1:
subs r6, r6, #0x01
cmp r6, #0x01
bne loop1
ldr r0, =CM_CLKEN_PLL
mov r1, #0x0f
str r1, [r0]
mov r6, #0x100
loop2:
subs r6, r6, #0x01
cmp r6, #0x01
bne loop2
ldr r0, =0x48008200
ldr r1, =0xbfffffff
str r1, [r0]
ldr r0, =0x48008210
ldr r1, =0xfffffff9
str r1, [r0]
ldr r0, =0x4806a004
ldr r1, =0x00
strb r1, [r0]
ldr r0, =0x4806a020
ldr r1, =0x07
strb r1, [r0]
ldr r0, =0x4806a00c
ldr r1, =0x83
strb r1, [r0]
ldr r0, =0x4806a000
ldr r1, =0x1a
strb r1, [r0]
ldr r0, =0x4806a004
ldr r1, =0x00
strb r1, [r0]
ldr r0, =0x4806a00c
ldr r1, =0x03
strb r1, [r0]
ldr r0, =0x4806a010
ldr r1, =0x03
strb r1, [r0]
ldr r0, =0x4806a008
ldr r1, =0x04
strb r1, [r0]
ldr r0, =0x4806a020
ldr r1, =0x00
strb r1, [r0]
#if 0
ldr r0, =0x4806a000
mov r1, #'u'
strb r1, [r0]
#endif
#if 0
/* LED0 OFF */
ldr r3, =0x480000E5
mov r4, #0x0b
strb r4, [r3]
#endif
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
bl s_init /* go setup pll,mux,memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
/* map interrupt controller */
ldr r0, VAL_INTH_SETUP
mcr p15, 0, r0, c15, c2, 4
/* back to arch calling code */
mov pc, lr
/* the literal pools origin */
.ltorg
VAL_INTH_SETUP:
.word PERIFERAL_PORT_BASE
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK

237
board/apollon/mem.c
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@ -1,237 +0,0 @@
/*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from omap2420
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include "mem.h"
/************************************************************
* sdelay() - simple spin loop. Will be constant time as
* its generally used in 12MHz bypass conditions only. This
* is necessary until timers are accessible.
*
* not inline to increase chances its in cache when called
*************************************************************/
void sdelay(unsigned long loops)
{
__asm__("1:\n" "subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0"(loops));
}
/********************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
* (config II default).
* -- called from SRAM, or Flash (using temp SRAM stack).
********************************************************************/
void prcm_init(void) { }
/**************************************************************************
* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
* command line mem=xyz use all memory with out discontigious support
* compiled in. Could do it at the ATAG, but there really is two banks...
* Called as part of 2nd phase DDR init.
**************************************************************************/
void make_cs1_contiguous(void)
{
u32 size, a_add_low, a_add_high;
size = get_sdr_cs_size(SDRC_CS0_OSET);
size /= SZ_32M; /* find size to offset CS1 */
a_add_high = (size & 3) << 8; /* set up low field */
a_add_low = (size & 0x3C) >> 2; /* set up high field */
__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
}
/********************************************************
* mem_ok() - test used to see if timings are correct
* for a part. Helps in gussing which part
* we are currently using.
*******************************************************/
u32 mem_ok(void)
{
u32 val1, val2;
u32 pattern = 0x12345678;
/* clear pos A */
__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
/* pattern to pos B */
__raw_writel(pattern, OMAP2420_SDRC_CS0);
/* remove pattern off the bus */
__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
/* get pos A value */
val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
/* see if pos A value changed */
if ((val1 != 0) || (val2 != pattern))
return (0);
else
return (1);
}
/********************************************************
* sdrc_init() - init the sdrc chip selects CS0 and CS1
* - early init routines, called from flash or
* SRAM.
*******************************************************/
void sdrc_init(void)
{
#define EARLY_INIT 1
/* only init up first bank here */
do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
}
/*************************************************************************
* do_sdrc_init(): initialize the SDRAM for use.
* -called from low level code with stack only.
* -code sets up SDRAM timing and muxing for 2422 or 2420.
* -optimal settings can be placed here, or redone after i2c
* inspection of board info
*
* This is a bit ugly, but should handle all memory moduels
* used with the APOLLON. The first time though this code from s_init()
* we configure the first chip select. Later on we come back and
* will configure the 2nd chip select if it exists.
*
**************************************************************************/
void do_sdrc_init(u32 offset, u32 early)
{
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
u32 mux = 0, mtype, mwidth, rev, tval;
rev = get_cpu_rev();
if (rev == CPU_2420_2422_ES1)
tval = 1;
else
tval = 0; /* disable bit switched meaning */
/* global settings */
__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
__raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
#ifdef CONFIG_SYS_NAND_BOOT
/* set nWP, disable limited addr */
__raw_writel(0x001, GPMC_CONFIG);
#else
/* set nWP, disable limited addr */
__raw_writel(0x111, GPMC_CONFIG);
#endif
/* discover bus connection from sysboot */
if (is_gpmc_muxed() == GPMC_MUXED)
mux = BIT9;
mtype = get_gpmc0_type();
mwidth = get_gpmc0_width();
/* setup cs0 */
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
sdelay(1000);
#ifdef CONFIG_SYS_NOR_BOOT
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
#else
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
GPMC_CONFIG1_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
#endif
sdelay(2000);
/* setup cs1 */
__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
sdelay(1000);
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
sdelay(2000);
/* setup cs2 */
__raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */
sdelay(1000);
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
GPMC_CONFIG1_2);
/* It's same as cs 0 */
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
#ifdef CONFIG_SYS_NOR_BOOT
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
#else
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
#endif
#ifndef CONFIG_SYS_NOR_BOOT
/* setup cs3 */
__raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
sdelay(1000);
__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
#endif
#ifndef ASYNC_NOR
__raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
__raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
__raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
#endif
sdelay(2000);
}

170
board/apollon/mem.h
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@ -1,170 +0,0 @@
/*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _APOLLON_OMAP24XX_MEM_H_
#define _APOLLON_OMAP24XX_MEM_H_
/* Slower full frequency range default timings for x32 operation*/
#define APOLLON_2420_SDRC_SHARING 0x00000100
#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
/* optimized timings good for current shipping parts */
#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
#ifdef PRCM_CONFIG_I
#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
#elif PRCM_CONFIG_II
#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
#endif
/* GPMC settings */
#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
/* CS0: OneNAND */
# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
/* CS1: Ethernet */
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
/* CS2: OneNAND */
/* It's same as CS0 */
# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
/* CS3: NOR */
#ifdef ASYNC_NOR
# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
#else
# define SYNC_NOR_VALUE 0x24aaa
# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
#endif /* ASYNC_NOR */
# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
#endif /* endif PRCM_CONFIG_I */
#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
/* CS0: OneNAND */
# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
/* CS1: ethernet */
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
/* CS2: OneNAND */
/* It's same as CS0 */
# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
/* CS3: NOR */
#define ASYNC_NOR
#ifdef ASYNC_NOR
# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
#else
# define SYNC_NOR_VALUE 0x24aaa
# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
#endif /* ASYNC_NOR */
# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
#endif /* endif PRCM_CONFIG_II */
#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
# ifdef CONFIG_SYS_NAND_BOOT
# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
# else /* NOR boot */
# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
# endif /* endif CONFIG_SYS_NAND_BOOT */
# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
#endif /* endif CONFIG_SYS_PRCM_III */
#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */

396
board/apollon/sys_info.c
View File

@ -1,396 +0,0 @@
/*
* (C) Copyright 2005-2007
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from omap2420
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/arch/sys_info.h>
#include <i2c.h>
/**************************************************************************
* get_prod_id() - get id info from chips
***************************************************************************/
static u32 get_prod_id(void)
{
u32 p;
p = __raw_readl(PRODUCTION_ID); /* get production ID */
return ((p & CPU_242X_PID_MASK) >> 16);
}
/**************************************************************************
* get_cpu_type() - low level get cpu type
* - no C globals yet.
* - just looking to say if this is a 2422 or 2420 or ...
* - to start with we will look at switch settings..
* - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
* (mux for 2420, non-mux for 2422).
***************************************************************************/
u32 get_cpu_type(void)
{
u32 v;
switch (get_prod_id()) {
case 1:; /* 2420 */
case 2:
return (CPU_2420);
break; /* 2420 pop */
case 4:
return (CPU_2422);
break;
case 8:
return (CPU_2423);
break;
default:
break; /* early 2420/2422's unmarked */
}
v = __raw_readl(TAP_IDCODE_REG);
v &= CPU_24XX_ID_MASK;
/* currently 2420 and 2422 have same id */
if (v == CPU_2420_CHIPID) {
if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
return (CPU_2420);
else
return (CPU_2422);
} else
return (CPU_2420); /* don't know, say 2420 */
}
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
u32 get_cpu_rev(void)
{
u32 v;
v = __raw_readl(TAP_IDCODE_REG);
v = v >> 28;
return (v + 1); /* currently 2422 and 2420 match up */
}
/****************************************************
* is_mem_sdr() - return 1 if mem type in use is SDR
****************************************************/
u32 is_mem_sdr(void)
{
volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET);
if (*burst == H4_2420_SDRC_MR_0_SDR)
return (1);
return (0);
}
/***********************************************************
* get_mem_type() - identify type of mDDR part used.
* 2422 uses stacked DDR, 2 parts CS0/CS1.
* 2420 may have 1 or 2, no good way to know...only init 1...
* when eeprom data is up we can select 1 more.
*************************************************************/
u32 get_mem_type(void)
{
u32 cpu, sdr = is_mem_sdr();
cpu = get_cpu_type();
if (cpu == CPU_2422 || cpu == CPU_2423)
return (DDR_STACKED);
if (get_prod_id() == 0x2)
return (XDR_POP);
if (get_board_type() == BOARD_H4_MENELAUS)
if (sdr)
return (SDR_DISCRETE);
else
return (DDR_COMBO);
else if (sdr) /* SDP + SDR kit */
return (SDR_DISCRETE);
else
return (DDR_DISCRETE); /* origional SDP */
}
/***********************************************************************
* get_cs0_size() - get size of chip select 0/1
************************************************************************/
u32 get_sdr_cs_size(u32 offset)
{
u32 size;
size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */
size &= 0x2FF; /* remove unwanted bits */
size *= SZ_2M; /* find size in MB */
return (size);
}
/***********************************************************************
* get_board_type() - get board type based on current production stats.
* --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
* when they are available we can get info from there. This should
* be correct of all known boards up until today.
************************************************************************/
u32 get_board_type(void)
{
return (BOARD_H4_SDP);
}
/******************************************************************
* get_sysboot_value() - get init word settings (dip switch on h4)
******************************************************************/
inline u32 get_sysboot_value(void)
{
return (0x00000FFF & __raw_readl(CONTROL_STATUS));
}
/***************************************************************************
* get_gpmc0_base() - Return current address hardware will be
* fetching from. The below effectively gives what is correct, its a bit
* mis-leading compared to the TRM. For the most general case the mask
* needs to be also taken into account this does work in practice.
* - for u-boot we currently map:
* -- 0 to nothing,
* -- 4 to flash
* -- 8 to enent
* -- c to wifi
****************************************************************************/
u32 get_gpmc0_base(void)
{
u32 b;
b = __raw_readl(GPMC_CONFIG7_0);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return (b);
}
/*****************************************************************
* is_gpmc_muxed() - tells if address/data lines are multiplexed
*****************************************************************/
u32 is_gpmc_muxed(void)
{
u32 mux;
mux = get_sysboot_value();
if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
return (GPMC_MUXED); /* NAND Boot mode */
if (mux & BIT1) /* if mux'ed */
return (GPMC_MUXED);
else
return (GPMC_NONMUXED);
}
/************************************************************************
* get_gpmc0_type() - read sysboot lines to see type of memory attached
************************************************************************/
u32 get_gpmc0_type(void)
{
u32 type;
type = get_sysboot_value();
if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2))
return (TYPE_NAND);
else
return (TYPE_NOR);
}
/*******************************************************************
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
*******************************************************************/
u32 get_gpmc0_width(void)
{
u32 width;
width = get_sysboot_value();
if ((width & 0xF) == (BIT3 | BIT2))
return (WIDTH_8BIT);
else
return (WIDTH_16BIT);
}
/*********************************************************************
* wait_on_value() - common routine to allow waiting for changes in
* volatile regs.
*********************************************************************/
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
{
u32 i = 0, val;
do {
++i;
val = __raw_readl(read_addr) & read_bit_mask;
if (val == match_value)
return (1);
if (i == bound)
return (0);
} while (1);
}
/*********************************************************************
* display_board_info() - print banner with board info.
*********************************************************************/
void display_board_info(u32 btype)
{
char cpu_2420[] = "2420"; /* cpu type */
char cpu_2422[] = "2422";
char cpu_2423[] = "2423";
char mem_sdr[] = "mSDR"; /* memory type */
char mem_ddr[] = "mDDR";
char t_tst[] = "TST"; /* security level */
char t_emu[] = "EMU";
char t_hs[] = "HS";
char t_gp[] = "GP";
char unk[] = "?";
char *cpu_s, *mem_s, *sec_s;
u32 cpu, rev, sec;
rev = get_cpu_rev();
cpu = get_cpu_type();
sec = get_device_type();
if (is_mem_sdr())
mem_s = mem_sdr;
else
mem_s = mem_ddr;
if (cpu == CPU_2423)
cpu_s = cpu_2423;
else if (cpu == CPU_2422)
cpu_s = cpu_2422;
else
cpu_s = cpu_2420;
switch (sec) {
case TST_DEVICE:
sec_s = t_tst;
break;
case EMU_DEVICE:
sec_s = t_emu;
break;
case HS_DEVICE:
sec_s = t_hs;
break;
case GP_DEVICE:
sec_s = t_gp;
break;
default:
sec_s = unk;
}
printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1);
printf("Samsung Apollon SDP Base Board + %s \n", mem_s);
}
/*************************************************************************
* get_board_rev() - setup to pass kernel board revision information
* 0 = 242x IP platform (first 2xx boards)
* 1 = 242x Menelaus platfrom.
*************************************************************************/
u32 get_board_rev(void)
{
u32 rev = 0;
u32 btype = get_board_type();
if (btype == BOARD_H4_MENELAUS)
rev = 1;
return (rev);
}
/********************************************************
* get_base(); get upper addr of current execution
*******************************************************/
u32 get_base(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
val &= 0xF0000000;
val >>= 28;
return (val);
}
/********************************************************
* get_base2(); get 2upper addr of current execution
*******************************************************/
u32 get_base2(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
val &= 0xFF000000;
val >>= 24;
return (val);
}
/********************************************************
* running_in_flash() - tell if currently running in
* flash.
*******************************************************/
u32 running_in_flash(void)
{
if (get_base() < 4)
return (1); /* in flash */
return (0); /* running in SRAM or SDRAM */
}
/********************************************************
* running_in_sram() - tell if currently running in
* sram.
*******************************************************/
u32 running_in_sram(void)
{
if (get_base() == 4)
return (1); /* in SRAM */
return (0); /* running in FLASH or SDRAM */
}
/********************************************************
* running_in_sdram() - tell if currently running in
* flash.
*******************************************************/
u32 running_in_sdram(void)
{
if (get_base() > 4)
return (1); /* in sdram */
return (0); /* running in SRAM or FLASH */
}
/*************************************************************
* running_from_internal_boot() - am I a signed NOR image.
*************************************************************/
u32 running_from_internal_boot(void)
{
u32 v, base;
v = get_sysboot_value() & BIT3;
base = get_base2();
/* if running at mask rom flash address and
* sysboot3 says this was an internal boot
*/
if ((base == 0x08) && v)
return (1);
else
return (0);
}
/*************************************************************
* get_device_type(): tell if GP/HS/EMU/TST
*************************************************************/
u32 get_device_type(void)
{
int mode;
mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8);
return (mode >>= 8);
}

1
boards.cfg
View File

@ -50,7 +50,6 @@ tt01 arm arm1136 - hale
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
apollon arm arm1136 apollon - omap24xx
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835

1
doc/README.scrapyard
View File

@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
apollon arm omap24xx - 2012-09-06 Kyungmin Park <kyungmin.park@samsung.com>
tb0229 mips mips32 - 2011-12-12
rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de>
OXC powerpc MPC8240 309a292 2011-12-07

261
include/configs/apollon.h
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@ -1,261 +0,0 @@
/*
* (C) Copyright 2005-2008
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Configuration settings for the 2420 Samsung Apollon board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP2420 1 /* which is in a 2420 */
#define CONFIG_OMAP2420_APOLLON 1
#define CONFIG_APOLLON 1
#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
#define CONFIG_ONENAND_U_BOOT y
/* Clock config to target*/
#define PRCM_CONFIG_I 1
/* #define PRCM_CONFIG_II 1 */
/* Boot method */
/* uncomment if you use NOR boot */
/* #define CONFIG_SYS_NOR_BOOT 1 */
/* uncomment if you use NOR on CS3 */
/* #define CONFIG_SYS_USE_NOR 1 */
#ifdef CONFIG_SYS_NOR_BOOT
#undef CONFIG_SYS_USE_NOR
#define CONFIG_SYS_USE_NOR 1
#endif
/* uncommnet if you want to use UBI */
#define CONFIG_SYS_USE_UBI
#include <asm/arch/omap2420.h> /* get chip and board defs */
#define V_SCLK 12000000
/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ V_SCLK
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE_FLEX SZ_256K
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
/*
* Hardware drivers
*/
/*
* SMC91c96 Etherent
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* UART1 on H4 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ONENAND
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#endif
#undef CONFIG_CMD_SOURCE
#ifndef CONFIG_SYS_USE_NOR
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_IMLS
#endif
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTDELAY 1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.116.25
#define CONFIG_SERVERIP 192.168.116.1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_ETHADDR 00:0E:99:00:24:20
#ifdef CONFIG_APOLLON_PLUS
#define CONFIG_SYS_MEM "mem=64M"
#else
#define CONFIG_SYS_MEM "mem=128"
#endif
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_SYS_UBI "ubi.mtd=4"
#else
#define CONFIG_SYS_UBI ""
#endif
#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
" console=ttyS0,115200n8" \
" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
CONFIG_SYS_UBI
#define CONFIG_EXTRA_ENV_SETTINGS \
"Image=tftp 0x80008000 Image; go 0x80008000\0" \
"zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
"xloader=tftp 0x80180000 x-load.bin; " \
" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
"onesyncboot=run syncmode oneboot\0" \
"updateb=tftp 0x80180000 u-boot-onenand.bin; " \
" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
"bootcmd=run uboot\0"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "Apollon # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
/* default load address */
#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0)
/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
* or by 32KHz clk, or from external sig. This rate is divided by a local
* divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_128M
#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#ifdef CONFIG_SYS_USE_NOR
/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
# define CONFIG_SYS_FLASH_BASE 0x18000000
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_MAX_FLASH_SECT 1024
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* Flash memory is CFI compliant */
# define CONFIG_SYS_FLASH_CFI 1
# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
/* Use buffered writes (~10x faster) */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
/* Use h/w sector protection*/
# define CONFIG_SYS_FLASH_PROTECTION 1
#else /* !CONFIG_SYS_USE_NOR */
# define CONFIG_SYS_NO_FLASH 1
#endif /* CONFIG_SYS_USE_NOR */
/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
#define CONFIG_SYS_ONENAND_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_ADDR 0x00020000
#define CONFIG_ENV_ADDR_FLEX 0x00040000
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "onenand0=onenand"
#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \
"128k(params)," \
"2m(kernel)," \
"16m(rootfs)," \
"32m(fs)," \
"-(ubifs)"
#endif
#define PHYS_SRAM 0x4020F800
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */

87
onenand_ipl/board/apollon/Makefile
View File

@ -1,87 +0,0 @@
include $(TOPDIR)/config.mk
include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
SOBJS := low_levelinit.o
SOBJS += start.o
COBJS := apollon.o
COBJS += onenand_read.o
COBJS += onenand_boot.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
onenandobj := $(OBJTREE)/onenand_ipl/
ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin
all: $(obj).depend $(ALL)
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-Map $@.map -o $@
$(onenandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links from common files
# from cpu directory
$(obj)start.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
# from onenand_ipl directory
$(obj)onenand_ipl.h:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
$(obj)onenand_boot.c: $(obj)onenand_ipl.h
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
$(obj)onenand_read.c: $(obj)onenand_ipl.h
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)apollon.c:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/apollon.c $@
$(obj)low_levelinit.S:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/low_levelinit.S $@
endif
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)$.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

70
onenand_ipl/board/apollon/apollon.c
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@ -1,70 +0,0 @@
/*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/mux.h>
#define write_config_reg(reg, value) \
do { \
writeb(value, reg); \
} while (0)
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
return 0;
}
#ifdef CONFIG_SYS_PRINTF
/* Pin Muxing registers used for UART1 */
/****************************************
* Routine: muxSetupUART1 (ostboot)
* Description: Set up uart1 muxing
*****************************************/
static void muxSetupUART1(void)
{
/* UART1_CTS pin configuration, PIN = D21 */
write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
/* UART1_RTS pin configuration, PIN = H21 */
write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
/* UART1_TX pin configuration, PIN = L20 */
write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
/* UART1_RX pin configuration, PIN = T21 */
write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
}
#endif
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called at time when only stack is available.
**********************************************************/
int s_init(int skip)
{
#ifdef CONFIG_SYS_PRINTF
muxSetupUART1();
#endif
return 0;
}

14
onenand_ipl/board/apollon/config.mk
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@ -1,14 +0,0 @@
#
# (C) Copyright 2005-2008 Samsung Electronics
# Kyungmin Park <kyungmin.park@samsung.com>
#
# Samsung Apollon board with OMAP2420 (ARM1136) cpu
#
# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0
# Physical Address:
# 8000'0000 (bank0)
# 8800'0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
CONFIG_SYS_TEXT_BASE = 0x00000000

205
onenand_ipl/board/apollon/low_levelinit.S
View File

@ -1,205 +0,0 @@
/*
* Board specific setup info
*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from board/omap2420h4/platform.S
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#define APOLLON_CS0_BASE 0x00000000
#ifdef PRCM_CONFIG_I
#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
#define SDRC_RFR_CTRL_0_VAL 0x00044C01
/* GPMC */
#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
#define APOLLON_GPMC_CONFIG2_0 0x000c1000
#define APOLLON_GPMC_CONFIG3_0 0x00030400
#define APOLLON_GPMC_CONFIG4_0 0x0B841006
#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
#define APOLLON_GPMC_CONFIG6_0 0x00000000
#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
#elif defined(PRCM_CONFIG_II)
#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
#define SDRC_RFR_CTRL_0_VAL 0x00030001
/* GPMC */
#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
#define APOLLON_GPMC_CONFIG2_0 0x00080E81
#define APOLLON_GPMC_CONFIG3_0 0x00030400
#define APOLLON_GPMC_CONFIG4_0 0x08041586
#define APOLLON_GPMC_CONFIG5_0 0x020C090E
#define APOLLON_GPMC_CONFIG6_0 0x00000000
#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
#else
#error "Please configure PRCM schecm"
#endif
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
mov r3, r0 /* save skip information */
/* Disable watchdog */
ldr r0, =WD2_BASE
ldr r1, =WD_UNLOCK1
str r1, [r0, #WSPR]
ldr r1, =WD_UNLOCK2
str r1, [r0, #WSPR]
#ifdef DEBUG_LED
/* LED0 OFF */
ldr r0, =0x480000E5 /* ball AA10, mode 3 */
mov r1, #0x0b
strb r1, [r0]
#endif
/* Pin muxing for SDRC */
mov r1, #0x00
ldr r0, =0x480000A1 /* ball C12, mode 0 */
strb r1, [r0]
ldr r0, =0x48000032 /* ball D11, mode 0 */
strb r1, [r0]
ldr r0, =0x480000A3 /* ball B13, mode 0 */
strb r1, [r0]
/* SDRC setting */
ldr r0, =OMAP2420_SDRC_BASE
ldr r1, =0x00000010
str r1, [r0, #0x10]
ldr r1, =0x00000100
str r1, [r0, #0x44]
/* SDRC CS0 configuration */
#ifdef CONFIG_APOLLON_PLUS
ldr r1, =0x01702011
#else
ldr r1, =0x00d04011
#endif
str r1, [r0, #0x80]
ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
str r1, [r0, #0x9C]
ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
str r1, [r0, #0xA0]
ldr r1, =SDRC_RFR_CTRL_0_VAL
str r1, [r0, #0xA4]
ldr r1, =0x00000041
str r1, [r0, #0x70]
/* Manual command sequence */
ldr r1, =0x00000007
str r1, [r0, #0xA8]
ldr r1, =0x00000000
str r1, [r0, #0xA8]
ldr r1, =0x00000001
str r1, [r0, #0xA8]
ldr r1, =0x00000002
str r1, [r0, #0xA8]
str r1, [r0, #0xA8]
/*
* CS0 SDRC Mode register
* Burst length = 4 - DDR memory
* Serial mode
* CAS latency = 3
*/
ldr r1, =0x00000032
str r1, [r0, #0x84]
/* Note: You MUST set EMR values */
/* EMR1 & EMR2 */
ldr r1, =0x00000000
str r1, [r0, #0x88]
str r1, [r0, #0x8C]
#ifdef OLD_SDRC_DLLA_CTRL
/* SDRC_DLLA_CTRL */
ldr r1, =0x00007306
str r1, [r0, #0x60]
ldr r1, =0x00007303
str r1, [r0, #0x60]
#else
/* SDRC_DLLA_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x60]
ldr r1, =0x00000503
str r1, [r0, #0x60]
#endif
#ifdef __BROKEN_FEATURE__
/* SDRC_DLLB_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x68]
ldr r1, =0x00000503
str r1, [r0, #0x68]
#endif
/* little delay after init */
mov r2, #0x1800
1:
subs r2, r2, #0x1
bne 1b
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
mov r0, r3 /* pass skip info to s_init */
bl s_init /* go setup pll,mux,memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
/* back to arch calling code */
mov pc, lr
/* the literal pools origin */
.ltorg
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK

53
onenand_ipl/board/apollon/u-boot.onenand.lds
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@ -1,53 +0,0 @@
/*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from X-loader
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) . = ALIGN(4); }
__bss_end__ = .;
}