ARM: AM43xx: clocks: Update DPLL details for EPOS EVM
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM. Following are the DPLL locking frequencies at OPP NOM: MPU locks at 600MHz Core locks at 1000MHz Per locks at 960MHz DDR locks at 266MHz Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
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static void setup_dplls(void)
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{
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const struct dpll_params *params;
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do_setup_dpll(&dpll_core_regs, &dpll_core);
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
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do_setup_dpll(&dpll_per_regs, &dpll_per);
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params = get_dpll_core_params();
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do_setup_dpll(&dpll_core_regs, params);
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params = get_dpll_mpu_params();
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do_setup_dpll(&dpll_mpu_regs, params);
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params = get_dpll_per_params();
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do_setup_dpll(&dpll_per_regs, params);
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writel(0x300, &cmwkup->clkdcoldodpllper);
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params = get_dpll_ddr_params();
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@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
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const struct dpll_params dpll_per = {
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960, OSC-1, 5, -1, -1, -1, -1};
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const struct dpll_params *get_dpll_mpu_params(void)
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{
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return &dpll_mpu;
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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return &dpll_core;
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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return &dpll_per;
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}
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void setup_clocks_for_console(void)
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{
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clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
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@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
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.cm_idlest_dpll = CM_WKUP + 0x5A4,
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.cm_clksel_dpll = CM_WKUP + 0x5AC,
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.cm_div_m2_dpll = CM_WKUP + 0x5B0,
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.cm_div_m4_dpll = CM_WKUP + 0x5B8,
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};
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const struct dpll_params dpll_mpu = {
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-1, -1, -1, -1, -1, -1, -1};
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const struct dpll_params dpll_core = {
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-1, -1, -1, -1, -1, -1, -1};
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const struct dpll_params dpll_per = {
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-1, -1, -1, -1, -1, -1, -1};
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void setup_clocks_for_console(void)
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{
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/* Do not add any spl_debug prints in this function */
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@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
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extern const struct dpll_regs dpll_core_regs;
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extern const struct dpll_regs dpll_per_regs;
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extern const struct dpll_regs dpll_ddr_regs;
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extern const struct dpll_params dpll_mpu;
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extern const struct dpll_params dpll_core;
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extern const struct dpll_params dpll_per;
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extern const struct dpll_params dpll_ddr;
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extern struct cm_wkuppll *const cmwkup;
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const struct dpll_params *get_dpll_mpu_params(void);
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const struct dpll_params *get_dpll_core_params(void);
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const struct dpll_params *get_dpll_per_params(void);
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const struct dpll_params *get_dpll_ddr_params(void);
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void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
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void prcm_init(void);
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@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
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#ifdef CONFIG_SPL_BUILD
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const struct dpll_params dpll_ddr = {
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-1, -1, -1, -1, -1, -1, -1};
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const struct dpll_params epos_evm_dpll_ddr = {
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266, 24, 1, -1, 1, -1, -1};
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const struct dpll_params epos_evm_dpll_mpu = {
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600, 24, 1, -1, -1, -1, -1};
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const struct dpll_params epos_evm_dpll_core = {
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1000, 24, -1, -1, 10, 8, 4};
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const struct dpll_params epos_evm_dpll_per = {
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960, 24, 5, -1, -1, -1, -1};
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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return &dpll_ddr;
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if (board_is_eposevm())
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return &epos_evm_dpll_ddr;
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}
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const struct dpll_params *get_dpll_mpu_params(void)
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{
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if (board_is_eposevm())
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return &epos_evm_dpll_mpu;
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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struct am43xx_board_id header;
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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if (board_is_eposevm())
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return &epos_evm_dpll_core;
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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if (board_is_eposevm())
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return &epos_evm_dpll_per;
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}
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void set_uart_mux_conf(void)
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@ -46,4 +46,5 @@ static inline int board_is_gpevm(void)
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void enable_uart0_pin_mux(void);
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void enable_board_pin_mux(void);
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void enable_i2c0_pin_mux(void);
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#endif
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@ -45,3 +45,8 @@ void enable_board_pin_mux(void)
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configure_module_pin_mux(mmc0_pin_mux);
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configure_module_pin_mux(i2c0_pin_mux);
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}
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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