x86: gpio: Add GPIO driver for Intel ICH6 and later.
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bill Richardson
Simon Glass
parent
468ebf190a
commit
55ae10f8db
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2012, Google Inc. All rights reserved.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _X86_GPIO_H_
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#define _X86_GPIO_H_
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#include <asm-generic/gpio.h>
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#endif /* _X86_GPIO_H_ */
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@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libgpio.o
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COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
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COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
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COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
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COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
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COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
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@ -0,0 +1,242 @@
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/*
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* Copyright (c) 2012 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
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* through the PCI bus. Each PCI device has 256 bytes of configuration space,
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* consisting of a standard header and a device-specific set of registers. PCI
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* bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
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* other things). Within the PCI configuration space, the GPIOBASE register
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* tells us where in the device's I/O region we can find more registers to
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* actually access the GPIOs.
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*
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* PCI bus/device/function 0:1f:0 => PCI config registers
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* PCI config register "GPIOBASE"
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* PCI I/O space + [GPIOBASE] => start of GPIO registers
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* GPIO registers => gpio pin function, direction, value
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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/* Where in config space is the register that points to the GPIO registers? */
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#define PCI_CFG_GPIOBASE 0x48
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/*
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* There are often more than 32 GPIOs, depending on the ICH version.
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* For now, we just support bank 0 because it's the same for all.
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*/
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#define GPIO_MAX 31
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/* Within the I/O space, where are the registers to control the GPIOs? */
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#define OFS_GPIO_USE_SEL 0x00
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#define OFS_GPIO_IO_SEL 0x04
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#define OFS_GP_LVL 0x0C
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static pci_dev_t dev; /* handle for 0:1f:0 */
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static u32 gpiobase; /* offset into I/O space */
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static int found_it_once; /* valid GPIO device? */
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static int in_use[GPIO_MAX]; /* "lock" for access to pins */
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static int gpio_init(void)
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{
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u8 tmpbyte;
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u16 tmpword;
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u32 tmplong;
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/* Have we already done this? */
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if (found_it_once)
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return 0;
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/* Where should it be? */
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dev = PCI_BDF(0, 0x1f, 0);
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/* Is the device present? */
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pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword);
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if (tmpword != PCI_VENDOR_ID_INTEL) {
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debug("%s: wrong VendorID\n", __func__);
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return -1;
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}
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/*
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* We'd like to check the Device ID too, but pretty much any
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* value is either a) correct with slight differences, or b)
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* correct but undocumented. We'll have to check other things
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* instead...
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*/
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/* I/O should already be enabled (it's a RO bit). */
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pci_read_config_word(dev, PCI_COMMAND, &tmpword);
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if (!(tmpword & PCI_COMMAND_IO)) {
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debug("%s: device IO not enabled\n", __func__);
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return -1;
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}
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/* Header Type must be normal (bits 6-0 only; see spec.) */
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte);
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if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
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debug("%s: invalid Header type\n", __func__);
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return -1;
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}
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/* Base Class must be a bridge device */
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pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte);
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if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
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debug("%s: invalid class\n", __func__);
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return -1;
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}
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/* Sub Class must be ISA */
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pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte);
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if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
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debug("%s: invalid subclass\n", __func__);
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return -1;
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}
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/* Programming Interface must be 0x00 (no others exist) */
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pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte);
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if (tmpbyte != 0x00) {
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debug("%s: invalid interface type\n", __func__);
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return -1;
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}
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/*
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* GPIOBASE moved to its current offset with ICH6, but prior to
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* that it was unused (or undocumented). Check that it looks
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* okay: not all ones or zeros, and mapped to I/O space (bit 0).
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*/
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pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong);
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if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
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!(tmplong & 0x00000001)) {
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debug("%s: unexpected GPIOBASE value\n", __func__);
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return -1;
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}
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/*
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* Okay, I guess we're looking at the right device. The actual
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* GPIO registers are in the PCI device's I/O space, starting
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* at the offset that we just read. Bit 0 indicates that it's
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* an I/O address, not a memory address, so mask that off.
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*/
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gpiobase = tmplong & 0xfffffffe;
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/* Finally. These are the droids we're looking for. */
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found_it_once = 1;
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return 0;
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}
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int gpio_request(unsigned gpio, const char *label /* UNUSED */)
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{
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u32 tmplong;
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/* Are we doing it wrong? */
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if (gpio > GPIO_MAX || in_use[gpio]) {
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debug("%s: gpio unavailable\n", __func__);
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return -1;
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}
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/* Is the hardware ready? */
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if (gpio_init()) {
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debug("%s: gpio_init failed\n", __func__);
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return -1;
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}
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/*
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* Make sure that the GPIO pin we want isn't already in use for some
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* built-in hardware function. We have to check this for every
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* requested pin.
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*/
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tmplong = inl(gpiobase + OFS_GPIO_USE_SEL);
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if (!(tmplong & (1UL << gpio))) {
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debug("%s: reserved for internal use\n", __func__);
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return -1;
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}
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in_use[gpio] = 1;
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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if (gpio > GPIO_MAX || !in_use[gpio]) {
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debug("%s: gpio unavailable\n", __func__);
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return -1;
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}
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in_use[gpio] = 0;
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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u32 tmplong;
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if (gpio > GPIO_MAX || !in_use[gpio]) {
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debug("%s: gpio unavailable\n", __func__);
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return -1;
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}
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tmplong = inl(gpiobase + OFS_GPIO_IO_SEL);
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tmplong |= (1UL << gpio);
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outl(gpiobase + OFS_GPIO_IO_SEL, tmplong);
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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u32 tmplong;
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if (gpio > GPIO_MAX || !in_use[gpio]) {
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debug("%s: gpio unavailable\n", __func__);
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return -1;
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}
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tmplong = inl(gpiobase + OFS_GPIO_IO_SEL);
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tmplong &= ~(1UL << gpio);
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outl(gpiobase + OFS_GPIO_IO_SEL, tmplong);
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return 0;
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}
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int gpio_get_value(unsigned gpio)
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{
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u32 tmplong;
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if (gpio > GPIO_MAX || !in_use[gpio]) {
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debug("%s: gpio unavailable\n", __func__);
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return -1;
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}
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tmplong = inl(gpiobase + OFS_GP_LVL);
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return (tmplong & (1UL << gpio)) ? 1 : 0;
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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u32 tmplong;
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if (gpio > GPIO_MAX || !in_use[gpio]) {
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debug("%s: gpio unavailable\n", __func__);
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return -1;
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}
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tmplong = inl(gpiobase + OFS_GP_LVL);
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if (value)
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tmplong |= (1UL << gpio);
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else
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tmplong &= ~(1UL << gpio);
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outl(gpiobase + OFS_GP_LVL, tmplong);
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return 0;
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}
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123
include/pci.h
123
include/pci.h
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@ -67,7 +67,130 @@
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CLASS_CODE 0x0b /* Device class code */
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#define PCI_CLASS_CODE_TOO_OLD 0x00
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#define PCI_CLASS_CODE_STORAGE 0x01
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#define PCI_CLASS_CODE_NETWORK 0x02
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#define PCI_CLASS_CODE_DISPLAY 0x03
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#define PCI_CLASS_CODE_MULTIMEDIA 0x04
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#define PCI_CLASS_CODE_MEMORY 0x05
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#define PCI_CLASS_CODE_BRIDGE 0x06
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#define PCI_CLASS_CODE_COMM 0x07
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#define PCI_CLASS_CODE_PERIPHERAL 0x08
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#define PCI_CLASS_CODE_INPUT 0x09
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#define PCI_CLASS_CODE_DOCKING 0x0A
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#define PCI_CLASS_CODE_PROCESSOR 0x0B
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#define PCI_CLASS_CODE_SERIAL 0x0C
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#define PCI_CLASS_CODE_WIRELESS 0x0D
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#define PCI_CLASS_CODE_I2O 0x0E
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#define PCI_CLASS_CODE_SATELLITE 0x0F
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#define PCI_CLASS_CODE_CRYPTO 0x10
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#define PCI_CLASS_CODE_DATA 0x11
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/* Base Class 0x12 - 0xFE is reserved */
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#define PCI_CLASS_CODE_OTHER 0xFF
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#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
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#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
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#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
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#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
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#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
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#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
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#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
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#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
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#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
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#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
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#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
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#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
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#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
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#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
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#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
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#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
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#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
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#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
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#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
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#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
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#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
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#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
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#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
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#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
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#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
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#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
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#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
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#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
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#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
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#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
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#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
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#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
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#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
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#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
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#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
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#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
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#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
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#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
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#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
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#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
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#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
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#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
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#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
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#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
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#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
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#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
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#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
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#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
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#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
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#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
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#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
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#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
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#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
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#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
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#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
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#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
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#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
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#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
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#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
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#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
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#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
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#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
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#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
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#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
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#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
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#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
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#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
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#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
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#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
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#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
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#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
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#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
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#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
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#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
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#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
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#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
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#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
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#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
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#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
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#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
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#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
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#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
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#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
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#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
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#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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Loading…
Reference in New Issue