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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

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This commit is contained in:
Wolfgang Denk 2008-05-03 20:46:40 +02:00
commit 56bb37e4b9
2 changed files with 12 additions and 7 deletions
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7
cpu/ppc4xx/44x_spd_ddr2.c
View file

@ -1,7 +1,10 @@
/* /*
* cpu/ppc4xx/44x_spd_ddr2.c * cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those are 440SP/SPe. * DDR2 controller (non Denali Core). Those currently are:
*
* 405: 405EX
* 440/460: 440SP/440SPe/460EX/460GT
* *
* (C) Copyright 2007-2008 * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de. * Stefan Roese, DENX Software Engineering, sr@denx.de.
@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,
if (num_banks == 4) if (num_banks == 4)
ind = 0; ind = 0;
else else
ind = 5; ind = 5 << 8;
switch (num_col_addr) { switch (num_col_addr) {
case 0x08: case 0x08:
mode |= (SDRAM_BXCF_M_AM_0 + ind); mode |= (SDRAM_BXCF_M_AM_0 + ind);

12
nand_spl/board/amcc/canyonlands/ddr2_fixed.c
View file

@ -49,20 +49,21 @@ long int initdram(int board_type)
* enabled. This will only work for the same memory * enabled. This will only work for the same memory
* configuration as used here: * configuration as used here:
* *
* Crucial CT6464AC53E.4FE - 512MB SO-DIMM * Crucial CT6464AC667.8FB - 512MB SO-DIMM
* *
*/ */
mtsdram(SDRAM_MCOPT2, 0x00000000); mtsdram(SDRAM_MCOPT2, 0x00000000);
mtsdram(SDRAM_MCOPT1, 0x05322000); mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_MODT0, 0x01000000); mtsdram(SDRAM_MODT0, 0x01000000);
mtsdram(SDRAM_CODT, 0x00800021); mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_WRDTR, 0x82000823); mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000); mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201); mtsdram(SDRAM_MB0CF, 0x00000201);
mtsdram(SDRAM_MB1CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000); mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000); mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243); mtsdram(SDRAM_SDTR2, 0x42103243);
mtsdram(SDRAM_SDTR3, 0x0A0D0D1A); mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
mtsdram(SDRAM_MMODE, 0x00000632); mtsdram(SDRAM_MMODE, 0x00000632);
mtsdram(SDRAM_MEMODE, 0x00000040); mtsdram(SDRAM_MEMODE, 0x00000040);
mtsdram(SDRAM_INITPLR0, 0xB5380000); mtsdram(SDRAM_INITPLR0, 0xB5380000);
@ -86,7 +87,8 @@ long int initdram(int board_type)
wait_init_complete(); wait_init_complete();
mtdcr(SDRAM_R0BAS, 0x0000F000); /* MQ0_B0BAS */ mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
mtsdram(SDRAM_RDCC, 0x40000000); mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038); mtsdram(SDRAM_RQDC, 0x80000038);