ARM: rmobile: Add support R-Car Generation 3

This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu 2016-04-01 03:51:34 +09:00
parent a7da6f8c3d
commit 581183def6
5 changed files with 198 additions and 1 deletions

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@ -8,8 +8,13 @@ config RCAR_32
bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
select CPU_V7
config RCAR_GEN3
bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
select ARM64
endchoice
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
endif

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@ -0,0 +1,12 @@
if RCAR_GEN3
choice
prompt "Renesus ARM64 SoCs board select"
optional
endchoice
config SYS_SOC
default "rmobile"
endif

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@ -0,0 +1,100 @@
/*
* ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
#define __ASM_ARCH_RCAR_GEN3_BASE_H
/*
* R-Car (R8A7750) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xEE220200
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
/* SCIF */
#define SCIF0_BASE 0xE6E60000
#define SCIF1_BASE 0xE6E68000
#define SCIF2_BASE 0xE6E88000
#define SCIF3_BASE 0xE6C50000
#define SCIF4_BASE 0xE6C40000
#define SCIF5_BASE 0xE6F30000
/* Module stop status register */
#define MSTPSR0 0xE6150030
#define MSTPSR1 0xE6150038
#define MSTPSR2 0xE6150040
#define MSTPSR3 0xE6150048
#define MSTPSR4 0xE615004C
#define MSTPSR5 0xE615003C
#define MSTPSR6 0xE61501C0
#define MSTPSR7 0xE61501C4
#define MSTPSR8 0xE61509A0
#define MSTPSR9 0xE61509A4
#define MSTPSR10 0xE61509A8
#define MSTPSR11 0xE61509AC
/* Realtime module stop control register */
#define RMSTPCR0 0xE6150110
#define RMSTPCR1 0xE6150114
#define RMSTPCR2 0xE6150118
#define RMSTPCR3 0xE615011C
#define RMSTPCR4 0xE6150120
#define RMSTPCR5 0xE6150124
#define RMSTPCR6 0xE6150128
#define RMSTPCR7 0xE615012C
#define RMSTPCR8 0xE6150980
#define RMSTPCR9 0xE6150984
#define RMSTPCR10 0xE6150988
#define RMSTPCR11 0xE615098C
/* System module stop control register */
#define SMSTPCR0 0xE6150130
#define SMSTPCR1 0xE6150134
#define SMSTPCR2 0xE6150138
#define SMSTPCR3 0xE615013C
#define SMSTPCR4 0xE6150140
#define SMSTPCR5 0xE6150144
#define SMSTPCR6 0xE6150148
#define SMSTPCR7 0xE615014C
#define SMSTPCR8 0xE6150990
#define SMSTPCR9 0xE6150994
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
/* PFC */
#define PFC_PUEN6 0xE6060418
#define PUEN_USB1_OVC (1 << 2)
#define PUEN_USB1_PWEN (1 << 1)
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct rcar_rwdt {
u32 rwtcnt;
u32 rwtcsra;
u32 rwtcsrb;
};
/* SWDT */
struct rcar_swdt {
u32 swtcnt;
u32 swtcsra;
u32 swtcsrb;
};
#endif
#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */

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@ -0,0 +1,76 @@
/*
* arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
* This file is lowlevel initialize routine.
*
* (C) Copyright 2015 Renesas Electronics Corporation
*
* This file is based on the arch/arm/cpu/armv8/start.S
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
#ifndef CONFIG_ARMV8_MULTIENTRY
/*
* For single-entry systems the lowlevel init is very simple.
*/
ldr x0, =GICD_BASE
bl gic_init_secure
#else /* CONFIG_ARMV8_MULTIENTRY is set */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
bl gic_init_secure
1:
#if defined(CONFIG_GICV3)
ldr x0, =GICR_BASE
bl gic_init_secure_percpu
#elif defined(CONFIG_GICV2)
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
#endif
branch_if_master x0, x1, 2f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
#ifdef CONFIG_GICV2
ldr x0, =GICC_BASE
#endif
bl gic_wait_for_interrupt
#endif
/*
* All slaves will enter EL2 and optionally EL1.
*/
bl armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl armv8_switch_to_el1
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
bl s_init
2:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)

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@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -29,7 +30,10 @@ static struct mstp_ctl mstptbl[] = {
RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
/* No MSTP6 */
#ifdef CONFIG_RCAR_GEN3
{ SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
#endif
{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,