Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

arch/microblaze/cpu/cache.c

@@ -61,12 +61,7 @@ void	dcache_enable (void) {
 
 void	dcache_disable(void) {
 #ifdef XILINX_USE_DCACHE
-#ifdef XILINX_DCACHE_BYTE_SIZE
 	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#else
-#warning please rebuild BSPs and update configuration
-	flush_cache(0, 32768);
-#endif
 #endif
 	MSRCLR(0x80);
 }

arch/microblaze/cpu/start.S

@@ -132,6 +132,12 @@ _start:
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
 
+	/* Flush cache before enable cache */
+	addik	r5, r0, 0
+	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush:	bralid r15, flush_cache
+	nop
+
 	/* enable instruction and data cache */
 	mfs	r12, rmsr
 	ori	r12, r12, 0xa0

arch/microblaze/cpu/u-boot.lds

@@ -45,7 +45,9 @@ SECTIONS
 	.data ALIGN(0x4):
 	{
 		__data_start = .;
+#ifdef CONFIG_OF_EMBED
 		dts/libdts.o (.data)
+#endif
 		*(.data)
 		__data_end = .;
 	}

arch/microblaze/include/asm/bitops.h

@@ -319,7 +319,8 @@ extern __inline__ int ext2_test_bit(int nr, const volatile void * addr)
 #define ext2_find_first_zero_bit(addr, size) \
 	ext2_find_next_zero_bit((addr), (size), 0)
 
-extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+static inline unsigned long ext2_find_next_zero_bit(void *addr,
+				unsigned long size, unsigned long offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;

arch/microblaze/include/asm/byteorder.h

@@ -20,29 +20,6 @@
 
 #ifdef __GNUC__
 
-/* This is effectively a dupe of the arch-independent byteswap
-   code in include/linux/byteorder/swab.h, however we force a cast
-   of the result up to 32 bits.  This in turn forces the compiler
-   to explicitly clear the high 16 bits, which it wasn't doing otherwise.
-
-   I think this is a symptom of a bug in mb-gcc.  JW 20040303
-*/
-
-
-static __inline__ __u16 ___arch__swab16 (__u16 half_word)
-{
-	/* 32 bit temp to cast result, forcing clearing of high word */
-	__u32 temp;
-
-	temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8);
-
-	return (__u16) temp;
-}
-
-#define __arch__swab16(x) ___arch__swab16(x)
-
-/* Microblaze has no arch-specific endian conversion insns */
-
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
 #  define __BYTEORDER_HAS_U64__
 #  define __SWAB_64_THRU_32__

arch/microblaze/include/asm/posix_types.h

@@ -16,9 +16,6 @@
 #ifndef __MICROBLAZE_POSIX_TYPES_H__
 #define __MICROBLAZE_POSIX_TYPES_H__
 
-#include <asm/bitops.h>
-
-
 typedef unsigned int	__kernel_dev_t;
 typedef unsigned long	__kernel_ino_t;
 typedef unsigned long long __kernel_ino64_t;

arch/microblaze/lib/bootm.c

@@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 #endif
 
 #ifdef XILINX_USE_DCACHE
-#ifdef XILINX_DCACHE_BYTE_SIZE
 	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#else
-#warning please rebuild BSPs and update configuration
-	flush_cache(0, 32768);
-#endif
 #endif
 	/*
 	 * Linux Kernel Parameters (passing device tree):

include/configs/microblaze-generic.h

@@ -287,6 +287,10 @@
 # undef CONFIG_DCACHE
 #endif
 
+#ifndef XILINX_DCACHE_BYTE_SIZE
+#define XILINX_DCACHE_BYTE_SIZE	32768
+#endif
+
 /*
  * BOOTP options
  */