rockchip: clk: rk3399: update driver for spl
Add ddr clock setting, add rockchip_get_pmucru API, and enable of-platdata support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass <sjg@chromium.org>
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fa72de1045
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5ae2fd9724
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@ -63,6 +63,13 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
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*/
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*/
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void *rockchip_get_cru(void);
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void *rockchip_get_cru(void);
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/**
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* rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
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*
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* @return pointer to registers, or -ve error on error
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*/
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void *rockchip_get_pmucru(void);
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struct rk3288_cru;
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struct rk3288_cru;
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struct rk3288_grf;
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struct rk3288_grf;
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@ -15,6 +15,11 @@ struct rk3399_clk_priv {
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ulong rate;
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ulong rate;
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};
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};
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struct rk3399_pmuclk_priv {
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struct rk3399_pmucru *pmucru;
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ulong rate;
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};
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struct rk3399_pmucru {
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struct rk3399_pmucru {
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u32 ppll_con[6];
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u32 ppll_con[6];
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u32 reserved[0x1a];
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u32 reserved[0x1a];
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@ -31,3 +31,24 @@ void *rockchip_get_cru(void)
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return priv->cru;
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return priv->cru;
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}
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}
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static int rockchip_get_pmucruclk(struct udevice **devp)
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{
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
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}
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void *rockchip_get_pmucru(void)
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{
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struct rk3399_pmuclk_priv *priv;
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struct udevice *dev;
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int ret;
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ret = rockchip_get_pmucruclk(&dev);
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if (ret)
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return ERR_PTR(ret);
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priv = dev_get_priv(dev);
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return priv->pmucru;
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}
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@ -7,7 +7,9 @@
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#include <common.h>
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#include <common.h>
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#include <clk-uclass.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <errno.h>
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#include <mapmem.h>
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#include <syscon.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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@ -18,10 +20,16 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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struct rk3399_pmuclk_priv {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_pmucru *pmucru;
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struct rk3399_clk_plat {
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struct dtd_rockchip_rk3399_cru dtd;
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};
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};
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struct rk3399_pmuclk_plat {
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struct dtd_rockchip_rk3399_pmucru dtd;
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};
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#endif
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struct pll_div {
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struct pll_div {
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u32 refdiv;
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u32 refdiv;
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u32 fbdiv;
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u32 fbdiv;
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@ -381,6 +389,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
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return 0;
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return 0;
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}
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}
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rk3399_cru *cru)
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static void rkclk_init(struct rk3399_cru *cru)
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{
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{
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u32 aclk_div;
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u32 aclk_div;
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@ -456,6 +465,7 @@ static void rkclk_init(struct rk3399_cru *cru)
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
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HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
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}
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}
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#endif
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void rk3399_configure_cpu(struct rk3399_cru *cru,
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void rk3399_configure_cpu(struct rk3399_cru *cru,
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enum apll_l_frequencies apll_l_freq)
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enum apll_l_frequencies apll_l_freq)
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@ -709,6 +719,44 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
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return rk3399_mmc_get_clk(cru, clk_id);
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return rk3399_mmc_get_clk(cru, clk_id);
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}
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}
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#define PMUSGRF_DDR_RGN_CON16 0xff330040
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static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
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ulong set_rate)
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{
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struct pll_div dpll_cfg;
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/* IC ECO bug, need to set this register */
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writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
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/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
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switch (set_rate) {
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case 200*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
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break;
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case 300*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
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break;
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case 666*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
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break;
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case 800*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
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break;
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case 933*MHz:
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dpll_cfg = (struct pll_div)
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{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
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break;
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default:
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error("Unsupported SDRAM frequency!,%ld\n", set_rate);
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}
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rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
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return set_rate;
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}
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static ulong rk3399_clk_get_rate(struct clk *clk)
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static ulong rk3399_clk_get_rate(struct clk *clk)
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{
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{
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struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
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struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
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@ -763,6 +811,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
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case DCLK_VOP1:
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case DCLK_VOP1:
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ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
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ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
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break;
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break;
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case SCLK_DDRCLK:
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ret = rk3399_ddr_set_clk(priv->cru, rate);
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break;
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default:
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default:
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return -ENOENT;
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return -ENOENT;
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}
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}
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@ -777,19 +828,26 @@ static struct clk_ops rk3399_clk_ops = {
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static int rk3399_clk_probe(struct udevice *dev)
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static int rk3399_clk_probe(struct udevice *dev)
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{
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{
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#ifdef CONFIG_SPL_BUILD
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struct rk3399_clk_priv *priv = dev_get_priv(dev);
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struct rk3399_clk_priv *priv = dev_get_priv(dev);
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rkclk_init(priv->cru);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_clk_plat *plat = dev_get_platdata(dev);
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priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
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#endif
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rkclk_init(priv->cru);
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#endif
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return 0;
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return 0;
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}
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}
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static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
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static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
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{
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_clk_priv *priv = dev_get_priv(dev);
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struct rk3399_clk_priv *priv = dev_get_priv(dev);
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priv->cru = (struct rk3399_cru *)dev_get_addr(dev);
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priv->cru = (struct rk3399_cru *)dev_get_addr(dev);
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#endif
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return 0;
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return 0;
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}
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}
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@ -811,7 +869,7 @@ static const struct udevice_id rk3399_clk_ids[] = {
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};
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};
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U_BOOT_DRIVER(clk_rk3399) = {
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U_BOOT_DRIVER(clk_rk3399) = {
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.name = "clk_rk3399",
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.name = "rockchip_rk3399_cru",
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.id = UCLASS_CLK,
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.id = UCLASS_CLK,
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.of_match = rk3399_clk_ids,
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.of_match = rk3399_clk_ids,
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.priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
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.priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
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@ -819,6 +877,9 @@ U_BOOT_DRIVER(clk_rk3399) = {
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.ops = &rk3399_clk_ops,
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.ops = &rk3399_clk_ops,
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.bind = rk3399_clk_bind,
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.bind = rk3399_clk_bind,
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.probe = rk3399_clk_probe,
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.probe = rk3399_clk_probe,
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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.platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
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#endif
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};
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};
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static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
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static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
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@ -930,6 +991,7 @@ static struct clk_ops rk3399_pmuclk_ops = {
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.set_rate = rk3399_pmuclk_set_rate,
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.set_rate = rk3399_pmuclk_set_rate,
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};
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};
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#ifndef CONFIG_SPL_BUILD
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static void pmuclk_init(struct rk3399_pmucru *pmucru)
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static void pmuclk_init(struct rk3399_pmucru *pmucru)
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{
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{
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u32 pclk_div;
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u32 pclk_div;
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@ -939,27 +1001,35 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru)
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/* configure pmu pclk */
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/* configure pmu pclk */
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pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
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pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
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assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f);
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rk_clrsetreg(&pmucru->pmucru_clksel[0],
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rk_clrsetreg(&pmucru->pmucru_clksel[0],
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PMU_PCLK_DIV_CON_MASK,
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PMU_PCLK_DIV_CON_MASK,
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pclk_div << PMU_PCLK_DIV_CON_SHIFT);
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pclk_div << PMU_PCLK_DIV_CON_SHIFT);
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}
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}
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#endif
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static int rk3399_pmuclk_probe(struct udevice *dev)
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static int rk3399_pmuclk_probe(struct udevice *dev)
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{
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{
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struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
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struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
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pmuclk_init(priv->pmucru);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
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priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
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#endif
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#ifndef CONFIG_SPL_BUILD
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pmuclk_init(priv->pmucru);
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#endif
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return 0;
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return 0;
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}
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}
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static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
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static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
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{
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
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struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
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priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev);
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priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev);
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#endif
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return 0;
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return 0;
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}
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}
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@ -969,11 +1039,14 @@ static const struct udevice_id rk3399_pmuclk_ids[] = {
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};
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};
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U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
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U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
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.name = "pmuclk_rk3399",
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.name = "rockchip_rk3399_pmucru",
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.id = UCLASS_CLK,
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.id = UCLASS_CLK,
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.of_match = rk3399_pmuclk_ids,
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.of_match = rk3399_pmuclk_ids,
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.priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
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.priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
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.ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
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.ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
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.ops = &rk3399_pmuclk_ops,
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.ops = &rk3399_pmuclk_ops,
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.probe = rk3399_pmuclk_probe,
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.probe = rk3399_pmuclk_probe,
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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.platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
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#endif
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};
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};
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#define SCLK_DPHY_RX0_CFG 165
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#define SCLK_DPHY_RX0_CFG 165
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#define SCLK_RMII_SRC 166
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#define SCLK_RMII_SRC 166
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#define SCLK_PCIEPHY_REF100M 167
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#define SCLK_PCIEPHY_REF100M 167
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#define SCLK_USBPHY0_480M_SRC 168
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#define SCLK_USBPHY1_480M_SRC 169
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#define SCLK_DDRCLK 170
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#define SCLK_TESTOUT2 171
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#define DCLK_VOP0 180
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#define DCLK_VOP0 180
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#define DCLK_VOP1 181
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#define DCLK_VOP1 181
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#define SRST_P_SPI0 214
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#define SRST_P_SPI0 214
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#define SRST_P_SPI1 215
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#define SRST_P_SPI1 215
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#define SRST_P_SPI2 216
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#define SRST_P_SPI2 216
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#define SRST_P_SPI3 217
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#define SRST_P_SPI4 217
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#define SRST_P_SPI4 218
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#define SRST_P_SPI5 218
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#define SRST_SPI0 219
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#define SRST_SPI0 219
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#define SRST_SPI1 220
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#define SRST_SPI1 220
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#define SRST_SPI2 221
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#define SRST_SPI2 221
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#define SRST_SPI3 222
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#define SRST_SPI4 222
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#define SRST_SPI4 223
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#define SRST_SPI5 223
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/* cru_softrst_con14 */
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/* cru_softrst_con14 */
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#define SRST_I2S0_8CH 224
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#define SRST_I2S0_8CH 224
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@ -717,8 +721,8 @@
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#define SRST_H_CM0S_NOC 3
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#define SRST_H_CM0S_NOC 3
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#define SRST_DBG_CM0S 4
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#define SRST_DBG_CM0S 4
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#define SRST_PO_CM0S 5
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#define SRST_PO_CM0S 5
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#define SRST_P_SPI6 6
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#define SRST_P_SPI3 6
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#define SRST_SPI6 7
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#define SRST_SPI3 7
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#define SRST_P_TIMER_0_1 8
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#define SRST_P_TIMER_0_1 8
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||||||
#define SRST_P_TIMER_0 9
|
#define SRST_P_TIMER_0 9
|
||||||
#define SRST_P_TIMER_1 10
|
#define SRST_P_TIMER_1 10
|
||||||
|
|
Loading…
Reference in New Issue