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mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance 

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:19 -05:00 committed by Kim Phillips
parent 8d85808fa1
commit 5afe9722b0
1 changed files with 149 additions and 100 deletions
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155
include/configs/MPC837XERDB.h
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@ -239,7 +239,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* /*
* Local Bus Configuration & Clock Setup * Local Bus Configuration & Clock Setup
@ -261,12 +262,13 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ /* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ #define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
| OR_GPCM_XACS \ | OR_GPCM_XACS \
| OR_GPCM_SCY_9 \ | OR_GPCM_SCY_9 \
@ -285,18 +287,18 @@
* NAND Flash on the Local Bus * NAND Flash on the Local Bus
*/ */
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
(2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ | (2 << BR_DECC_SHIFT) /* Use HW ECC */ \
BR_PS_8 | /* Port Size = 8 bit */ \ | BR_PS_8 | /* 8 bit Port */ \
BR_MS_FCM | /* MSEL = FCM */ \ | BR_MS_FCM | /* MSEL = FCM */ \
BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
OR_FCM_CSCT | \ | OR_FCM_CSCT \
OR_FCM_CST | \ | OR_FCM_CST \
OR_FCM_CHT | \ | OR_FCM_CHT \
OR_FCM_SCY_1 | \ | OR_FCM_SCY_1 \
OR_FCM_TRLX | \ | OR_FCM_TRLX \
OR_FCM_EHTR) | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
@ -308,7 +310,8 @@
#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */ #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */ /* Access Base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
#endif #endif
@ -465,7 +468,8 @@
*/ */
#ifndef CONFIG_SYS_RAMBOOT #ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_SIZE 0x4000
#else #else
@ -537,9 +541,11 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ /* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/* /*
@ -553,8 +559,8 @@
* Core HID Setup * Core HID Setup
*/ */
#define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
HID0_ENABLE_INSTRUCTION_CACHE) | HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_SYS_HID2 HID2_HBE
/* /*
@ -567,53 +573,93 @@
#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
| BATU_BL_8M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* L2 Switch: cache-inhibit and guarded */ /* L2 Switch: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ /* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | BATL_PP_10 \
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | BATL_MEMCOHERENCE)
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ /* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
/* PCI MEM space: cacheable */ /* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */ /* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else #else
@ -639,16 +685,18 @@
#define CONFIG_HAS_FSL_DR_USB #define CONFIG_HAS_FSL_DR_USB
#define CONFIG_NETDEV eth1 #define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME mpc837x_rdb #define CONFIG_HOSTNAME mpc837x_rdb
#define CONFIG_ROOTPATH "/nfsroot" #define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
#define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ /* U-Boot image on TFTP server */
#define CONFIG_FDTFILE mpc8379_rdb.dtb #define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ /* default location for tftp and bootm */
#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
@ -656,8 +704,8 @@
#define MK_STR(x) XMK_STR(x) #define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "netdev=" CONFIG_NETDEV "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \ "tftpflash=tftp $loadaddr $uboot;" \
"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
@ -665,14 +713,15 @@
"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=780000\0" \ "fdtaddr=780000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \ "ramdiskaddr=1000000\0" \
"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
"console=ttyS0\0" \ "console=ttyS0\0" \
"setbootargs=setenv bootargs " \ "setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
"$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \