SPEAr : Network driver support added
Designware network driver support added. This is a Synopsys ethernet controller Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Vipin KUMAR
Ben Warren
parent
c19a20d5bd
commit
5b1b1883ff
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@ -0,0 +1,25 @@
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This driver supports Designware Ethernet Controller provided by Synopsis.
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The driver is enabled by CONFIG_DESIGNWARE_ETH.
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The driver has been developed and tested on SPEAr platforms. By default, the
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MDIO interface works at 100/Full. #defining the below options in board
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configuration file changes this behavior.
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Call an subroutine from respective board/.../board.c
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designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
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The various options suported by the driver are
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1. CONFIG_DW_ALTDESCRIPTOR
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Define this to use the Alternate/Enhanced Descriptor configurations.
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1. CONFIG_DW_AUTONEG
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Define this to autonegotiate with the host before proceeding with mac
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level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
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and CONFIG_DW_DUPLEXHALF.
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2. CONFIG_DW_SPEED10M
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Define this to change the default behavior from 100Mbps to 10Mbps.
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3. CONFIG_DW_DUPLEXHALF
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Define this to change the default behavior from Full Duplex to Half.
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4. CONFIG_DW_SEARCH_PHY
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Define this to search the phy address. This would overwrite the value
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passed as 3rd arg from designware_initialize routine.
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@ -34,6 +34,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
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COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
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COBJS-$(CONFIG_CS8900) += cs8900.o
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COBJS-$(CONFIG_TULIP) += dc2114x.o
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COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
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COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
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COBJS-$(CONFIG_DNET) += dnet.o
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COBJS-$(CONFIG_E1000) += e1000.o
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@ -0,0 +1,531 @@
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/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Designware ethernet IP driver for u-boot
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include "designware.h"
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static void tx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
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char *txbuffs = &priv->txbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
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DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
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DESC_TXSTS_TXCHECKINSCTRL | \
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DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
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desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
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desc_p->dmamac_cntl = 0;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
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#else
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desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
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desc_p->txrx_status = 0;
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#endif
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
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}
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static void rx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
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char *rxbuffs = &priv->rxbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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desc_p->dmamac_cntl =
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(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
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DESC_RXCTRL_RXCHAIN;
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desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
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}
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static void descs_init(struct eth_device *dev)
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{
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tx_descs_init(dev);
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rx_descs_init(dev);
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}
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static int mac_reset(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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int timeout = CONFIG_MACRESET_TIMEOUT;
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writel(DMAMAC_SRST, &dma_p->busmode);
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writel(MII_PORTSELECT, &mac_p->conf);
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do {
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if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
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return 0;
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udelay(1000);
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} while (timeout--);
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return -1;
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}
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static int dw_write_hwaddr(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 macid_lo, macid_hi;
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u8 *mac_id = &dev->enetaddr[0];
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macid_lo = mac_id[0] + (mac_id[1] << 8) + \
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(mac_id[2] << 16) + (mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, &mac_p->macaddr0hi);
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writel(macid_lo, &mac_p->macaddr0lo);
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return 0;
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}
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static int dw_eth_init(struct eth_device *dev, bd_t *bis)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 conf;
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/* Reset ethernet hardware */
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if (mac_reset(dev) < 0)
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return -1;
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writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
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&dma_p->busmode);
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writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
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writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
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conf = FRAMEBURSTENABLE | DISABLERXOWN;
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if (priv->speed != SPEED_1000M)
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conf |= MII_PORTSELECT;
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if (priv->duplex == FULL_DUPLEX)
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conf |= FULLDPLXMODE;
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writel(conf, &mac_p->conf);
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descs_init(dev);
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/*
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* Start/Enable xfer at dma as well as mac level
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*/
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writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
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writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
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writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
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writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
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return 0;
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}
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static int dw_eth_send(struct eth_device *dev, volatile void *packet,
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int length)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 desc_num = priv->tx_currdescnum;
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struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
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/* Check if the descriptor is owned by CPU */
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if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
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printf("CPU not owner of tx frame\n");
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return -1;
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}
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memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
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desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
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desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
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#else
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desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
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DESC_TXCTRL_TXFIRST;
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desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
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#endif
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_TX_DESCR_NUM)
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desc_num = 0;
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priv->tx_currdescnum = desc_num;
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/* Start the transmission */
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writel(POLL_DATA, &dma_p->txpolldemand);
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return 0;
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}
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static int dw_eth_recv(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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u32 desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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u32 status = desc_p->txrx_status;
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int length = 0;
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/* Check if the owner is the CPU */
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if (!(status & DESC_RXSTS_OWNBYDMA)) {
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length = (status & DESC_RXSTS_FRMLENMSK) >> \
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DESC_RXSTS_FRMLENSHFT;
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NetReceive(desc_p->dmamac_addr, length);
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/*
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* Make the current descriptor valid again and go to
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* the next one
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*/
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desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_RX_DESCR_NUM)
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desc_num = 0;
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}
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priv->rx_currdescnum = desc_num;
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return length;
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}
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static void dw_eth_halt(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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mac_reset(dev);
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priv->tx_currdescnum = priv->rx_currdescnum = 0;
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}
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static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 miiaddr;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK);
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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do {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
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*val = readl(&mac_p->miidata);
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return 0;
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}
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udelay(1000);
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} while (timeout--);
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return -1;
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}
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static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 miiaddr;
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int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
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u16 value;
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writel(val, &mac_p->miidata);
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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do {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY))
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ret = 0;
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udelay(1000);
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} while (timeout--);
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/* Needed as a fix for ST-Phy */
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eth_mdio_read(dev, addr, reg, &value);
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return ret;
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}
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#if defined(CONFIG_DW_SEARCH_PHY)
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static int find_phy(struct eth_device *dev)
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{
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int phy_addr = 0;
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u16 ctrl, oldctrl;
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do {
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eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
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oldctrl = ctrl & PHY_BMCR_AUTON;
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ctrl ^= PHY_BMCR_AUTON;
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eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
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eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
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ctrl &= PHY_BMCR_AUTON;
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if (ctrl == oldctrl) {
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phy_addr++;
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} else {
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ctrl ^= PHY_BMCR_AUTON;
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eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
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return phy_addr;
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}
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} while (phy_addr < 32);
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return -1;
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}
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#endif
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static int dw_reset_phy(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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u16 ctrl;
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int timeout = CONFIG_PHYRESET_TIMEOUT;
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u32 phy_addr = priv->address;
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eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET);
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do {
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eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
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if (!(ctrl & PHY_BMCR_RESET))
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break;
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udelay(1000);
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} while (timeout--);
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if (timeout < 0)
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return -1;
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#ifdef CONFIG_PHY_RESET_DELAY
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udelay(CONFIG_PHY_RESET_DELAY);
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#endif
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return 0;
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}
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static int configure_phy(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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int phy_addr;
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u16 bmcr, ctrl;
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#if defined(CONFIG_DW_AUTONEG)
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u16 bmsr;
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u32 timeout;
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u16 anlpar, btsr;
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#endif
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#if defined(CONFIG_DW_SEARCH_PHY)
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phy_addr = find_phy(dev);
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if (phy_addr > 0)
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priv->address = phy_addr;
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else
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return -1;
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#endif
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if (dw_reset_phy(dev) < 0)
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return -1;
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#if defined(CONFIG_DW_AUTONEG)
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bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \
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PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
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#else
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bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX;
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#if defined(CONFIG_DW_SPEED10M)
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bmcr &= ~PHY_BMCR_100MB;
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#endif
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#if defined(CONFIG_DW_DUPLEXHALF)
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bmcr &= ~PHY_BMCR_DPLX;
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#endif
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#endif
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if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0)
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return -1;
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/* Read the phy status register and populate priv structure */
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#if defined(CONFIG_DW_AUTONEG)
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timeout = CONFIG_AUTONEG_TIMEOUT;
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do {
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eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr);
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if (bmsr & PHY_BMSR_AUTN_COMP)
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break;
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udelay(1000);
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} while (timeout--);
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eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar);
|
||||
eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr);
|
||||
|
||||
if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
|
||||
priv->speed = SPEED_1000M;
|
||||
if (btsr & PHY_1000BTSR_1000FD)
|
||||
priv->duplex = FULL_DUPLEX;
|
||||
else
|
||||
priv->duplex = HALF_DUPLEX;
|
||||
} else {
|
||||
if (anlpar & PHY_ANLPAR_100)
|
||||
priv->speed = SPEED_100M;
|
||||
else
|
||||
priv->speed = SPEED_10M;
|
||||
|
||||
if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
|
||||
priv->duplex = FULL_DUPLEX;
|
||||
else
|
||||
priv->duplex = HALF_DUPLEX;
|
||||
}
|
||||
#else
|
||||
if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0)
|
||||
return -1;
|
||||
|
||||
if (ctrl & PHY_BMCR_DPLX)
|
||||
priv->duplex = FULL_DUPLEX;
|
||||
else
|
||||
priv->duplex = HALF_DUPLEX;
|
||||
|
||||
if (ctrl & PHY_BMCR_1000_MBPS)
|
||||
priv->speed = SPEED_1000M;
|
||||
else if (ctrl & PHY_BMCR_100_MBPS)
|
||||
priv->speed = SPEED_100M;
|
||||
else
|
||||
priv->speed = SPEED_10M;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MII)
|
||||
static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
|
||||
dev = eth_get_dev_by_name(devname);
|
||||
if (dev)
|
||||
eth_mdio_read(dev, addr, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
|
||||
dev = eth_get_dev_by_name(devname);
|
||||
if (dev)
|
||||
eth_mdio_write(dev, addr, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
struct dw_eth_dev *priv;
|
||||
|
||||
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
|
||||
if (!dev)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* Since the priv structure contains the descriptors which need a strict
|
||||
* buswidth alignment, memalign is used to allocate memory
|
||||
*/
|
||||
priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
|
||||
if (!priv) {
|
||||
free(dev);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memset(dev, 0, sizeof(struct eth_device));
|
||||
memset(priv, 0, sizeof(struct dw_eth_dev));
|
||||
|
||||
sprintf(dev->name, "mii%d", id);
|
||||
dev->iobase = (int)base_addr;
|
||||
dev->priv = priv;
|
||||
|
||||
eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]);
|
||||
|
||||
priv->dev = dev;
|
||||
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
|
||||
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
|
||||
DW_DMA_BASE_OFFSET);
|
||||
priv->address = phy_addr;
|
||||
|
||||
if (mac_reset(dev) < 0)
|
||||
return -1;
|
||||
|
||||
if (configure_phy(dev) < 0) {
|
||||
printf("Phy could not be configured\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
dev->init = dw_eth_init;
|
||||
dev->send = dw_eth_send;
|
||||
dev->recv = dw_eth_recv;
|
||||
dev->halt = dw_eth_halt;
|
||||
dev->write_hwaddr = dw_write_hwaddr;
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
#if defined(CONFIG_MII)
|
||||
miiphy_register(dev->name, dw_mii_read, dw_mii_write);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _DW_ETH_H
|
||||
#define _DW_ETH_H
|
||||
|
||||
#define CONFIG_TX_DESCR_NUM 16
|
||||
#define CONFIG_RX_DESCR_NUM 16
|
||||
#define CONFIG_ETH_BUFSIZE 2048
|
||||
#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
|
||||
#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
|
||||
|
||||
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
|
||||
|
||||
struct eth_mac_regs {
|
||||
u32 conf; /* 0x00 */
|
||||
u32 framefilt; /* 0x04 */
|
||||
u32 hashtablehigh; /* 0x08 */
|
||||
u32 hashtablelow; /* 0x0c */
|
||||
u32 miiaddr; /* 0x10 */
|
||||
u32 miidata; /* 0x14 */
|
||||
u32 flowcontrol; /* 0x18 */
|
||||
u32 vlantag; /* 0x1c */
|
||||
u32 version; /* 0x20 */
|
||||
u8 reserved_1[20];
|
||||
u32 intreg; /* 0x38 */
|
||||
u32 intmask; /* 0x3c */
|
||||
u32 macaddr0hi; /* 0x40 */
|
||||
u32 macaddr0lo; /* 0x44 */
|
||||
};
|
||||
|
||||
/* MAC configuration register definitions */
|
||||
#define FRAMEBURSTENABLE (1 << 21)
|
||||
#define MII_PORTSELECT (1 << 15)
|
||||
#define FES_100 (1 << 14)
|
||||
#define DISABLERXOWN (1 << 13)
|
||||
#define FULLDPLXMODE (1 << 11)
|
||||
#define RXENABLE (1 << 2)
|
||||
#define TXENABLE (1 << 3)
|
||||
|
||||
/* MII address register definitions */
|
||||
#define MII_BUSY (1 << 0)
|
||||
#define MII_WRITE (1 << 1)
|
||||
#define MII_CLKRANGE_60_100M (0)
|
||||
#define MII_CLKRANGE_100_150M (0x4)
|
||||
#define MII_CLKRANGE_20_35M (0x8)
|
||||
#define MII_CLKRANGE_35_60M (0xC)
|
||||
#define MII_CLKRANGE_150_250M (0x10)
|
||||
#define MII_CLKRANGE_250_300M (0x14)
|
||||
|
||||
#define MIIADDRSHIFT (11)
|
||||
#define MIIREGSHIFT (6)
|
||||
#define MII_REGMSK (0x1F << 6)
|
||||
#define MII_ADDRMSK (0x1F << 11)
|
||||
|
||||
|
||||
struct eth_dma_regs {
|
||||
u32 busmode; /* 0x00 */
|
||||
u32 txpolldemand; /* 0x04 */
|
||||
u32 rxpolldemand; /* 0x08 */
|
||||
u32 rxdesclistaddr; /* 0x0c */
|
||||
u32 txdesclistaddr; /* 0x10 */
|
||||
u32 status; /* 0x14 */
|
||||
u32 opmode; /* 0x18 */
|
||||
u32 intenable; /* 0x1c */
|
||||
u8 reserved[40];
|
||||
u32 currhosttxdesc; /* 0x48 */
|
||||
u32 currhostrxdesc; /* 0x4c */
|
||||
u32 currhosttxbuffaddr; /* 0x50 */
|
||||
u32 currhostrxbuffaddr; /* 0x54 */
|
||||
};
|
||||
|
||||
#define DW_DMA_BASE_OFFSET (0x1000)
|
||||
|
||||
/* Bus mode register definitions */
|
||||
#define FIXEDBURST (1 << 16)
|
||||
#define PRIORXTX_41 (3 << 14)
|
||||
#define PRIORXTX_31 (2 << 14)
|
||||
#define PRIORXTX_21 (1 << 14)
|
||||
#define PRIORXTX_11 (0 << 14)
|
||||
#define BURST_1 (1 << 8)
|
||||
#define BURST_2 (2 << 8)
|
||||
#define BURST_4 (4 << 8)
|
||||
#define BURST_8 (8 << 8)
|
||||
#define BURST_16 (16 << 8)
|
||||
#define BURST_32 (32 << 8)
|
||||
#define RXHIGHPRIO (1 << 1)
|
||||
#define DMAMAC_SRST (1 << 0)
|
||||
|
||||
/* Poll demand definitions */
|
||||
#define POLL_DATA (0xFFFFFFFF)
|
||||
|
||||
/* Operation mode definitions */
|
||||
#define STOREFORWARD (1 << 21)
|
||||
#define FLUSHTXFIFO (1 << 20)
|
||||
#define TXSTART (1 << 13)
|
||||
#define TXSECONDFRAME (1 << 2)
|
||||
#define RXSTART (1 << 1)
|
||||
|
||||
/* Descriptior related definitions */
|
||||
#define MAC_MAX_FRAME_SZ (2048)
|
||||
|
||||
struct dmamacdescr {
|
||||
u32 txrx_status;
|
||||
u32 dmamac_cntl;
|
||||
void *dmamac_addr;
|
||||
struct dmamacdescr *dmamac_next;
|
||||
};
|
||||
|
||||
/*
|
||||
* txrx_status definitions
|
||||
*/
|
||||
|
||||
/* tx status bits definitions */
|
||||
#if defined(CONFIG_DW_ALTDESCRIPTOR)
|
||||
|
||||
#define DESC_TXSTS_OWNBYDMA (1 << 31)
|
||||
#define DESC_TXSTS_TXINT (1 << 30)
|
||||
#define DESC_TXSTS_TXLAST (1 << 29)
|
||||
#define DESC_TXSTS_TXFIRST (1 << 28)
|
||||
#define DESC_TXSTS_TXCRCDIS (1 << 27)
|
||||
|
||||
#define DESC_TXSTS_TXPADDIS (1 << 26)
|
||||
#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
|
||||
#define DESC_TXSTS_TXRINGEND (1 << 21)
|
||||
#define DESC_TXSTS_TXCHAIN (1 << 20)
|
||||
#define DESC_TXSTS_MSK (0x1FFFF << 0)
|
||||
|
||||
#else
|
||||
|
||||
#define DESC_TXSTS_OWNBYDMA (1 << 31)
|
||||
#define DESC_TXSTS_MSK (0x1FFFF << 0)
|
||||
|
||||
#endif
|
||||
|
||||
/* rx status bits definitions */
|
||||
#define DESC_RXSTS_OWNBYDMA (1 << 31)
|
||||
#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
|
||||
#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
|
||||
#define DESC_RXSTS_FRMLENSHFT (16)
|
||||
|
||||
#define DESC_RXSTS_ERROR (1 << 15)
|
||||
#define DESC_RXSTS_RXTRUNCATED (1 << 14)
|
||||
#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
|
||||
#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
|
||||
#define DESC_RXSTS_RXDAMAGED (1 << 11)
|
||||
#define DESC_RXSTS_RXVLANTAG (1 << 10)
|
||||
#define DESC_RXSTS_RXFIRST (1 << 9)
|
||||
#define DESC_RXSTS_RXLAST (1 << 8)
|
||||
#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
|
||||
#define DESC_RXSTS_RXCOLLISION (1 << 6)
|
||||
#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
|
||||
#define DESC_RXSTS_RXWATCHDOG (1 << 4)
|
||||
#define DESC_RXSTS_RXMIIERROR (1 << 3)
|
||||
#define DESC_RXSTS_RXDRIBBLING (1 << 2)
|
||||
#define DESC_RXSTS_RXCRC (1 << 1)
|
||||
|
||||
/*
|
||||
* dmamac_cntl definitions
|
||||
*/
|
||||
|
||||
/* tx control bits definitions */
|
||||
#if defined(CONFIG_DW_ALTDESCRIPTOR)
|
||||
|
||||
#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
|
||||
#define DESC_TXCTRL_SIZE1SHFT (0)
|
||||
#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
|
||||
#define DESC_TXCTRL_SIZE2SHFT (16)
|
||||
|
||||
#else
|
||||
|
||||
#define DESC_TXCTRL_TXINT (1 << 31)
|
||||
#define DESC_TXCTRL_TXLAST (1 << 30)
|
||||
#define DESC_TXCTRL_TXFIRST (1 << 29)
|
||||
#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
|
||||
#define DESC_TXCTRL_TXCRCDIS (1 << 26)
|
||||
#define DESC_TXCTRL_TXRINGEND (1 << 25)
|
||||
#define DESC_TXCTRL_TXCHAIN (1 << 24)
|
||||
|
||||
#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
|
||||
#define DESC_TXCTRL_SIZE1SHFT (0)
|
||||
#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
|
||||
#define DESC_TXCTRL_SIZE2SHFT (11)
|
||||
|
||||
#endif
|
||||
|
||||
/* rx control bits definitions */
|
||||
#if defined(CONFIG_DW_ALTDESCRIPTOR)
|
||||
|
||||
#define DESC_RXCTRL_RXINTDIS (1 << 31)
|
||||
#define DESC_RXCTRL_RXRINGEND (1 << 15)
|
||||
#define DESC_RXCTRL_RXCHAIN (1 << 14)
|
||||
|
||||
#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
|
||||
#define DESC_RXCTRL_SIZE1SHFT (0)
|
||||
#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
|
||||
#define DESC_RXCTRL_SIZE2SHFT (16)
|
||||
|
||||
#else
|
||||
|
||||
#define DESC_RXCTRL_RXINTDIS (1 << 31)
|
||||
#define DESC_RXCTRL_RXRINGEND (1 << 25)
|
||||
#define DESC_RXCTRL_RXCHAIN (1 << 24)
|
||||
|
||||
#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
|
||||
#define DESC_RXCTRL_SIZE1SHFT (0)
|
||||
#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
|
||||
#define DESC_RXCTRL_SIZE2SHFT (11)
|
||||
|
||||
#endif
|
||||
|
||||
struct dw_eth_dev {
|
||||
u32 address;
|
||||
u32 speed;
|
||||
u32 duplex;
|
||||
u32 tx_currdescnum;
|
||||
u32 rx_currdescnum;
|
||||
u32 padding;
|
||||
|
||||
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
|
||||
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
|
||||
|
||||
char txbuffs[TX_TOTAL_BUFSIZE];
|
||||
char rxbuffs[RX_TOTAL_BUFSIZE];
|
||||
|
||||
struct eth_mac_regs *mac_regs_p;
|
||||
struct eth_dma_regs *dma_regs_p;
|
||||
|
||||
struct eth_device *dev;
|
||||
} __attribute__ ((aligned(8)));
|
||||
|
||||
/* Speed specific definitions */
|
||||
#define SPEED_10M 1
|
||||
#define SPEED_100M 2
|
||||
#define SPEED_1000M 3
|
||||
|
||||
/* Duplex mode specific definitions */
|
||||
#define HALF_DUPLEX 1
|
||||
#define FULL_DUPLEX 2
|
||||
|
||||
#endif
|
||||
|
|
@ -49,6 +49,7 @@ int bfin_EMAC_initialize(bd_t *bis);
|
|||
int cs8900_initialize(u8 dev_num, int base_addr);
|
||||
int dc21x4x_initialize(bd_t *bis);
|
||||
int davinci_emac_initialize(void);
|
||||
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
|
||||
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
||||
int e1000_initialize(bd_t *bis);
|
||||
int eepro100_initialize(bd_t *bis);
|
||||
|
|
|
|||
Loading…
Reference in New Issue