From fd070d811d47d122b7a08cc417689d952c61f386 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:41 -0400 Subject: [PATCH 01/11] spl/Makefile: Add drivers/power/pmic/libpmic to CONFIG_SPL_POWER_SUPPORT We may need to access the PMIC code in SPL, when we have power set. Signed-off-by: Tom Rini --- spl/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/spl/Makefile b/spl/Makefile index 174d0a7fc4..b366ac2bb7 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -87,7 +87,8 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o -LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o +LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \ + drivers/power/pmic/libpmic.o LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o From 8b65b12a04e5665922697576538e75215d5b7a0f Mon Sep 17 00:00:00 2001 From: Greg Guyotte Date: Fri, 30 Aug 2013 16:28:42 -0400 Subject: [PATCH 02/11] drivers/power/pmic: Add tps65217 driver Add a driver for the TPS65217 PMIC that is found in the Beaglebone family of boards. Signed-off-by: Greg Guyotte [trini: Split and rework Greg's changes into new drivers/power framework] Signed-off-by: Tom Rini --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65217.c | 109 +++++++++++++++++++++++++++++ include/power/tps65217.h | 82 ++++++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65217.c create mode 100644 include/power/tps65217.h diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index f054470552..ac2b6252e2 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,7 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c new file mode 100644 index 0000000000..36e9024bf8 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65217.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * tps65217_reg_read() - Generic function that can read a TPS65217 register + * @src_reg: Source register address + * @src_val: Address of destination variable + * @return: 0 for success, not 0 on failure. + */ +int tps65217_reg_read(uchar src_reg, uchar *src_val) +{ + return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1); +} + +/** + * tps65217_reg_write() - Generic function that can write a TPS65217 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65217_PROT_LEVEL_NONE, + * TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65217_MASK_ALL_BITS) { + ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK; + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65217_PROT_LEVEL_2) { + ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65217_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65217_DEFDCDC1) && + (dc_cntrl_reg != TPS65217_DEFDCDC2) && + (dc_cntrl_reg != TPS65217_DEFDCDC3)) + return 1; + + /* set voltage level */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65217_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW, + TPS65217_DCDC_GO, TPS65217_DCDC_GO)) + return 1; + + return 0; +} diff --git a/include/power/tps65217.h b/include/power/tps65217.h new file mode 100644 index 0000000000..e8c8475577 --- /dev/null +++ b/include/power/tps65217.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65217a + */ + +#ifndef __POWER_TPS65217_H__ +#define __POWER_TPS65217_H__ + +/* I2C chip address */ +#define TPS65217_CHIP_PM 0x24 + +/* Registers */ +enum { + TPS65217_CHIPID = 0x00, + TPS65217_POWER_PATH, + TPS65217_INTERRUPT, + TPS65217_CHGCONFIG0, + TPS65217_CHGCONFIG1, + TPS65217_CHGCONFIG2, + TPS65217_CHGCONFIG3, + TPS65217_WLEDCTRL1, + TPS65217_WLEDCTRL2, + TPS65217_MUXCTRL, + TPS65217_STATUS, + TPS65217_PASSWORD, + TPS65217_PGOOD, + TPS65217_DEFPG, + TPS65217_DEFDCDC1, + TPS65217_DEFDCDC2, + TPS65217_DEFDCDC3, + TPS65217_DEFSLEW, + TPS65217_DEFLDO1, + TPS65217_DEFLDO2, + TPS65217_DEFLS1, + TPS65217_DEFLS2, + TPS65217_ENABLE, + TPS65217_DEFUVLO, + TPS65217_SEQ1, + TPS65217_SEQ2, + TPS65217_SEQ3, + TPS65217_SEQ4, + TPS65217_SEQ5, + TPS65217_SEQ6, + TPS65217_PMIC_NUM_OF_REGS, +}; + +#define TPS65217_PROT_LEVEL_NONE 0x00 +#define TPS65217_PROT_LEVEL_1 0x01 +#define TPS65217_PROT_LEVEL_2 0x02 + +#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00 +#define TPS65217_PASSWORD_UNLOCK 0x7D + +#define TPS65217_DCDC_GO 0x80 + +#define TPS65217_MASK_ALL_BITS 0xFF + +#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03 +#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00 +#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01 +#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 +#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 + +#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F +#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 + +#define TPS65217_LDO_MASK 0x1F +#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06 +#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F + +#define TPS65217_PWR_SRC_USB_BITMASK 0x4 +#define TPS65217_PWR_SRC_AC_BITMASK 0x8 + +int tps65217_reg_read(uchar src_reg, uchar *src_val); +int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask); +int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +#endif /* __POWER_TPS65217_H__ */ From b04601a7f0f29138bd4a14c383cdeefe83b5a7ee Mon Sep 17 00:00:00 2001 From: "Philip, Avinash" Date: Fri, 30 Aug 2013 16:28:43 -0400 Subject: [PATCH 03/11] drivers/power/pmic: Add tps65910 driver Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM, AM335x EVM SK and others. Signed-off-by: Philip, Avinash [trini: Split and rework Avinash's changes into new drivers/power framework] Signed-off-by: Tom Rini --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65910.c | 83 ++++++++++++++++++++++++++++++ include/power/tps65910.h | 77 +++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65910.c create mode 100644 include/power/tps65910.h diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index ac2b6252e2..11b3d030e4 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -14,6 +14,7 @@ COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c new file mode 100644 index 0000000000..7ee1160e0d --- /dev/null +++ b/drivers/power/pmic/pmic_tps65910.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C + * interface. + * @return: 0 on success, not 0 on failure + */ +int tps65910_set_i2c_control(void) +{ + int ret; + uchar buf; + + /* VDD1/2 voltage selection register access by control i/f */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + &buf, 1); + + if (ret) + return ret; + + buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + &buf, 1); +} + +/* + * tps65910_voltage_update() - Voltage switching for MPU frequency switching. + * @module: mpu - 0, core - 1 + * @vddx_op_vol_sel: vdd voltage to set + * @return: 0 on success, not 0 on failure + */ +int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf; + unsigned int reg_offset; + int ret; + + if (module == MPU) + reg_offset = TPS65910_VDD1_OP_REG; + else + reg_offset = TPS65910_VDD2_OP_REG; + + /* Select VDDx OP */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + buf &= ~TPS65910_OP_REG_CMD_MASK; + + ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + /* Configure VDDx OP Voltage */ + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + buf &= ~TPS65910_OP_REG_SEL_MASK; + buf |= vddx_op_vol_sel; + + ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + if (ret) + return ret; + + if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} diff --git a/include/power/tps65910.h b/include/power/tps65910.h new file mode 100644 index 0000000000..ca8430145b --- /dev/null +++ b/include/power/tps65910.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the TRM at http://www.ti.com/product/tps65910 + */ +#ifndef __POWER_TPS65910_H__ +#define __POWER_TPS65910_H__ + +#define MPU 0 +#define CORE 1 + +#define TPS65910_SR_I2C_ADDR 0x12 +#define TPS65910_CTRL_I2C_ADDR 0x2D + +/* PMIC Register offsets */ +enum { + TPS65910_VDD1_REG = 0x21, + TPS65910_VDD1_OP_REG = 0x22, + TPS65910_VDD2_REG = 0x24, + TPS65910_VDD2_OP_REG = 0x25, + TPS65910_DEVCTRL_REG = 0x3F, +}; + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define TPS65910_VGAIN_SEL_MASK (0x3 << 6) +#define TPS65910_ILMAX_MASK (0x1 << 5) +#define TPS65910_TSTEP_MASK (0x7 << 2) +#define TPS65910_ST_MASK (0x3) + +#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6) +#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6) +#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5) +#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5) + +#define TPS65910_REG_TSTEP_ (0x0 << 2) +#define TPS65910_REG_TSTEP_12_5 (0x1 << 2) +#define TPS65910_REG_TSTEP_9_4 (0x2 << 2) +#define TPS65910_REG_TSTEP_7_5 (0x3 << 2) +#define TPS65910_REG_TSTEP_6_25 (0x4 << 2) +#define TPS65910_REG_TSTEP_4_7 (0x5 << 2) +#define TPS65910_REG_TSTEP_3_12 (0x6 << 2) +#define TPS65910_REG_TSTEP_2_5 (0x7 << 2) + +#define TPS65910_REG_ST_OFF (0x0) +#define TPS65910_REG_ST_ON_HI_POW (0x1) +#define TPS65910_REG_ST_OFF_1 (0x2) +#define TPS65910_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define TPS65910_OP_REG_SEL (0x7F) + +#define TPS65910_OP_REG_CMD_MASK (0x1 << 7) +#define TPS65910_OP_REG_CMD_OP (0x0 << 7) +#define TPS65910_OP_REG_CMD_SR (0x1 << 7) + +#define TPS65910_OP_REG_SEL_MASK (0x7F) +#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */ +#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */ +#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ +#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +int tps65910_set_i2c_control(void); +int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel); +#endif /* __POWER_TPS65910_H__ */ From 6a0d803c7c9eeee24f579b764eb4bc51ed79eb5e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:44 -0400 Subject: [PATCH 04/11] am33xx: Add am33xx_spl_board_init function, call We need to allow for a further call-out in spl_board_init. Call this am33xx_spl_board_init and add a __weak version. This function may be used to scale the MPU frequency up, depending on board needs. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 9 +++++++++ arch/arm/cpu/armv7/omap-common/boot-common.c | 3 +++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + 3 files changed, 13 insertions(+) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 2ea3d698fb..05a2d28ba1 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -137,6 +138,14 @@ int arch_misc_init(void) } #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +/* + * This function is the place to do per-board things such as ramp up the + * MPU clock frequency. + */ +__weak void am33xx_spl_board_init(void) +{ +} + static void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 6b4772b684..0ffa03ac01 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -76,6 +76,9 @@ void spl_board_init(void) #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif +#ifdef CONFIG_AM33XX + am33xx_spl_board_init(); +#endif } int board_mmc_init(bd_t *bis) diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index c6070a3fc9..55f57ac9be 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -42,4 +42,5 @@ u32 wait_on_value(u32, u32, void *, u32); #ifdef CONFIG_NOR_BOOT void enable_norboot_pin_mux(void); #endif +void am33xx_spl_board_init(void); #endif From 5287946c0612e55f948b6ccbe2beaaffb78130ef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:45 -0400 Subject: [PATCH 05/11] am33xx: Add the efuse_sma CONTROL_MODULE register Starting with PG2.1 we have a register in the CONTROL_MODULE that is set with the package type and maximum supported frequency. Add this, and the relevant mask/values. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 73e6db8998..52fa128af9 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -38,6 +38,16 @@ #define AM335X 0xB944 #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) +#define DEVICE_ID_MASK 0x1FFF + +/* MPU max frequencies */ +#define AM335X_ZCZ_300 0x1FEF +#define AM335X_ZCZ_600 0x1FAF +#define AM335X_ZCZ_720 0x1F2F +#define AM335X_ZCZ_800 0x1E2F +#define AM335X_ZCZ_1000 0x1C2F +#define AM335X_ZCE_300 0x1FDF +#define AM335X_ZCE_600 0x1F9F /* This gives the status of the boot mode pins on the evm */ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ @@ -509,6 +519,8 @@ struct ctrl_dev { unsigned int macid1h; /* offset 0x3c */ unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ + unsigned int resv5[106]; + unsigned int efuse_sma; /* offset 0x1FC */ }; /* gmii_sel register defines */ From 9721027aae63aab072de6ee8eae68d8e684b3af3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 30 Aug 2013 16:28:46 -0400 Subject: [PATCH 06/11] am335x_evm: am33xx_spl_board_init function and scale core frequency Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/sys_info.c | 57 ++++++++ .../include/asm/arch-am33xx/clocks_am33xx.h | 10 +- arch/arm/include/asm/arch-am33xx/sys_proto.h | 3 + board/ti/am335x/board.c | 134 ++++++++++++++++++ include/configs/am335x_evm.h | 5 + 5 files changed, 208 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 63afaaa328..50eb598ff2 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -17,6 +17,7 @@ #include #include #include +#include struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; @@ -119,3 +120,59 @@ int print_cpuinfo(void) return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_AM33XX +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev) +{ + int sil_rev; + + sil_rev = readl(&cdev->deviceid) >> 28; + + if (sil_rev == 1) + /* PG 2.0, efuse may not be set. */ + return MPUPLL_M_800; + else if (sil_rev >= 2) { + /* Check what the efuse says our max speed is. */ + int efuse_arm_mpu_max_freq; + efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { + case AM335X_ZCZ_1000: + return MPUPLL_M_1000; + case AM335X_ZCZ_800: + return MPUPLL_M_800; + case AM335X_ZCZ_720: + return MPUPLL_M_720; + case AM335X_ZCZ_600: + case AM335X_ZCE_600: + return MPUPLL_M_600; + case AM335X_ZCZ_300: + case AM335X_ZCE_300: + return MPUPLL_M_300; + } + } + + /* PG 1.0 or otherwise unknown, use the PG1.0 max */ + return MPUPLL_M_720; +} + +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency) +{ + /* For PG2.1 and later, we have one set of values. */ + if (sil_rev >= 2) { + switch (frequency) { + case MPUPLL_M_1000: + return TPS65910_OP_REG_SEL_1_3_2_5; + case MPUPLL_M_800: + return TPS65910_OP_REG_SEL_1_2_6; + case MPUPLL_M_720: + return TPS65910_OP_REG_SEL_1_2_0; + case MPUPLL_M_600: + case MPUPLL_M_300: + return TPS65910_OP_REG_SEL_1_1_3; + } + } + + /* Default to PG1.0/PG2.0 values. */ + return TPS65910_OP_REG_SEL_1_1_3; +} +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 140379fb38..aad698ddfe 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -11,9 +11,17 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_550 550 +#define MPUPLL_M_300 300 + /* MAIN PLL Fdll = 550 MHz, by default */ #ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK 550 +#define CONFIG_SYS_MPUCLK MPUPLL_M_550 #endif #define UART_RESET (0x1 << 1) diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 55f57ac9be..87b7d367b9 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,6 +10,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include #define BOARD_REV_ID 0x0 @@ -43,4 +44,6 @@ u32 wait_on_value(u32, u32, void *, u32); void enable_norboot_pin_mux(void); #endif void am33xx_spl_board_init(void); +int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); +int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); #endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index cc0442612f..6135f07a41 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -244,6 +246,138 @@ const struct dpll_params dpll_ddr_evm_sk = { const struct dpll_params dpll_ddr_bone_black = { 400, OSC-1, 1, -1, -1, -1, -1}; +void am33xx_spl_board_init(void) +{ + struct am335x_baseboard_id header; + struct dpll_params dpll_mpu = {0, OSC-1, 1, -1, -1, -1, -1}; + int mpu_vdd; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Get the frequency */ + dpll_mpu.m = am335x_get_efuse_mpu_max_freq(cdev); + + if (board_is_bone(&header) || board_is_bone_lt(&header)) { + /* BeagleBone PMIC Code */ + int usb_cur_lim; + + /* + * Only perform PMIC configurations if board rev > A1 + * on Beaglebone White + */ + if (board_is_bone(&header) && !strncmp(header.version, + "00A1", 4)) + return; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * On Beaglebone White we need to ensure we have AC power + * before increasing the frequency. + */ + if (board_is_bone(&header)) { + uchar pmic_status_reg; + if (tps65217_reg_read(TPS65217_STATUS, + &pmic_status_reg)) + return; + if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { + puts("No AC power, disabling frequency switch\n"); + return; + } + } + + /* + * Override what we have detected since we know if we have + * a Beaglebone Black it supports 1GHz. + */ + if (board_is_bone_lt(&header)) + dpll_mpu.m = MPUPLL_M_1000; + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (board_is_bone(&header)) { + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } else { + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } else { + int sil_rev; + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + } + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); +} + const struct dpll_params *get_dpll_ddr_params(void) { struct am335x_baseboard_id header; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 3de30fc280..0c3384cc4a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -189,8 +189,13 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS +/* PMIC support */ +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + /* SPL */ #ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT /* CPSW support */ From 52f7d8442e0837ef00f848865286e301a5f0f78f Mon Sep 17 00:00:00 2001 From: Steve Kipisz Date: Wed, 14 Aug 2013 10:51:31 -0400 Subject: [PATCH 07/11] am335x:Handle worst case scenario for Errata 1.0.24 In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra Cc: Lars Poeschel Signed-off-by: Steve Kipisz [trini: Adapt to current framework] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 2 ++ arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 8 +++++-- .../include/asm/arch-am33xx/clocks_am33xx.h | 2 ++ board/ti/am335x/board.c | 24 ++++++++++++++----- include/configs/pcm051.h | 1 + include/power/tps65217.h | 1 + 6 files changed, 30 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 05a2d28ba1..a31bf40e5b 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -144,6 +144,8 @@ int arch_misc_init(void) */ __weak void am33xx_spl_board_init(void) { + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } static void rtc32k_enable(void) diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index e5f287b338..fabe2595a3 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = { .cm_div_m2_dpll = CM_WKUP + 0xA0, }; -const struct dpll_params dpll_mpu = { +struct dpll_params dpll_mpu_opp100 = { CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { +const struct dpll_params dpll_core_opp100 = { 1000, OSC-1, -1, -1, 10, 8, 4}; +const struct dpll_params dpll_mpu = { + MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + 50, OSC-1, -1, -1, 1, 1, 1}; const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index aad698ddfe..02ed5957e9 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -29,5 +29,7 @@ #define UART_SMART_IDLE_EN (0x1 << 0x3) extern void enable_dmm_clocks(void); +extern const struct dpll_params dpll_core_opp100; +extern struct dpll_params dpll_mpu_opp100; #endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 6135f07a41..c2fc5a613b 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -249,14 +249,13 @@ const struct dpll_params dpll_ddr_bone_black = { void am33xx_spl_board_init(void) { struct am335x_baseboard_id header; - struct dpll_params dpll_mpu = {0, OSC-1, 1, -1, -1, -1, -1}; int mpu_vdd; if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); /* Get the frequency */ - dpll_mpu.m = am335x_get_efuse_mpu_max_freq(cdev); + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); if (board_is_bone(&header) || board_is_bone_lt(&header)) { /* BeagleBone PMIC Code */ @@ -293,13 +292,13 @@ void am33xx_spl_board_init(void) * a Beaglebone Black it supports 1GHz. */ if (board_is_bone_lt(&header)) - dpll_mpu.m = MPUPLL_M_1000; + dpll_mpu_opp100.m = MPUPLL_M_1000; /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ - if (dpll_mpu.m == MPUPLL_M_1000) { + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; } else { @@ -313,6 +312,15 @@ void am33xx_spl_board_init(void) TPS65217_USB_INPUT_CUR_LIMIT_MASK)) puts("tps65217_reg_write failure\n"); + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { @@ -360,7 +368,8 @@ void am33xx_spl_board_init(void) * VDD to drive at that speed. */ sil_rev = readl(&cdev->deviceid) >> 28; - mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, dpll_mpu.m); + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); /* Tell the TPS65910 to use i2c */ tps65910_set_i2c_control(); @@ -372,10 +381,13 @@ void am33xx_spl_board_init(void) /* Second, update the CORE voltage. */ if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) return; + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); } /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } const struct dpll_params *get_dpll_ddr_params(void) diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index e2b4de7414..2fff0beffa 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -201,6 +201,7 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT /* * Place the image at the start of the ROM defined image space. * We limit our size to the ROM-defined downloaded image area, and use the diff --git a/include/power/tps65217.h b/include/power/tps65217.h index e8c8475577..297c4cbd99 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -65,6 +65,7 @@ enum { #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03 +#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09 #define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F #define TPS65217_DCDC_VOLT_SEL_1325MV 0x11 From d3d33daf1112d3b1c6c330422740a4e210259f88 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 23 Aug 2013 17:27:04 +0530 Subject: [PATCH 08/11] ARM: DRA7: Enable saveenv command dra7xx_evm has eMMC and the default environment can be stored in it. So enabling saveenv command and the configs to store environment in eMMC. Tested on DRA752 ES1.0 Signed-off-by: Lokesh Vutla --- include/configs/dra7xx_evm.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 4fbe768cbc..7b120de213 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,7 +14,13 @@ #define CONFIG_DRA7XX -#define CONFIG_ENV_IS_NOWHERE /* For now. */ +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_CMD_SAVEENV #define CONSOLEDEV "ttyO0" #define CONFIG_CONS_INDEX 1 From e22cc0cf137149bea3a06bb29ffe06e82d8edb84 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Fri, 23 Aug 2013 17:34:17 +0530 Subject: [PATCH 09/11] ARM: OMAP5: Avoid writing into LDO SRAM bits Writing magic bits into LDO SRAM was suggested only for OMAP5432 ES1.0. Now these are no longer applicable. Moreover these bits should not be overwritten as they are loaded from EFUSE. So avoid writing into these registers. Boot tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 7 ------- arch/arm/cpu/armv7/omap5/prcm-regs.c | 12 ------------ arch/arm/include/asm/omap_common.h | 6 ------ 3 files changed, 25 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 7580594074..ab0c5680f5 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->iva); do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { - /* Configure LDO SRAM "magic" bits */ - writel(2, (*prcm)->prm_sldo_core_setup); - writel(2, (*prcm)->prm_sldo_mpu_setup); - writel(2, (*prcm)->prm_sldo_mm_setup); - } } static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 579818d559..5a3d52c11a 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = { .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, - .prm_sldo_core_setup = 0x4ae07bc4, - .prm_sldo_core_ctrl = 0x4ae07bc8, - .prm_sldo_mpu_setup = 0x4ae07bcc, - .prm_sldo_mpu_ctrl = 0x4ae07bd0, - .prm_sldo_mm_setup = 0x4ae07bd4, - .prm_sldo_mm_ctrl = 0x4ae07bd8, /* SCRM stuff, used by some boards */ .scrm_auxclk0 = 0x4ae0a310, @@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = { .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, - .prm_sldo_core_setup = 0x4ae07cc4, - .prm_sldo_core_ctrl = 0x4ae07cc8, - .prm_sldo_mpu_setup = 0x4ae07ccc, - .prm_sldo_mpu_ctrl = 0x4ae07cd0, - .prm_sldo_mm_setup = 0x4ae07cd4, - .prm_sldo_mm_ctrl = 0x4ae07cd8, .prm_abbldo_mpu_setup = 0x4ae07cdc, .prm_abbldo_mpu_ctrl = 0x4ae07ce0, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 5e2f027ba4..61fee9f06d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -310,12 +310,6 @@ struct prcm_regs { u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; - u32 prm_sldo_core_setup; - u32 prm_sldo_core_ctrl; - u32 prm_sldo_mpu_setup; - u32 prm_sldo_mpu_ctrl; - u32 prm_sldo_mm_setup; - u32 prm_sldo_mm_ctrl; u32 prm_abbldo_mpu_setup; u32 prm_abbldo_mpu_ctrl; From 93ff25529898b931b5000c6e9ec9d7325f2ec414 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 5 Sep 2013 11:50:41 +0200 Subject: [PATCH 10/11] net, phy, cpsw: fix NULL pointer deference if phy_connect() did not find a phy, phydev is NULL and following code in cpsw_phy_init() crashes. Fix this. Signed-off-by: Heiko Schocher Cc: Joe Hershberger Cc: Mugunthan V N Cc: Tom Rini Acked-by: Mugunthan V N --- drivers/net/cpsw.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 9bab71a212..39240d9662 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave, static void cpsw_slave_update_link(struct cpsw_slave *slave, struct cpsw_priv *priv, int *link) { - struct phy_device *phy = priv->phydev; + struct phy_device *phy; u32 mac_control = 0; + phy = priv->phydev; + + if (!phy) + return; + phy_startup(phy); *link = phy->link; @@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) dev, slave->data->phy_if); + if (!phydev) + return -1; + phydev->supported &= supported; phydev->advertising = phydev->supported; From 827512fb1154c05c6eb1e2259e936df55c98a535 Mon Sep 17 00:00:00 2001 From: "Robert P. J. Day" Date: Mon, 9 Sep 2013 12:27:25 -0400 Subject: [PATCH 11/11] am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should mmcroot. If, in CONFIG_BOOTCOMMAND, the environment switches both the mmcdev and bootpart variables to refer to MMC device 1, it would make sense that the mmcroot env variable should switch to that device as well. Signed-off-by: Robert P. J. Day --- include/configs/am335x_evm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0c3384cc4a..cdf689f875 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -170,6 +170,7 @@ "run mmcboot;" \ "setenv mmcdev 1; " \ "setenv bootpart 1:2; " \ + "setenv mmcroot /dev/mmcblk1p2 ro; " \ "run mmcboot;" \ "run nandboot;"