diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c index 442b5fc918..72d524caad 100644 --- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c +++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c @@ -91,7 +91,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, } /* Initialize IO Control */ - out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); + out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR); /* Initialize DDR Local Window */ out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 8bce586b53..c430cb640b 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -848,10 +848,6 @@ typedef struct ioctrl512x { u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ } ioctrl512x_t; -/* Indexes in regs array */ -/* Set for DDR */ -#define IOCTRL_MUX_DDR 0x00000036 - /* IO pin fields */ #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ diff --git a/include/configs/aria.h b/include/configs/aria.h index b6669e72a6..7097ab72d0 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -79,6 +79,8 @@ #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 + /* DDR Controller Configuration * * SYS_CFG: diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index cccc31d5ed..cafd6a7f66 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -67,6 +67,8 @@ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 + /* DDR Controller Configuration * * SYS_CFG: diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index fb49388bd0..8ecc9e1141 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -86,6 +86,8 @@ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 + /* DDR Controller Configuration * * SYS_CFG: