net: sc589: drop unused !NET_MULTI driver
No boards appear to use this driver, and it doesn't support NET_MULTI, so punt the old driver. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
Wolfgang Denk
parent
c1761eeab0
commit
5de78b17f0
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@ -1,517 +0,0 @@
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/*------------------------------------------------------------------------
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. 3c589.c
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. This is a driver for 3Com's 3C589 (Etherlink III) PCMCIA Ethernet device.
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.
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. (C) Copyright 2002
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. Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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. Rolf Offermanns <rof@sysgo.de>
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.
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. This program is free software; you can redistribute it and/or modify
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. it under the terms of the GNU General Public License as published by
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. the Free Software Foundation; either version 2 of the License, or
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. (at your option) any later version.
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.
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. This program is distributed in the hope that it will be useful,
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. but WITHOUT ANY WARRANTY; without even the implied warranty of
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. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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. GNU General Public License for more details.
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.
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. You should have received a copy of the GNU General Public License
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. along with this program; if not, write to the Free Software
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. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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.
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----------------------------------------------------------------------------*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include "3c589.h"
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/* Use power-down feature of the chip */
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#define POWER_DOWN 0
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#define NO_AUTOPROBE
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static const char version[] =
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"Your ad here! :P\n";
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#undef EL_DEBUG
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typedef unsigned char byte;
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typedef unsigned short word;
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typedef unsigned long int dword;
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/*------------------------------------------------------------------------
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.
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. Configuration options, for the experienced user to change.
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.
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-------------------------------------------------------------------------*/
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/*
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. Wait time for memory to be free. This probably shouldn't be
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. tuned that much, as waiting for this means nothing else happens
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. in the system
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*/
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#define MEMORY_WAIT_TIME 16
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#if (EL_DEBUG > 2 )
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#define PRINTK3(args...) printf(args)
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#else
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#define PRINTK3(args...)
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#endif
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#if EL_DEBUG > 1
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#define PRINTK2(args...) printf(args)
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#else
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#define PRINTK2(args...)
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#endif
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#ifdef EL_DEBUG
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#define PRINTK(args...) printf(args)
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#else
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#define PRINTK(args...)
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#endif
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#define outb(args...) mmio_outb(args)
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#define mmio_outb(value, addr) (*((volatile byte *)(addr)) = value)
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#define inb(args...) mmio_inb(args)
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#define mmio_inb(addr) (*((volatile byte *)(addr)))
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#define outw(args...) mmio_outw(args)
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#define mmio_outw(value, addr) (*((volatile word *)(addr)) = value)
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#define inw(args...) mmio_inw(args)
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#define mmio_inw(addr) (*((volatile word *)(addr)))
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#define outsw(args...) mmio_outsw(args)
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#define mmio_outsw(r,b,l) ({ int __i; \
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word *__b2; \
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__b2 = (word *) b; \
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for (__i = 0; __i < l; __i++) { \
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mmio_outw( *(__b2 + __i), r); \
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} \
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})
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#define insw(args...) mmio_insw(args)
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#define mmio_insw(r,b,l) ({ int __i ; \
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word *__b2; \
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__b2 = (word *) b; \
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for (__i = 0; __i < l; __i++) { \
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*(__b2 + __i) = mmio_inw(r); \
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mmio_inw(0); \
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}; \
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})
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/*------------------------------------------------------------------------
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.
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. The internal workings of the driver. If you are changing anything
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. here with the 3Com stuff, you should have the datasheet and know
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. what you are doing.
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.
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-------------------------------------------------------------------------*/
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#define EL_BASE_ADDR 0x20000000
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/* Offsets from base I/O address. */
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#define EL3_DATA 0x00
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#define EL3_TIMER 0x0a
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#define EL3_CMD 0x0e
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#define EL3_STATUS 0x0e
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#define EEPROM_READ 0x0080
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#define EL3WINDOW(win_num) mmio_outw(SelectWindow + (win_num), EL_BASE_ADDR + EL3_CMD)
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/* The top five bits written to EL3_CMD are a command, the lower
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11 bits are the parameter, if applicable. */
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enum c509cmd {
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TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
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RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11,
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TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
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FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
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SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
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SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11,
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StatsDisable = 22<<11, StopCoax = 23<<11,
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};
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enum c509status {
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IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
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TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
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IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000
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};
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/* The SetRxFilter command accepts the following classes: */
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enum RxFilter {
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RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
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};
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/* Register window 1 offsets, the window used in normal operation. */
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#define TX_FIFO 0x00
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#define RX_FIFO 0x00
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#define RX_STATUS 0x08
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#define TX_STATUS 0x0B
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#define TX_FREE 0x0C /* Remaining free bytes in Tx buffer. */
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/*
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Read a word from the EEPROM using the regular EEPROM access register.
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Assume that we are in register window zero.
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*/
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static word read_eeprom(dword ioaddr, int index)
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{
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int i;
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outw(EEPROM_READ + index, ioaddr + 0xa);
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/* Reading the eeprom takes 162 us */
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for (i = 1620; i >= 0; i--)
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if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0)
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break;
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return inw(ioaddr + 0xc);
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}
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static void el_get_mac_addr( unsigned char *mac_addr )
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{
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int i;
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union
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{
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word w;
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unsigned char b[2];
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} wrd;
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unsigned char old_window = inw( EL_BASE_ADDR + EL3_STATUS ) >> 13;
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GO_WINDOW(0);
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VX_BUSY_WAIT;
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for (i = 0; i < 3; i++)
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{
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wrd.w = read_eeprom(EL_BASE_ADDR, 0xa+i);
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#ifdef __BIG_ENDIAN
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mac_addr[2*i] = wrd.b[0];
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mac_addr[2*i+1] = wrd.b[1];
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#else
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mac_addr[2*i] = wrd.b[1];
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mac_addr[2*i+1] = wrd.b[0];
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#endif
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}
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GO_WINDOW(old_window);
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VX_BUSY_WAIT;
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}
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#if EL_DEBUG > 1
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static void print_packet( byte * buf, int length )
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{
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int i;
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int remainder;
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int lines;
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PRINTK2("Packet of length %d \n", length );
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lines = length / 16;
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remainder = length % 16;
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for ( i = 0; i < lines ; i ++ ) {
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int cur;
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for ( cur = 0; cur < 8; cur ++ ) {
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byte a, b;
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a = *(buf ++ );
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b = *(buf ++ );
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PRINTK2("%02x%02x ", a, b );
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}
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PRINTK2("\n");
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}
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for ( i = 0; i < remainder/2 ; i++ ) {
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byte a, b;
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a = *(buf ++ );
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b = *(buf ++ );
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PRINTK2("%02x%02x ", a, b );
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}
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PRINTK2("\n");
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}
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#endif /* EL_DEBUG > 1 */
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/**************************************************************************
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ETH_RESET - Reset adapter
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***************************************************************************/
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static void el_reset(bd_t *bd)
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{
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/***********************************************************
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Reset 3Com 595 card
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*************************************************************/
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/* QUICK HACK
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* - adjust timing for 3c589
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* - enable io for PCMCIA */
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outw(0x0004, 0xa0000018);
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udelay(100);
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outw(0x0041, 0x28010000);
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udelay(100);
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/* issue global reset */
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outw(GLOBAL_RESET, BASE + VX_COMMAND);
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/* must wait for at least 1ms */
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udelay(100000000);
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/* set mac addr */
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{
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uchar mac_addr[6];
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int i;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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el_get_mac_addr(mac_addr);
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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GO_WINDOW(2);
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VX_BUSY_WAIT;
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printf("3C589 MAC Addr.: ");
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for (i = 0; i < 6; i++)
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{
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printf("%02x", mac_addr[i]);
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outb(mac_addr[i], BASE + VX_W2_ADDR_0 + i);
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VX_BUSY_WAIT;
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}
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printf("\n\n");
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}
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/* set RX filter */
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outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + VX_COMMAND);
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VX_BUSY_WAIT;
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/* set irq mask and read_zero */
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outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
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S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
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VX_BUSY_WAIT;
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outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
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S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
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VX_BUSY_WAIT;
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/* enable TP Linkbeat */
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GO_WINDOW(4);
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VX_BUSY_WAIT;
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outw( ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
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VX_BUSY_WAIT;
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/*
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* Attempt to get rid of any stray interrupts that occured during
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* configuration. On the i386 this isn't possible because one may
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* already be queued. However, a single stray interrupt is
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* unimportant.
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*/
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outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
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VX_BUSY_WAIT;
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/* enable TX and RX */
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outw( RX_ENABLE, BASE + VX_COMMAND );
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VX_BUSY_WAIT;
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outw( TX_ENABLE, BASE + VX_COMMAND );
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VX_BUSY_WAIT;
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/* print the diag. regs. */
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PRINTK2("Diag. Regs\n");
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PRINTK2("--> MEDIA_TYPE: %04x\n", inw(BASE + VX_W4_MEDIA_TYPE));
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PRINTK2("--> NET_DIAG: %04x\n", inw(BASE + VX_W4_NET_DIAG));
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PRINTK2("--> FIFO_DIAG: %04x\n", inw(BASE + VX_W4_FIFO_DIAG));
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PRINTK2("--> CTRLR_STATUS: %04x\n", inw(BASE + VX_W4_CTRLR_STATUS));
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PRINTK2("\n\n");
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/* enter working mode */
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GO_WINDOW(1);
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VX_BUSY_WAIT;
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/* wait for another 1ms */
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udelay(100000000);
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}
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/*-----------------------------------------------------------------
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.
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. The driver can be entered at any of the following entry points.
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.
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.------------------------------------------------------------------ */
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extern int eth_init(bd_t *bd);
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extern void eth_halt(void);
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extern int eth_rx(void);
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extern int eth_send(volatile void *packet, int length);
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/*
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------------------------------------------------------------
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.
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. Internal routines
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.
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------------------------------------------------------------
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*/
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int eth_init(bd_t *bd)
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{
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el_reset(bd);
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return 0;
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}
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void eth_halt() {
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return;
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}
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#define EDEBUG 1
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/**************************************************************************
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ETH_POLL - Wait for a frame
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***************************************************************************/
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int eth_rx()
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{
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word status, rx_status, packet_size;
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VX_BUSY_WAIT;
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status = inw( BASE + VX_STATUS );
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if ( (status & S_RX_COMPLETE) == 0 ) return 0; /* nothing to do */
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/* Packet waiting -> check RX_STATUS */
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rx_status = inw( BASE + VX_W1_RX_STATUS );
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if ( rx_status & ERR_RX )
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{
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/* error in packet -> discard */
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PRINTK("[ERROR] Invalid packet -> discarding\n");
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PRINTK("-- error code 0x%02x\n", rx_status & ERR_MASK);
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PRINTK("-- rx bytes 0x%04d\n", rx_status & ((1<<11) - 1));
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PRINTK("[ERROR] Invalid packet -> discarding\n");
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outw( RX_DISCARD_TOP_PACK, BASE + VX_COMMAND );
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return 0;
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}
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/* correct pack. waiting in fifo */
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packet_size = rx_status & RX_BYTES_MASK;
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PRINTK("Correct packet waiting in fifo, size: %d\n", packet_size);
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{
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volatile word *packet_start = (word *)(BASE + VX_W1_RX_PIO_RD_1);
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word *RcvBuffer = (word *)(NetRxPackets[0]);
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int wcount = 0;
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for (wcount = 0; wcount < (packet_size >> 1); wcount++)
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{
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*RcvBuffer++ = *(packet_start);
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}
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/* handle odd packets */
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if ( packet_size & 1 )
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{
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*RcvBuffer++ = *(packet_start);
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}
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}
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/* fifo should now be empty (besides the padding bytes) */
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if ( ((*((word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK) > 3 )
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{
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PRINTK("[ERROR] Fifo not empty after packet read (remaining pkts: %d)\n",
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(((*(word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK));
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}
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/* discard packet */
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*((word *)(BASE + VX_COMMAND)) = RX_DISCARD_TOP_PACK;
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/* Pass Packets to upper Layer */
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NetReceive(NetRxPackets[0], packet_size);
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return packet_size;
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}
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/**************************************************************************
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ETH_TRANSMIT - Transmit a frame
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***************************************************************************/
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static char padmap[] = {
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0, 3, 2, 1};
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int eth_send(volatile void *packet, int length) {
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int pad;
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int status;
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volatile word *buf = (word *)packet;
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int dummy = 0;
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/* padding stuff */
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pad = padmap[length & 3];
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PRINTK("eth_send(), length: %d\n", length);
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/* drop acknowledgements */
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while(( status=inb(EL_BASE_ADDR + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
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if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) {
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outw(TX_RESET, EL_BASE_ADDR + VX_COMMAND);
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outw(TX_ENABLE, EL_BASE_ADDR + VX_COMMAND);
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PRINTK("Bad status, resetting and reenabling transmitter\n");
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}
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outb(0x0, EL_BASE_ADDR + VX_W1_TX_STATUS);
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}
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while (inw(EL_BASE_ADDR + VX_W1_FREE_TX) < length + pad + 4) {
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/* no room in FIFO */
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if (dummy == 0)
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{
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PRINTK("No room in FIFO, waiting...\n");
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dummy++;
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}
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}
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PRINTK(" ---> FIFO ready\n");
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outw(length, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
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/* Second dword meaningless */
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outw(0x0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
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#if EL_DEBUG > 1
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print_packet((byte *)buf, length);
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#endif
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/* write packet */
|
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{
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unsigned int i, totw;
|
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|
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totw = ((length + 1) >> 1);
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PRINTK("Buffer: (totw = %d)\n", totw);
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for (i = 0; i < totw; i++) {
|
||||
outw( *(buf+i), EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
|
||||
udelay(10);
|
||||
}
|
||||
if(totw & 1)
|
||||
{ /* pad to double word length */
|
||||
outw( 0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
|
||||
udelay(10);
|
||||
}
|
||||
PRINTK("\n\n");
|
||||
}
|
||||
|
||||
/* wait for Tx complete */
|
||||
PRINTK("Waiting for Tx to complete...\n");
|
||||
while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0)
|
||||
{
|
||||
udelay(10);
|
||||
}
|
||||
PRINTK(" ---> Tx completed, status = 0x%04x\n", status);
|
||||
|
||||
return length;
|
||||
}
|
||||
|
|
@ -1,435 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer. 2. The name
|
||||
* of the author may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
||||
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
October 2, 1994
|
||||
|
||||
Modified by: Andres Vega Garcia
|
||||
|
||||
INRIA - Sophia Antipolis, France
|
||||
e-mail: avega@sophia.inria.fr
|
||||
finger: avega@pax.inria.fr
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
|
||||
* 3c590 family.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp>
|
||||
* for etherboot
|
||||
* Mar. 14, 2000
|
||||
*/
|
||||
|
||||
/*
|
||||
* Ethernet software status per interface.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Some global constants
|
||||
*/
|
||||
|
||||
#define TX_INIT_RATE 16
|
||||
#define TX_INIT_MAX_RATE 64
|
||||
#define RX_INIT_LATENCY 64
|
||||
#define RX_INIT_EARLY_THRESH 64
|
||||
#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
|
||||
#define MIN_RX_EARLY_THRESHL 4
|
||||
|
||||
#define EEPROMSIZE 0x40
|
||||
#define MAX_EEPROMBUSY 1000
|
||||
#define VX_LAST_TAG 0xd7
|
||||
#define VX_MAX_BOARDS 16
|
||||
#define VX_ID_PORT 0x100
|
||||
|
||||
/*
|
||||
* some macros to acces long named fields
|
||||
*/
|
||||
#define BASE (EL_BASE_ADDR)
|
||||
|
||||
/*
|
||||
* Commands to read/write EEPROM trough EEPROM command register (Window 0,
|
||||
* Offset 0xa)
|
||||
*/
|
||||
#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
|
||||
#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
|
||||
#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
|
||||
#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
|
||||
|
||||
#define EEPROM_BUSY (1<<15)
|
||||
|
||||
/*
|
||||
* Some short functions, worth to let them be a macro
|
||||
*/
|
||||
|
||||
/**************************************************************************
|
||||
* *
|
||||
* These define the EEPROM data structure. They are used in the probe
|
||||
* function to verify the existence of the adapter after having sent
|
||||
* the ID_Sequence.
|
||||
*
|
||||
* There are others but only the ones we use are defined here.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#define EEPROM_NODE_ADDR_0 0x0 /* Word */
|
||||
#define EEPROM_NODE_ADDR_1 0x1 /* Word */
|
||||
#define EEPROM_NODE_ADDR_2 0x2 /* Word */
|
||||
#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
|
||||
#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
|
||||
#define EEPROM_ADDR_CFG 0x8 /* Base addr */
|
||||
#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
|
||||
#define EEPROM_OEM_ADDR_0 0xa /* Word */
|
||||
#define EEPROM_OEM_ADDR_1 0xb /* Word */
|
||||
#define EEPROM_OEM_ADDR_2 0xc /* Word */
|
||||
#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */
|
||||
|
||||
#define NO_RX_OVN_ANOMALY (1<<5)
|
||||
|
||||
/**************************************************************************
|
||||
* *
|
||||
* These are the registers for the 3Com 3c509 and their bit patterns when *
|
||||
* applicable. They have been taken out the the "EtherLink III Parallel *
|
||||
* Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
|
||||
* from 3com. *
|
||||
* *
|
||||
**************************************************************************/
|
||||
|
||||
#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a
|
||||
* command reg. */
|
||||
#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status
|
||||
* reg. */
|
||||
#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window
|
||||
* reg. */
|
||||
/*
|
||||
* Window 0 registers. Setup.
|
||||
*/
|
||||
/* Write */
|
||||
#define VX_W0_EEPROM_DATA 0x0c
|
||||
#define VX_W0_EEPROM_COMMAND 0x0a
|
||||
#define VX_W0_RESOURCE_CFG 0x08
|
||||
#define VX_W0_ADDRESS_CFG 0x06
|
||||
#define VX_W0_CONFIG_CTRL 0x04
|
||||
/* Read */
|
||||
#define VX_W0_PRODUCT_ID 0x02
|
||||
#define VX_W0_MFG_ID 0x00
|
||||
|
||||
|
||||
/*
|
||||
* Window 1 registers. Operating Set.
|
||||
*/
|
||||
/* Write */
|
||||
#define VX_W1_TX_PIO_WR_2 0x02
|
||||
#define VX_W1_TX_PIO_WR_1 0x00
|
||||
/* Read */
|
||||
#define VX_W1_FREE_TX 0x0c
|
||||
#define VX_W1_TX_STATUS 0x0b /* byte */
|
||||
#define VX_W1_TIMER 0x0a /* byte */
|
||||
#define VX_W1_RX_STATUS 0x08
|
||||
#define VX_W1_RX_PIO_RD_2 0x02
|
||||
#define VX_W1_RX_PIO_RD_1 0x00
|
||||
|
||||
/*
|
||||
* Window 2 registers. Station Address Setup/Read
|
||||
*/
|
||||
/* Read/Write */
|
||||
#define VX_W2_ADDR_5 0x05
|
||||
#define VX_W2_ADDR_4 0x04
|
||||
#define VX_W2_ADDR_3 0x03
|
||||
#define VX_W2_ADDR_2 0x02
|
||||
#define VX_W2_ADDR_1 0x01
|
||||
#define VX_W2_ADDR_0 0x00
|
||||
|
||||
/*
|
||||
* Window 3 registers. FIFO Management.
|
||||
*/
|
||||
/* Read */
|
||||
#define VX_W3_INTERNAL_CFG 0x00
|
||||
#define VX_W3_RESET_OPT 0x08
|
||||
#define VX_W3_FREE_TX 0x0c
|
||||
#define VX_W3_FREE_RX 0x0a
|
||||
|
||||
/*
|
||||
* Window 4 registers. Diagnostics.
|
||||
*/
|
||||
/* Read/Write */
|
||||
#define VX_W4_MEDIA_TYPE 0x0a
|
||||
#define VX_W4_CTRLR_STATUS 0x08
|
||||
#define VX_W4_NET_DIAG 0x06
|
||||
#define VX_W4_FIFO_DIAG 0x04
|
||||
#define VX_W4_HOST_DIAG 0x02
|
||||
#define VX_W4_TX_DIAG 0x00
|
||||
|
||||
/*
|
||||
* Window 5 Registers. Results and Internal status.
|
||||
*/
|
||||
/* Read */
|
||||
#define VX_W5_READ_0_MASK 0x0c
|
||||
#define VX_W5_INTR_MASK 0x0a
|
||||
#define VX_W5_RX_FILTER 0x08
|
||||
#define VX_W5_RX_EARLY_THRESH 0x06
|
||||
#define VX_W5_TX_AVAIL_THRESH 0x02
|
||||
#define VX_W5_TX_START_THRESH 0x00
|
||||
|
||||
/*
|
||||
* Window 6 registers. Statistics.
|
||||
*/
|
||||
/* Read/Write */
|
||||
#define TX_TOTAL_OK 0x0c
|
||||
#define RX_TOTAL_OK 0x0a
|
||||
#define TX_DEFERRALS 0x08
|
||||
#define RX_FRAMES_OK 0x07
|
||||
#define TX_FRAMES_OK 0x06
|
||||
#define RX_OVERRUNS 0x05
|
||||
#define TX_COLLISIONS 0x04
|
||||
#define TX_AFTER_1_COLLISION 0x03
|
||||
#define TX_AFTER_X_COLLISIONS 0x02
|
||||
#define TX_NO_SQE 0x01
|
||||
#define TX_CD_LOST 0x00
|
||||
|
||||
/****************************************
|
||||
*
|
||||
* Register definitions.
|
||||
*
|
||||
****************************************/
|
||||
|
||||
/*
|
||||
* Command register. All windows.
|
||||
*
|
||||
* 16 bit register.
|
||||
* 15-11: 5-bit code for command to be executed.
|
||||
* 10-0: 11-bit arg if any. For commands with no args;
|
||||
* this can be set to anything.
|
||||
*/
|
||||
#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms
|
||||
* after issuing */
|
||||
#define WINDOW_SELECT (unsigned short) (0x1<<11)
|
||||
#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to
|
||||
* determine whether
|
||||
* this is needed. If
|
||||
* so; wait 800 uSec
|
||||
* before using trans-
|
||||
* ceiver. */
|
||||
#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on
|
||||
* power-up */
|
||||
#define RX_ENABLE (unsigned short) (0x4<<11)
|
||||
#define RX_RESET (unsigned short) (0x5<<11)
|
||||
#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11)
|
||||
#define TX_ENABLE (unsigned short) (0x9<<11)
|
||||
#define TX_DISABLE (unsigned short) (0xa<<11)
|
||||
#define TX_RESET (unsigned short) (0xb<<11)
|
||||
#define REQ_INTR (unsigned short) (0xc<<11)
|
||||
/*
|
||||
* The following C_* acknowledge the various interrupts. Some of them don't
|
||||
* do anything. See the manual.
|
||||
*/
|
||||
#define ACK_INTR (unsigned short) (0x6800)
|
||||
# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1)
|
||||
# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2)
|
||||
# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4)
|
||||
# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8)
|
||||
# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10)
|
||||
# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20)
|
||||
# define C_INT_RQD (unsigned short) (ACK_INTR|0x40)
|
||||
# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80)
|
||||
#define SET_INTR_MASK (unsigned short) (0xe<<11)
|
||||
#define SET_RD_0_MASK (unsigned short) (0xf<<11)
|
||||
#define SET_RX_FILTER (unsigned short) (0x10<<11)
|
||||
# define FIL_INDIVIDUAL (unsigned short) (0x1)
|
||||
# define FIL_MULTICAST (unsigned short) (0x02)
|
||||
# define FIL_BRDCST (unsigned short) (0x04)
|
||||
# define FIL_PROMISC (unsigned short) (0x08)
|
||||
#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11)
|
||||
#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11)
|
||||
#define SET_TX_START_THRESH (unsigned short) (0x13<<11)
|
||||
#define STATS_ENABLE (unsigned short) (0x15<<11)
|
||||
#define STATS_DISABLE (unsigned short) (0x16<<11)
|
||||
#define STOP_TRANSCEIVER (unsigned short) (0x17<<11)
|
||||
|
||||
/*
|
||||
* Status register. All windows.
|
||||
*
|
||||
* 15-13: Window number(0-7).
|
||||
* 12: Command_in_progress.
|
||||
* 11: reserved.
|
||||
* 10: reserved.
|
||||
* 9: reserved.
|
||||
* 8: reserved.
|
||||
* 7: Update Statistics.
|
||||
* 6: Interrupt Requested.
|
||||
* 5: RX Early.
|
||||
* 4: RX Complete.
|
||||
* 3: TX Available.
|
||||
* 2: TX Complete.
|
||||
* 1: Adapter Failure.
|
||||
* 0: Interrupt Latch.
|
||||
*/
|
||||
#define S_INTR_LATCH (unsigned short) (0x1)
|
||||
#define S_CARD_FAILURE (unsigned short) (0x2)
|
||||
#define S_TX_COMPLETE (unsigned short) (0x4)
|
||||
#define S_TX_AVAIL (unsigned short) (0x8)
|
||||
#define S_RX_COMPLETE (unsigned short) (0x10)
|
||||
#define S_RX_EARLY (unsigned short) (0x20)
|
||||
#define S_INT_RQD (unsigned short) (0x40)
|
||||
#define S_UPD_STATS (unsigned short) (0x80)
|
||||
#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000)
|
||||
|
||||
#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
|
||||
|
||||
/* Address Config. Register.
|
||||
* Window 0/Port 06
|
||||
*/
|
||||
|
||||
#define ACF_CONNECTOR_BITS 14
|
||||
#define ACF_CONNECTOR_UTP 0
|
||||
#define ACF_CONNECTOR_AUI 1
|
||||
#define ACF_CONNECTOR_BNC 3
|
||||
|
||||
#define INTERNAL_CONNECTOR_BITS 20
|
||||
#define INTERNAL_CONNECTOR_MASK 0x01700000
|
||||
|
||||
/*
|
||||
* FIFO Registers. RX Status.
|
||||
*
|
||||
* 15: Incomplete or FIFO empty.
|
||||
* 14: 1: Error in RX Packet 0: Incomplete or no error.
|
||||
* 13-11: Type of error.
|
||||
* 1000 = Overrun.
|
||||
* 1011 = Run Packet Error.
|
||||
* 1100 = Alignment Error.
|
||||
* 1101 = CRC Error.
|
||||
* 1001 = Oversize Packet Error (>1514 bytes)
|
||||
* 0010 = Dribble Bits.
|
||||
* (all other error codes, no errors.)
|
||||
*
|
||||
* 10-0: RX Bytes (0-1514)
|
||||
*/
|
||||
#define ERR_INCOMPLETE (unsigned short) (0x8000)
|
||||
#define ERR_RX (unsigned short) (0x4000)
|
||||
#define ERR_MASK (unsigned short) (0x7800)
|
||||
#define ERR_OVERRUN (unsigned short) (0x4000)
|
||||
#define ERR_RUNT (unsigned short) (0x5800)
|
||||
#define ERR_ALIGNMENT (unsigned short) (0x6000)
|
||||
#define ERR_CRC (unsigned short) (0x6800)
|
||||
#define ERR_OVERSIZE (unsigned short) (0x4800)
|
||||
#define ERR_DRIBBLE (unsigned short) (0x1000)
|
||||
|
||||
/*
|
||||
* TX Status.
|
||||
*
|
||||
* Reports the transmit status of a completed transmission. Writing this
|
||||
* register pops the transmit completion stack.
|
||||
*
|
||||
* Window 1/Port 0x0b.
|
||||
*
|
||||
* 7: Complete
|
||||
* 6: Interrupt on successful transmission requested.
|
||||
* 5: Jabber Error (TP Only, TX Reset required. )
|
||||
* 4: Underrun (TX Reset required. )
|
||||
* 3: Maximum Collisions.
|
||||
* 2: TX Status Overflow.
|
||||
* 1-0: Undefined.
|
||||
*
|
||||
*/
|
||||
#define TXS_COMPLETE 0x80
|
||||
#define TXS_INTR_REQ 0x40
|
||||
#define TXS_JABBER 0x20
|
||||
#define TXS_UNDERRUN 0x10
|
||||
#define TXS_MAX_COLLISION 0x8
|
||||
#define TXS_STATUS_OVERFLOW 0x4
|
||||
|
||||
#define RS_AUI (1<<5)
|
||||
#define RS_BNC (1<<4)
|
||||
#define RS_UTP (1<<3)
|
||||
#define RS_T4 (1<<0)
|
||||
#define RS_TX (1<<1)
|
||||
#define RS_FX (1<<2)
|
||||
#define RS_MII (1<<6)
|
||||
|
||||
|
||||
/*
|
||||
* FIFO Status (Window 4)
|
||||
*
|
||||
* Supports FIFO diagnostics
|
||||
*
|
||||
* Window 4/Port 0x04.1
|
||||
*
|
||||
* 15: 1=RX receiving (RO). Set when a packet is being received
|
||||
* into the RX FIFO.
|
||||
* 14: Reserved
|
||||
* 13: 1=RX underrun (RO). Generates Adapter Failure interrupt.
|
||||
* Requires RX Reset or Global Reset command to recover.
|
||||
* It is generated when you read past the end of a packet -
|
||||
* reading past what has been received so far will give bad
|
||||
* data.
|
||||
* 12: 1=RX status overrun (RO). Set when there are already 8
|
||||
* packets in the RX FIFO. While this bit is set, no additional
|
||||
* packets are received. Requires no action on the part of
|
||||
* the host. The condition is cleared once a packet has been
|
||||
* read out of the RX FIFO.
|
||||
* 11: 1=RX overrun (RO). Set when the RX FIFO is full (there
|
||||
* may not be an overrun packet yet). While this bit is set,
|
||||
* no additional packets will be received (some additional
|
||||
* bytes can still be pending between the wire and the RX
|
||||
* FIFO). Requires no action on the part of the host. The
|
||||
* condition is cleared once a few bytes have been read out
|
||||
* from the RX FIFO.
|
||||
* 10: 1=TX overrun (RO). Generates adapter failure interrupt.
|
||||
* Requires TX Reset or Global Reset command to recover.
|
||||
* Disables Transmitter.
|
||||
* 9-8: Unassigned.
|
||||
* 7-0: Built in self test bits for the RX and TX FIFO's.
|
||||
*/
|
||||
#define FIFOS_RX_RECEIVING (unsigned short) 0x8000
|
||||
#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000
|
||||
#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000
|
||||
#define FIFOS_RX_OVERRUN (unsigned short) 0x0800
|
||||
#define FIFOS_TX_OVERRUN (unsigned short) 0x0400
|
||||
|
||||
/*
|
||||
* Misc defines for various things.
|
||||
*/
|
||||
#define TAG_ADAPTER 0xd0
|
||||
#define ACTIVATE_ADAPTER_TO_CONFIG 0xff
|
||||
#define ENABLE_DRQ_IRQ 0x0001
|
||||
#define MFG_ID 0x506d /* `TCM' */
|
||||
#define PROD_ID 0x5090
|
||||
#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
|
||||
#define JABBER_GUARD_ENABLE 0x40
|
||||
#define LINKBEAT_ENABLE 0x80
|
||||
#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
|
||||
#define DISABLE_UTP 0x0
|
||||
#define RX_BYTES_MASK (unsigned short) (0x07ff)
|
||||
#define RX_ERROR 0x4000
|
||||
#define RX_INCOMPLETE 0x8000
|
||||
#define TX_INDICATE 1<<15
|
||||
#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY)
|
||||
|
||||
#define VX_IOSIZE 0x20
|
||||
|
||||
#define VX_CONNECTORS 8
|
||||
|
||||
/*
|
||||
* Local variables:
|
||||
* c-basic-offset: 8
|
||||
* End:
|
||||
*/
|
||||
|
|
@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB := $(obj)libnet.o
|
||||
|
||||
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
|
||||
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
|
||||
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
|
||||
COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
|
||||
|
|
|
|||
Loading…
Reference in New Issue