zynq: Move bootmode to headers
These numbers will be reused by SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -21,6 +21,12 @@
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#define ZYNQ_SPI_BASEADDR1 0xE0007000
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#define ZYNQ_SPI_BASEADDR1 0xE0007000
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#define ZYNQ_DDRC_BASEADDR 0xF8006000
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#define ZYNQ_DDRC_BASEADDR 0xF8006000
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/* Bootmode setting values */
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#define ZYNQ_BM_MASK 0xF
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#define ZYNQ_BM_NOR 0x2
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#define ZYNQ_BM_SD 0x5
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#define ZYNQ_BM_JTAG 0x0
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/* Reflect slcr offsets */
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/* Reflect slcr offsets */
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struct slcr_regs {
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struct slcr_regs {
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u32 scl; /* 0x0 */
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u32 scl; /* 0x0 */
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@ -12,12 +12,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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/* Bootmode setting values */
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#define ZYNQ_BM_MASK 0x0F
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#define ZYNQ_BM_NOR 0x02
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#define ZYNQ_BM_SD 0x05
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#define ZYNQ_BM_JTAG 0x0
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#ifdef CONFIG_FPGA
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#ifdef CONFIG_FPGA
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Xilinx_desc fpga;
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Xilinx_desc fpga;
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