mpc832x: add support for the mpc8321 based suvd3 board
- serial console on UART1 - Ethernet RMII over UCC4 - PHY SMSC LAN8700 - 64MB Flash - 128 MB DDR2 RAM - I2C - bootcount This board is similiar to the kmeter1 (8360) board, so common config options are extracted into the include/configs/km83xx-common.h file. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
This commit is contained in:
Heiko Schocher
Wolfgang Denk
parent
de3ad13de5
commit
62ddcf05e7
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@ -433,6 +433,7 @@ Heiko Schocher <hs@denx.de>
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municse MPC5200
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sc3 PPC405GP
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suen3 ARM926EJS (Kirkwood SoC)
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suvd3 MPC8321
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uc101 MPC5200
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ve8313 MPC8313
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@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
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#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
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(defined(CONFIG_QE))
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#include <asm/immap_qe.h>
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void fdt_fixup_muram (void *blob)
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@ -51,7 +51,7 @@
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#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
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#endif /* defined(CONFIG_MPC8260) */
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#if defined(CONFIG_MPC8360)
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#if defined(CONFIG_QE)
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#include <asm/immap_qe.h>
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#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
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@ -29,6 +29,7 @@
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#include <malloc.h>
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#include <hush.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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@ -402,7 +403,7 @@ static void setports(int gpio)
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#endif
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#endif
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#if !defined(CONFIG_KMETER1)
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#if !defined(CONFIG_MPC83xx)
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static void writeStartSeq(void)
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{
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set_sda(1);
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@ -461,7 +462,7 @@ static int i2c_make_abort(void)
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*/
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void i2c_init_board(void)
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{
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#if defined(CONFIG_KMETER1)
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#if defined(CONFIG_MPC83xx)
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struct fsl_i2c *dev;
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dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
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uchar dummy;
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@ -573,6 +574,7 @@ int board_eth_init(bd_t *bis)
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(void)keymile_hdlc_enet_initialize(bis);
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#endif
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if (ethernet_present())
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return -1;
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return 0;
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return cpu_eth_init(bis);
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return -1;
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}
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@ -8,7 +8,7 @@
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2008
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* (C) Copyright 2008 - 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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@ -32,7 +32,7 @@
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* port pin dir open_drain assign */
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#if defined(CONFIG_KMETER1)
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/* MDIO */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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@ -55,6 +55,40 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
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{5, 2, 1, 0, 1}, /* UART2_RTS */
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{5, 3, 2, 0, 2}, /* UART2_SIN */
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{5, 1, 2, 0, 3}, /* UART2_CTS */
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#else
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/* Local Bus */
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{0, 16, 1, 0, 3}, /* LA00 */
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{0, 17, 1, 0, 3}, /* LA01 */
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{0, 18, 1, 0, 3}, /* LA02 */
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{0, 19, 1, 0, 3}, /* LA03 */
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{0, 20, 1, 0, 3}, /* LA04 */
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{0, 21, 1, 0, 3}, /* LA05 */
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{0, 22, 1, 0, 3}, /* LA06 */
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{0, 23, 1, 0, 3}, /* LA07 */
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{0, 24, 1, 0, 3}, /* LA08 */
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{0, 25, 1, 0, 3}, /* LA09 */
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{0, 26, 1, 0, 3}, /* LA10 */
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{0, 27, 1, 0, 3}, /* LA11 */
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{0, 28, 1, 0, 3}, /* LA12 */
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{0, 29, 1, 0, 3}, /* LA13 */
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{0, 30, 1, 0, 3}, /* LA14 */
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{0, 31, 1, 0, 3}, /* LA15 */
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/* MDIO */
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{3, 4, 3, 0, 2}, /* MDIO */
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{3, 5, 1, 0, 2}, /* MDC */
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/* UCC4 - UEC */
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{1, 18, 1, 0, 1}, /* TxD0 */
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{1, 19, 1, 0, 1}, /* TxD1 */
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{1, 22, 2, 0, 1}, /* RxD0 */
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{1, 23, 2, 0, 1}, /* RxD1 */
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{1, 26, 2, 0, 1}, /* RxER */
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{1, 28, 2, 0, 1}, /* Rx_DV */
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{1, 30, 1, 0, 1}, /* TxEN */
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{1, 31, 2, 0, 1}, /* CRS */
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{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
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#endif
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/* END of table */
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{0, 0, 0, 0, QE_IOP_TAB_END},
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@ -77,11 +111,38 @@ static int board_init_i2c_busses(void)
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return 0;
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}
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#if defined(CONFIG_SUVD3)
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const uint upma_table[] = {
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0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
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0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
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0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
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0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
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};
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#endif
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int board_early_init_r(void)
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{
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struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;
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unsigned short svid;
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#if defined(CONFIG_SUVD3)
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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fsl_lbc_t *lbc = &immap->im_lbc;
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u32 *mxmr = &lbc->mamr;
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#endif
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#if defined(CONFIG_MPC8360)
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unsigned short svid;
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/*
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* Because of errata in the UCCs, we have to write to the reserved
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* registers to slow the clocks down.
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@ -105,13 +166,19 @@ int board_early_init_r(void)
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0x00000050, 0x000000a0);
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break;
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}
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#endif
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/* enable the PHY on the PIGGY */
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setbits_8(&base->pgy_eth, 0x01);
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/* enable the Unit LED (green) */
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setbits_8(&base->oprth, WRL_BOOT);
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/* take FE/GbE PHYs out of reset */
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setbits_8(&base->prst, 0x1c);
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#if defined(CONFIG_SUVD3)
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/* configure UPMA for APP1 */
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upmconfig(UPMA, (uint *) upma_table,
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sizeof(upma_table) / sizeof(uint));
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out_be32(mxmr, CONFIG_SYS_MAMR);
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#endif
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return 0;
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}
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@ -185,12 +252,13 @@ phys_size_t initdram(int board_type)
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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puts("Board: Keymile kmeter1");
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puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
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if (ethernet_present())
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puts(" with PIGGY.");
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puts("\n");
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@ -198,19 +266,9 @@ int checkboard(void)
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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/*
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* update property in the blob
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*/
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void ft_blob_update(void *blob, bd_t *bd)
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{
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/* no board specific update */
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup (blob, bd);
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ft_blob_update (blob, bd);
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ft_cpu_setup(blob, bd);
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}
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#endif
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@ -486,10 +486,11 @@ MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freesca
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MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
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MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
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MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
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kmeter1 powerpc mpc83xx kmeter1 keymile
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kmeter1 powerpc mpc83xx km83xx keymile
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MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
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SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
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SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
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suvd3 powerpc mpc83xx km83xx keymile
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TQM834x powerpc mpc83xx tqm834x tqc
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sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
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sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
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@ -0,0 +1,324 @@
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/*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_KM83XX_H
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#define __CONFIG_KM83XX_H
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/* include common defines/options for all Keymile boards */
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#include "keymile-common.h"
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#include "km-powerpc.h"
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#define MTDIDS_DEFAULT "nor0=boot"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"boot:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
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#define CONFIG_MISC_INIT_R
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/*
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* System Clock Setup
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*/
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#define CONFIG_83XX_CLKIN 66000000
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CFG_83XX_DDR_USES_CS0
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/*
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* Manually set up DDR parameters
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*/
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#define CONFIG_DDR_II
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#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_FLASH_BASE 0xF0000000
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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/* Reserve 768 kB for Mon */
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 0 Local GPCM 16 bit 256MB FLASH
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* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
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*
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*/
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_5 | \
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OR_GPCM_TRLX | OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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/*
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* PRIO1/PIGGY on the local bus CS1
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*/
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
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(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
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BR_V)
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX | OR_GPCM_EAD)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI
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#endif
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_UEC_ETH
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#define CONFIG_ETHPRIME "UEC0"
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#define CONFIG_UEC_ETH1 /* GETH1 */
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#define UEC_VERBOSE_DEBUG 1
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#ifdef CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
|
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
|
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
#else /* CFG_SYS_RAMBOOT */
|
||||
#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif /* CFG_SYS_RAMBOOT */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#define CONFIG_NAND_KMETER1
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*
|
||||
* Core HID Setup
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
||||
HID0_ENABLE_INSTRUCTION_CACHE)
|
||||
#define CONFIG_SYS_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||
|
||||
/* DDR: cache cacheable */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
|
||||
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define BOOTFLASH_START 0xF0000000
|
||||
|
||||
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
|
||||
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_KM_DEF_ROOTPATH
|
||||
#define CONFIG_KM_DEF_ROOTPATH \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_KM_DEF_ENV \
|
||||
CONFIG_KM_DEF_ROOTPATH \
|
||||
"dtt_bus=pca9547:70:a\0" \
|
||||
"EEprom_ivm=pca9547:70:9\0" \
|
||||
"newenv=" \
|
||||
"prot off 0xF00C0000 +0x40000 && " \
|
||||
"era 0xF00C0000 +0x40000\0" \
|
||||
"unlock=yes\0" \
|
||||
""
|
||||
|
||||
#if defined(CONFIG_UEC_ETH)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_KM83XX_H */
|
||||
|
|
@ -27,30 +27,20 @@
|
|||
#define CONFIG_MPC8360 /* MPC8360 CPU specific */
|
||||
#define CONFIG_KMETER1 /* KMETER1 board specific */
|
||||
#define CONFIG_HOSTNAME kmeter1
|
||||
#define CONFIG_KM_BOARD_NAME "kmeter1"
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
||||
#define CONFIG_KM_DEF_NETDEV \
|
||||
"netdev=eth2\0" \
|
||||
|
||||
/* include common defines/options for all Keymile boards */
|
||||
#include "keymile-common.h"
|
||||
#include "km-powerpc.h"
|
||||
|
||||
#define MTDIDS_DEFAULT "nor0=boot"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=" \
|
||||
"boot:" \
|
||||
"768k(u-boot)," \
|
||||
"128k(env)," \
|
||||
"128k(envred)," \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
|
||||
/* include common defines/options for all 83xx Keymile boards */
|
||||
#include "km83xx-common.h"
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
/*
|
||||
* System Clock Setup
|
||||
* System IO Setup
|
||||
*/
|
||||
#define CONFIG_83XX_CLKIN 66000000
|
||||
#define CONFIG_SYS_CLK_FREQ 66000000
|
||||
#define CONFIG_83XX_PCICLK 66000000
|
||||
#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
|
|
@ -71,55 +61,7 @@
|
|||
HRCWH_LALE_EARLY | \
|
||||
HRCWH_LDP_CLEAR )
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CONFIG_SYS_SICRH 0x00000006
|
||||
#define CONFIG_SYS_SICRL 0x00000000
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
/*
|
||||
* Bus Arbitration Configuration Register (ACR)
|
||||
*/
|
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
|
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
|
||||
#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
|
||||
#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
#define CFG_83XX_DDR_USES_CS0
|
||||
|
||||
#undef CONFIG_DDR_ECC
|
||||
|
||||
/*
|
||||
* DDRCDR - DDR Control Driver Register
|
||||
*/
|
||||
|
||||
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CONFIG_DDR_II
|
||||
#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
|
||||
CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10 | \
|
||||
CSCONFIG_ODT_WR_ACS)
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
|
||||
SDRAM_CFG_SREN)
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
||||
|
|
@ -127,6 +69,11 @@
|
|||
#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
|
||||
(0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
|
||||
CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10 | \
|
||||
CSCONFIG_ODT_WR_ACS)
|
||||
|
||||
#define CONFIG_SYS_DDRCDR 0x40000001
|
||||
#define CONFIG_SYS_DDR_MODE 0x47860452
|
||||
#define CONFIG_SYS_DDR_MODE2 0x8080c000
|
||||
|
|
@ -159,32 +106,13 @@
|
|||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xF0000000
|
||||
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
|
||||
#define CONFIG_SYS_PIGGY_SIZE 128
|
||||
#define CONFIG_SYS_PAXE_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PAXE_SIZE 512
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve for Mon */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
/* EEprom support */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
|
|
@ -198,52 +126,9 @@
|
|||
*
|
||||
* Bank Bus Machine PortSz Size Device
|
||||
* ---- --- ------- ------ ----- ------
|
||||
* 0 Local GPCM 16 bit 256MB FLASH
|
||||
* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
|
||||
* 3 Local GPCM 8 bit 512MB PAXE
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_5 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
/* max num of sects on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
|
||||
/*
|
||||
* PRIO1/PIGGY on the local bus CS1
|
||||
*/
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
|
||||
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EAD)
|
||||
|
||||
/*
|
||||
* PAXE on the local bus CS3
|
||||
|
|
@ -259,177 +144,15 @@
|
|||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EAD)
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
||||
|
||||
/* Pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#undef CONFIG_PCI /* No PCI */
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI
|
||||
#endif
|
||||
/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#define CONFIG_ETHPRIME "UEC0"
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */
|
||||
#define UEC_VERBOSE_DEBUG 1
|
||||
|
||||
#ifdef CONFIG_UEC_ETH1
|
||||
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
|
||||
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII */
|
||||
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
#else /* CFG_RAMBOOT */
|
||||
#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
#define CONFIG_I2C_MUX 1
|
||||
|
||||
/* EEprom support */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#define CONFIG_NAND_KMETER1
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
||||
|
||||
/*
|
||||
* Core HID Setup
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT 0x000000000
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
||||
HID0_ENABLE_INSTRUCTION_CACHE)
|
||||
#define CONFIG_SYS_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
#define CONFIG_HIGH_BATS /* High BATs supported */
|
||||
|
||||
/* DDR: cache cacheable */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \
|
||||
BATU_VP)
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
|
||||
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||
|
||||
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
|
|
@ -457,31 +180,4 @@
|
|||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#define BOOTFLASH_START F0000000
|
||||
|
||||
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
|
||||
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_KM_DEF_ENV \
|
||||
"dtt_bus=pca9547:70:a\0" \
|
||||
"EEprom_ivm=pca9547:70:9\0" \
|
||||
"newenv=" \
|
||||
"prot off 0xF00C0000 +0x40000 && " \
|
||||
"era 0xF00C0000 +0x40000\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"unlock=yes\0" \
|
||||
""
|
||||
|
||||
#if defined(CONFIG_UEC_ETH)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* Copyright (C) 2007 Logic Product Development, Inc.
|
||||
* Peter Barada <peterb@logicpd.com>
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_QE /* Has QE */
|
||||
#define CONFIG_MPC832x /* MPC832x CPU specific */
|
||||
#define CONFIG_SUVD3 /* SUVD3 board specific */
|
||||
#define CONFIG_HOSTNAME suvd3
|
||||
#define CONFIG_KM_BOARD_NAME "suvd3"
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
||||
#define CONFIG_KM_DEF_NETDEV \
|
||||
"netdev=eth0\0"
|
||||
|
||||
#define CONFIG_KM_DEF_ROOTPATH \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0"
|
||||
|
||||
/* include common defines/options for all 83xx Keymile boards */
|
||||
#include "km83xx-common.h"
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
*/
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 | \
|
||||
HRCWL_CSB_TO_CLKIN_2X1 | \
|
||||
HRCWL_CORE_TO_CSB_2_5X1 | \
|
||||
HRCWL_CE_PLL_VCO_DIV_2 | \
|
||||
HRCWL_CE_TO_PLL_1X3)
|
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH (\
|
||||
HRCWH_PCI_AGENT | \
|
||||
HRCWH_PCI_ARBITER_DISABLE | \
|
||||
HRCWH_CORE_ENABLE | \
|
||||
HRCWH_FROM_0X00000100 | \
|
||||
HRCWH_BOOTSEQ_DISABLE | \
|
||||
HRCWH_SW_WATCHDOG_DISABLE | \
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT | \
|
||||
HRCWH_BIG_ENDIAN | \
|
||||
HRCWH_LALE_NORMAL)
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
|
||||
SDRAM_CFG_32_BE | \
|
||||
SDRAM_CFG_SREN)
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
||||
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
|
||||
(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
|
||||
CSCONFIG_ODT_WR_CFG | \
|
||||
CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10)
|
||||
|
||||
#define CONFIG_SYS_DDR_MODE 0x47860252
|
||||
#define CONFIG_SYS_DDR_MODE2 0x8080c000
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
|
||||
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
|
||||
(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
|
||||
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WWT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RWT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
|
||||
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
|
||||
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
|
||||
(2 << TIMING_CFG1_WRREC_SHIFT) | \
|
||||
(6 << TIMING_CFG1_REFREC_SHIFT) | \
|
||||
(2 << TIMING_CFG1_ACTTORW_SHIFT) | \
|
||||
(6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
|
||||
(2 << TIMING_CFG1_PRETOACT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
|
||||
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
|
||||
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
|
||||
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
|
||||
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
|
||||
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
|
||||
(5 << TIMING_CFG2_CPO_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
|
||||
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
|
||||
#define CONFIG_SYS_PIGGY_SIZE 128
|
||||
#define CONFIG_SYS_APP1_BASE 0xA0000000
|
||||
#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
|
||||
#define CONFIG_SYS_APP2_BASE 0xB0000000
|
||||
#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
|
||||
|
||||
/* EEprom support */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
/*
|
||||
* Init Local Bus Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Size Device
|
||||
* ---- --- ------- ------ ----- ------
|
||||
* 2 Local UPMA 16 bit 256MB APP1
|
||||
* 3 Local GPCM 16 bit 256MB APP2
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* APP1 on the local bus CS2
|
||||
*/
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
|
||||
BR_PS_16 | \
|
||||
BR_MS_UPMA | \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
|
||||
BR_PS_16 | \
|
||||
BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
|
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_3 | \
|
||||
OR_GPCM_TRLX)
|
||||
|
||||
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
|
||||
0x0000c000 | \
|
||||
MxMR_WLFx_2X)
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
|
||||
/* APP1: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI MEM space: cacheable */
|
||||
#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
/* PCI MMIO space: cache-inhibit and guarded */
|
||||
#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
#else /* CONFIG_PCI */
|
||||
|
||||
/* APP2: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
|
||||
#define CONFIG_SYS_IBAT7L (0)
|
||||
#define CONFIG_SYS_IBAT7U (0)
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue